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[/] [ethernet_tri_mode/] [trunk/] [rtl/] [verilog/] [RMON/] [RMON_dpram.v] - Diff between revs 7 and 33

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Rev 7 Rev 33
module RMON_dpram(
module RMON_dpram(
Reset   ,
Reset   ,
Clk     ,
Clk     ,
//port-a for Rmon 
//port-a for Rmon 
Addra,
Addra,
Dina,
Dina,
Douta,
Douta,
Wea,
Wea,
//port-b for CPU  
//port-b for CPU  
Addrb,
Addrb,
Doutb
Doutb
);
);
 
 
input           Reset   ;
input           Reset   ;
input           Clk     ;
input           Clk     ;
                //port-a for Rmon  
                //port-a for Rmon  
input   [5:0]   Addra;
input   [5:0]   Addra;
input   [31:0]  Dina;
input   [31:0]  Dina;
output  [31:0]  Douta;
output  [31:0]  Douta;
input           Wea;
input           Wea;
                //port-b for CPU
                //port-b for CPU
input   [5:0]   Addrb;
input   [5:0]   Addrb;
output  [31:0]  Doutb;
output  [31:0]  Doutb;
//******************************************************************************
//******************************************************************************
//internal signals                                                              
//internal signals                                                              
//******************************************************************************
//******************************************************************************
 
 
wire            Clka;
wire            Clka;
wire            Clkb;
wire            Clkb;
assign          Clka=Clk;
assign          Clka=Clk;
assign  #2      Clkb=Clk;
assign  #2      Clkb=Clk;
//******************************************************************************
//******************************************************************************
 
 
duram #(32,6,"M4K") U_duram(
duram #(32,6,"M4K") U_duram(
.data_a         (Dina           ),
.data_a         (Dina           ),
.data_b         (32'b0          ),
.data_b         (32'b0          ),
.wren_a         (Wea            ),
.wren_a         (Wea            ),
.wren_b         (1'b0           ),
.wren_b         (1'b0           ),
.address_a      (Addra          ),
.address_a      (Addra          ),
.address_b      (Addrb          ),
.address_b      (Addrb          ),
.clock_a        (Clka           ),
.clock_a        (Clka           ),
.clock_b        (Clkb           ),
.clock_b        (Clkb           ),
.q_a            (Douta          ),
.q_a            (Douta          ),
.q_b            (Doutb          ));
.q_b            (Doutb          ));
 
 
 
 

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