module afifo(
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module afifo(
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din,
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din,
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wr_en,
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wr_en,
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wr_clk,
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wr_clk,
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rd_en,
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rd_en,
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rd_clk,
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rd_clk,
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ainit,
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ainit,
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dout,
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dout,
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full,
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full,
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almost_full,
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almost_full,
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empty,
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empty,
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wr_count,
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wr_count,
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rd_count,
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rd_count,
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rd_ack,
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rd_ack,
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wr_ack);
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wr_ack);
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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parameter DATA_WIDTH =16;
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parameter DATA_WIDTH =16;
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parameter ADDR_WIDTH =8;
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parameter ADDR_WIDTH =8;
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parameter COUNT_DATA_WIDTH =8;
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parameter COUNT_DATA_WIDTH =8;
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parameter ALMOST_FULL_DEPTH =8;
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parameter ALMOST_FULL_DEPTH =8;
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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input [DATA_WIDTH-1:0] din;
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input [DATA_WIDTH-1:0] din;
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input wr_en;
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input wr_en;
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input wr_clk;
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input wr_clk;
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input rd_en;
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input rd_en;
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input rd_clk;
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input rd_clk;
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input ainit;
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input ainit;
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output [DATA_WIDTH-1:0] dout;
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output [DATA_WIDTH-1:0] dout;
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output full;
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output full;
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output almost_full;
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output almost_full;
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output empty;
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output empty;
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output [COUNT_DATA_WIDTH-1:0] wr_count /* synthesis syn_keep=1 */;
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output [COUNT_DATA_WIDTH-1:0] wr_count /* synthesis syn_keep=1 */;
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output [COUNT_DATA_WIDTH-1:0] rd_count /* synthesis syn_keep=1 */;
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output [COUNT_DATA_WIDTH-1:0] rd_count /* synthesis syn_keep=1 */;
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output rd_ack;
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output rd_ack;
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output wr_ack;
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output wr_ack;
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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//local signals
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//local signals
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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reg [ADDR_WIDTH-1:0] Add_wr;
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reg [ADDR_WIDTH-1:0] Add_wr;
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reg [ADDR_WIDTH-1:0] Add_wr_ungray;
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reg [ADDR_WIDTH-1:0] Add_wr_ungray;
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reg [ADDR_WIDTH-1:0] Add_wr_gray;
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reg [ADDR_WIDTH-1:0] Add_wr_gray;
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reg [ADDR_WIDTH-1:0] Add_wr_gray_dl1;
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reg [ADDR_WIDTH-1:0] Add_wr_gray_dl1;
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reg [ADDR_WIDTH-1:0] Add_rd;
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reg [ADDR_WIDTH-1:0] Add_rd;
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wire [ADDR_WIDTH-1:0] Add_rd_pluse;
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wire [ADDR_WIDTH-1:0] Add_rd_pluse;
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reg [ADDR_WIDTH-1:0] Add_rd_gray;
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reg [ADDR_WIDTH-1:0] Add_rd_gray;
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reg [ADDR_WIDTH-1:0] Add_rd_gray_dl1;
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reg [ADDR_WIDTH-1:0] Add_rd_gray_dl1;
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reg [ADDR_WIDTH-1:0] Add_rd_ungray;
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reg [ADDR_WIDTH-1:0] Add_rd_ungray;
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wire [ADDR_WIDTH-1:0] Add_wr_pluse;
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wire [ADDR_WIDTH-1:0] Add_wr_pluse;
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integer i;
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integer i;
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reg full /* synthesis syn_keep=1 */;
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reg full /* synthesis syn_keep=1 */;
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reg empty;
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reg empty;
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wire [ADDR_WIDTH-1:0] ff_used_wr;
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wire [ADDR_WIDTH-1:0] ff_used_wr;
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wire [ADDR_WIDTH-1:0] ff_used_rd;
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wire [ADDR_WIDTH-1:0] ff_used_rd;
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reg rd_ack;
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reg rd_ack;
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reg rd_ack_tmp;
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reg rd_ack_tmp;
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reg almost_full;
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reg almost_full;
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wire [DATA_WIDTH-1:0] dout_tmp;
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wire [DATA_WIDTH-1:0] dout_tmp;
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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//Write clock domain
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//Write clock domain
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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assign wr_ack =0;
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assign wr_ack =0;
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assign ff_used_wr =Add_wr-Add_rd_ungray;
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assign ff_used_wr =Add_wr-Add_rd_ungray;
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assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
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assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
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always @ (posedge ainit or posedge wr_clk)
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always @ (posedge ainit or posedge wr_clk)
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if (ainit)
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if (ainit)
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Add_wr_gray <=0;
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Add_wr_gray <=0;
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else
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else
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begin
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begin
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Add_wr_gray[ADDR_WIDTH-1] <=Add_wr[ADDR_WIDTH-1];
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Add_wr_gray[ADDR_WIDTH-1] <=Add_wr[ADDR_WIDTH-1];
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for (i=ADDR_WIDTH-2;i>=0;i=i-1)
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for (i=ADDR_WIDTH-2;i>=0;i=i-1)
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Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
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Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
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end
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end
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//读地址进行反gray编码.
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//读地址进行反gray编码.
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always @ (posedge wr_clk or posedge ainit)
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always @ (posedge wr_clk or posedge ainit)
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if (ainit)
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if (ainit)
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Add_rd_gray_dl1 <=0;
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Add_rd_gray_dl1 <=0;
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else
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else
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Add_rd_gray_dl1 <=Add_rd_gray;
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Add_rd_gray_dl1 <=Add_rd_gray;
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always @ (posedge wr_clk or posedge ainit)
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always @ (posedge wr_clk or posedge ainit)
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if (ainit)
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if (ainit)
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Add_rd_ungray =0;
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Add_rd_ungray =0;
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else
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else
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begin
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begin
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Add_rd_ungray[ADDR_WIDTH-1] =Add_rd_gray_dl1[ADDR_WIDTH-1];
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Add_rd_ungray[ADDR_WIDTH-1] =Add_rd_gray_dl1[ADDR_WIDTH-1];
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for (i=ADDR_WIDTH-2;i>=0;i=i-1)
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for (i=ADDR_WIDTH-2;i>=0;i=i-1)
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Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
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Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
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end
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end
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assign Add_wr_pluse=Add_wr+1;
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assign Add_wr_pluse=Add_wr+1;
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/*
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/*
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always @ (Add_wr_pluse or Add_rd_ungray)
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always @ (Add_wr_pluse or Add_rd_ungray)
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if (Add_wr_pluse==Add_rd_ungray)
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if (Add_wr_pluse==Add_rd_ungray)
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full =1;
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full =1;
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else
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else
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full =0;
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full =0;
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*/
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*/
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always @ (posedge wr_clk or posedge ainit)
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always @ (posedge wr_clk or posedge ainit)
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if (ainit)
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if (ainit)
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full <=0;
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full <=0;
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else if(Add_wr_pluse==Add_rd_ungray&&wr_en)
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else if(Add_wr_pluse==Add_rd_ungray&&wr_en)
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full <=1;
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full <=1;
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else if(Add_wr!=Add_rd_ungray)
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else if(Add_wr!=Add_rd_ungray)
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full <=0;
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full <=0;
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always @ (posedge wr_clk or posedge ainit)
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always @ (posedge wr_clk or posedge ainit)
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if (ainit)
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if (ainit)
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almost_full <=0;
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almost_full <=0;
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else if (wr_count>=ALMOST_FULL_DEPTH)
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else if (wr_count>=ALMOST_FULL_DEPTH)
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almost_full <=1;
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almost_full <=1;
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else
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else
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almost_full <=0;
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almost_full <=0;
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always @ (posedge wr_clk or posedge ainit)
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always @ (posedge wr_clk or posedge ainit)
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if (ainit)
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if (ainit)
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Add_wr <=0;
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Add_wr <=0;
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else if (wr_en&&!full)
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else if (wr_en&&!full)
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Add_wr <=Add_wr +1;
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Add_wr <=Add_wr +1;
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//******************************************************************************
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//******************************************************************************
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//read clock domain
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//read clock domain
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//******************************************************************************
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//******************************************************************************
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always @ (posedge rd_clk or posedge ainit)
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always @ (posedge rd_clk or posedge ainit)
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if (ainit)
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if (ainit)
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rd_ack <=0;
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rd_ack <=0;
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else if (rd_en&&!empty)
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else if (rd_en&&!empty)
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rd_ack <=1;
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rd_ack <=1;
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else
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else
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rd_ack <=0;
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rd_ack <=0;
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assign ff_used_rd =Add_wr_ungray-Add_rd;
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assign ff_used_rd =Add_wr_ungray-Add_rd;
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assign rd_count =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
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assign rd_count =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
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assign Add_rd_pluse =Add_rd+1;
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assign Add_rd_pluse =Add_rd+1;
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always @ (posedge rd_clk or posedge ainit)
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always @ (posedge rd_clk or posedge ainit)
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if (ainit)
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if (ainit)
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Add_rd <=0;
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Add_rd <=0;
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else if (rd_en&&!empty) //出EOP后就不读了。
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else if (rd_en&&!empty) //出EOP后就不读了。
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Add_rd <=Add_rd + 1;
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Add_rd <=Add_rd + 1;
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//读地址进行gray码变换.
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//读地址进行gray码变换.
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always @ (posedge ainit or posedge rd_clk)
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always @ (posedge ainit or posedge rd_clk)
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if (ainit)
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if (ainit)
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Add_rd_gray <=0;
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Add_rd_gray <=0;
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else
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else
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begin
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begin
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Add_rd_gray[ADDR_WIDTH-1] <=Add_rd[ADDR_WIDTH-1];
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Add_rd_gray[ADDR_WIDTH-1] <=Add_rd[ADDR_WIDTH-1];
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for (i=ADDR_WIDTH-2;i>=0;i=i-1)
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for (i=ADDR_WIDTH-2;i>=0;i=i-1)
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Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
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Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
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end
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end
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/* Add_rd_gray <={ Add_rd[8],
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/* Add_rd_gray <={ Add_rd[8],
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Add_rd[8]^Add_rd[7],
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Add_rd[8]^Add_rd[7],
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Add_rd[7]^Add_rd[6],
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Add_rd[7]^Add_rd[6],
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Add_rd[6]^Add_rd[5],
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Add_rd[6]^Add_rd[5],
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Add_rd[5]^Add_rd[4],
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Add_rd[5]^Add_rd[4],
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Add_rd[4]^Add_rd[3],
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Add_rd[4]^Add_rd[3],
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Add_rd[3]^Add_rd[2],
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Add_rd[3]^Add_rd[2],
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Add_rd[2]^Add_rd[1],
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Add_rd[2]^Add_rd[1],
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Add_rd[1]^Add_rd[0]};
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Add_rd[1]^Add_rd[0]};
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*/
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*/
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//写地址进行反gray编码.
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//写地址进行反gray编码.
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always @ (posedge rd_clk or posedge ainit)
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always @ (posedge rd_clk or posedge ainit)
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if (ainit)
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if (ainit)
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Add_wr_gray_dl1 <=0;
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Add_wr_gray_dl1 <=0;
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else
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else
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Add_wr_gray_dl1 <=Add_wr_gray;
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Add_wr_gray_dl1 <=Add_wr_gray;
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always @ (posedge rd_clk or posedge ainit)
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always @ (posedge rd_clk or posedge ainit)
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if (ainit)
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if (ainit)
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Add_wr_ungray =0;
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Add_wr_ungray =0;
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else
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else
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begin
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begin
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Add_wr_ungray[ADDR_WIDTH-1] =Add_wr_gray_dl1[ADDR_WIDTH-1];
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Add_wr_ungray[ADDR_WIDTH-1] =Add_wr_gray_dl1[ADDR_WIDTH-1];
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for (i=ADDR_WIDTH-2;i>=0;i=i-1)
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for (i=ADDR_WIDTH-2;i>=0;i=i-1)
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Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
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Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
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end
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end
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/* Add_wr_ungray <={
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/* Add_wr_ungray <={
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Add_wr_gray_dl1[8],
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Add_wr_gray_dl1[8],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
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Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
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*/
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*/
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//empty信号产生
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//empty信号产生
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/*
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/*
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always @ (Add_rd or Add_wr_ungray)
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always @ (Add_rd or Add_wr_ungray)
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if (Add_rd==Add_wr_ungray)
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if (Add_rd==Add_wr_ungray)
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empty =1;
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empty =1;
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else
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else
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empty =0;
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empty =0;
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*/
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*/
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always @ (posedge rd_clk or posedge ainit)
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always @ (posedge rd_clk or posedge ainit)
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if (ainit)
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if (ainit)
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empty <=1;
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empty <=1;
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else if (Add_rd_pluse==Add_wr_ungray&&rd_en)
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else if (Add_rd_pluse==Add_wr_ungray&&rd_en)
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empty <=1;
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empty <=1;
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else if (Add_rd!=Add_wr_ungray)
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else if (Add_rd!=Add_wr_ungray)
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empty <=0;
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empty <=0;
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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//instant need change for your own dpram
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//instant need change for your own dpram
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//////////////////////////////////////////////////////
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//////////////////////////////////////////////////////
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duram #(
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duram #(
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DATA_WIDTH,
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DATA_WIDTH,
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ADDR_WIDTH
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ADDR_WIDTH
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)
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)
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U_duram (
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U_duram (
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.data_a (din ),
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.data_a (din ),
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.wren_a (wr_en ),
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.wren_a (wr_en ),
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.address_a (Add_wr ),
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.address_a (Add_wr ),
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.address_b (Add_rd ),
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.address_b (Add_rd ),
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.clock_a (wr_clk ),
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.clock_a (wr_clk ),
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.clock_b (rd_clk ),
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.clock_b (rd_clk ),
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.q_b (dout ));
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.q_b (dout ));
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