//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth_defines.v ////
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//// eth_defines.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2002/02/26 16:11:32 mohor
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// Number of interrupts changed
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//
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// Revision 1.14 2002/02/16 14:03:44 mohor
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// Revision 1.14 2002/02/16 14:03:44 mohor
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// Registered trimmed. Unused registers removed.
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// Registered trimmed. Unused registers removed.
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//
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//
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// Revision 1.13 2002/02/16 13:06:33 mohor
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// Revision 1.13 2002/02/16 13:06:33 mohor
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// EXTERNAL_DMA used instead of WISHBONE_DMA.
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// EXTERNAL_DMA used instead of WISHBONE_DMA.
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//
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//
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// Revision 1.12 2002/02/15 10:58:31 mohor
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// Revision 1.12 2002/02/15 10:58:31 mohor
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// Changed that were lost with last update put back to the file.
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// Changed that were lost with last update put back to the file.
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//
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//
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// Revision 1.11 2002/02/14 20:19:41 billditt
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// Revision 1.11 2002/02/14 20:19:41 billditt
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// Modified for Address Checking,
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// Modified for Address Checking,
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// addition of eth_addrcheck.v
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// addition of eth_addrcheck.v
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//
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//
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// Revision 1.10 2002/02/12 17:01:19 mohor
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// Revision 1.10 2002/02/12 17:01:19 mohor
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// HASH0 and HASH1 registers added.
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// HASH0 and HASH1 registers added.
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// Revision 1.9 2002/02/08 16:21:54 mohor
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// Revision 1.9 2002/02/08 16:21:54 mohor
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// Rx status is written back to the BD.
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// Rx status is written back to the BD.
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//
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//
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// Revision 1.8 2002/02/05 16:44:38 mohor
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// Revision 1.8 2002/02/05 16:44:38 mohor
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// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
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// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
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// MHz. Statuses, overrun, control frame transmission and reception still need
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// MHz. Statuses, overrun, control frame transmission and reception still need
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// to be fixed.
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// to be fixed.
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//
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//
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// Revision 1.7 2002/01/23 10:28:16 mohor
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// Revision 1.7 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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// Link in the header changed.
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//
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//
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// Revision 1.6 2001/12/05 15:00:16 mohor
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// Revision 1.6 2001/12/05 15:00:16 mohor
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// instead of the number of RX descriptors).
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// instead of the number of RX descriptors).
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//
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//
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// Revision 1.5 2001/12/05 10:21:37 mohor
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// Revision 1.5 2001/12/05 10:21:37 mohor
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// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
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// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
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//
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//
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// Revision 1.4 2001/11/13 14:23:56 mohor
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// Revision 1.4 2001/11/13 14:23:56 mohor
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// Generic memory model is used. Defines are changed for the same reason.
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// Generic memory model is used. Defines are changed for the same reason.
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//
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//
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Status signals changed, Adress decoding changed, interrupt controller
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// Status signals changed, Adress decoding changed, interrupt controller
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// added.
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// added.
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//
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//
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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// demands).
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//
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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// is done due to the ASIC tools.
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//
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//`define EXTERNAL_DMA // Using DMA
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//`define EXTERNAL_DMA // Using DMA
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// Selection of the used memory
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// Selection of the used memory
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//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
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//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
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// specific elements.
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// specific elements.
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//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
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//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_MODER_ADR 8'h0 // 0x0
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_INT_MASK_ADR 8'h2 // 0x8
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`define ETH_IPGT_ADR 8'h3 // 0xC
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`define ETH_IPGT_ADR 8'h3 // 0xC
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`define ETH_IPGR1_ADR 8'h4 // 0x10
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`define ETH_IPGR1_ADR 8'h4 // 0x10
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`define ETH_IPGR2_ADR 8'h5 // 0x14
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`define ETH_IPGR2_ADR 8'h5 // 0x14
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`define ETH_PACKETLEN_ADR 8'h6 // 0x18
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`define ETH_PACKETLEN_ADR 8'h6 // 0x18
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`define ETH_COLLCONF_ADR 8'h7 // 0x1C
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`define ETH_COLLCONF_ADR 8'h7 // 0x1C
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`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
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`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
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`define ETH_CTRLMODER_ADR 8'h9 // 0x24
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`define ETH_CTRLMODER_ADR 8'h9 // 0x24
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`define ETH_MIIMODER_ADR 8'hA // 0x28
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`define ETH_MIIMODER_ADR 8'hA // 0x28
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`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
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`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
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`define ETH_MIIADDRESS_ADR 8'hC // 0x30
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`define ETH_MIIADDRESS_ADR 8'hC // 0x30
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`define ETH_MIITX_DATA_ADR 8'hD // 0x34
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`define ETH_MIITX_DATA_ADR 8'hD // 0x34
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`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
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`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
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`define ETH_MIISTATUS_ADR 8'hF // 0x3C
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`define ETH_MIISTATUS_ADR 8'hF // 0x3C
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`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
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`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
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`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
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`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
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`define ETH_HASH0_ADR 8'h12 // 0x48
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`define ETH_HASH0_ADR 8'h12 // 0x48
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`define ETH_HASH1_ADR 8'h13 // 0x4C
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`define ETH_HASH1_ADR 8'h13 // 0x4C
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`define ETH_MODER_DEF 17'h0A800
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`define ETH_MODER_DEF 17'h0A800
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`define ETH_INT_SOURCE_DEF 32'h00000000
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`define ETH_INT_SOURCE_DEF 32'h00000000
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`define ETH_INT_MASK_DEF 7'h0
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`define ETH_INT_MASK_DEF 7'h0
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`define ETH_IPGT_DEF 7'h12
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`define ETH_IPGT_DEF 7'h12
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`define ETH_IPGR1_DEF 7'h0C
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`define ETH_IPGR1_DEF 7'h0C
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`define ETH_IPGR2_DEF 7'h12
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`define ETH_IPGR2_DEF 7'h12
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`define ETH_PACKETLEN_DEF 32'h003C0600
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`define ETH_PACKETLEN_DEF 32'h003C0600
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`define ETH_COLLCONF0_DEF 6'h3f
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`define ETH_COLLCONF0_DEF 6'h3f
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`define ETH_COLLCONF1_DEF 4'hF
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`define ETH_COLLCONF1_DEF 4'hF
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`define ETH_TX_BD_NUM_DEF 8'h80
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`define ETH_TX_BD_NUM_DEF 8'h80
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`define ETH_CTRLMODER_DEF 3'h0
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`define ETH_CTRLMODER_DEF 3'h0
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`define ETH_MIIMODER_DEF 11'h064
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`define ETH_MIIMODER_DEF 11'h064
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`define ETH_MIIADDRESS0_DEF 5'h00
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`define ETH_MIIADDRESS0_DEF 5'h00
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`define ETH_MIIADDRESS1_DEF 5'h00
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`define ETH_MIIADDRESS1_DEF 5'h00
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`define ETH_MIITX_DATA_DEF 16'h0000
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`define ETH_MIITX_DATA_DEF 16'h0000
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`define ETH_MIIRX_DATA_DEF 16'h0000
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`define ETH_MIIRX_DATA_DEF 16'h0000
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`define ETH_MIISTATUS_DEF 32'h00000000
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`define ETH_MIISTATUS_DEF 32'h00000000
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`define ETH_MAC_ADDR0_DEF 32'h00000000
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`define ETH_MAC_ADDR0_DEF 32'h00000000
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`define ETH_MAC_ADDR1_DEF 16'h0000
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`define ETH_MAC_ADDR1_DEF 16'h0000
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`define ETH_HASH0_DEF 32'h00000000
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`define ETH_HASH0_DEF 32'h00000000
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`define ETH_HASH1_DEF 32'h00000000
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`define ETH_HASH1_DEF 32'h00000000
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// Outputs are registered (uncomment when needed)
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// Outputs are registered (uncomment when needed)
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// `define ETH_REGISTERED_OUTPUTS
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// `define ETH_REGISTERED_OUTPUTS
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`define TX_FIFO_CNT_WIDTH 4
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`define TX_FIFO_CNT_WIDTH 4
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`define TX_FIFO_DEPTH 8
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`define TX_FIFO_DEPTH 8
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`define TX_FIFO_DATA_WIDTH 32
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`define TX_FIFO_DATA_WIDTH 32
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`define RX_FIFO_CNT_WIDTH 4
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`define RX_FIFO_CNT_WIDTH 4
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`define RX_FIFO_DEPTH 8
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`define RX_FIFO_DEPTH 8
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`define RX_FIFO_DATA_WIDTH 32
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`define RX_FIFO_DATA_WIDTH 32
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`define MULTICAST_XFR 0
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`define UNICAST_XFR 1
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`define BROADCAST_XFR 2
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