//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth_top.v ////
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//// eth_top.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/cores/ethmac/ ////
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//// http://www.opencores.org/cores/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2001/10/19 11:24:29 mohor
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// Number of addresses (wb_adr_i) minimized.
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//
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// Revision 1.5 2001/10/19 08:43:51 mohor
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// Revision 1.5 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.4 2001/10/18 12:07:11 mohor
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// Revision 1.4 2001/10/18 12:07:11 mohor
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// Status signals changed, Adress decoding changed, interrupt controller
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// Status signals changed, Adress decoding changed, interrupt controller
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// added.
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// added.
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//
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//
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// Revision 1.3 2001/09/24 15:02:56 mohor
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// Revision 1.3 2001/09/24 15:02:56 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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// demands).
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//
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//
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// Revision 1.2 2001/08/15 14:03:59 mohor
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// Revision 1.2 2001/08/15 14:03:59 mohor
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// Signal names changed on the top level for easier pad insertion (ASIC).
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// Signal names changed on the top level for easier pad insertion (ASIC).
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//
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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// is done due to the ASIC tools.
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//
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//
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Unconnected signals are now connected.
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// Unconnected signals are now connected.
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//
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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//
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//
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//
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//
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//
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//
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//
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//
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`include "eth_defines.v"
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module eth_top
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module eth_top
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(
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(
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// WISHBONE common
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// WISHBONE common
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
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// WISHBONE slave
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// WISHBONE slave
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
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wb_req_o, wb_ack_i, wb_nd_o, wb_rd_o,
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wb_req_o, wb_ack_i, wb_nd_o, wb_rd_o,
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//TX
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//TX
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mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
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//RX
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//RX
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
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// MIIM
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// MIIM
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mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o,
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mdc_pad_o, md_pad_i, md_pad_o, md_padoen_o,
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int_o
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int_o
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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// WISHBONE common
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// WISHBONE common
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input wb_clk_i; // WISHBONE clock
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input wb_clk_i; // WISHBONE clock
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input wb_rst_i; // WISHBONE reset
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input wb_rst_i; // WISHBONE reset
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input [31:0] wb_dat_i; // WISHBONE data input
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input [31:0] wb_dat_i; // WISHBONE data input
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output [31:0] wb_dat_o; // WISHBONE data output
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output [31:0] wb_dat_o; // WISHBONE data output
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output wb_err_o; // WISHBONE error output
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output wb_err_o; // WISHBONE error output
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// WISHBONE slave
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// WISHBONE slave
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input [11:2] wb_adr_i; // WISHBONE address input
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input [11:2] wb_adr_i; // WISHBONE address input
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input [3:0] wb_sel_i; // WISHBONE byte select input
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input [3:0] wb_sel_i; // WISHBONE byte select input
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input wb_we_i; // WISHBONE write enable input
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input wb_we_i; // WISHBONE write enable input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_cyc_i; // WISHBONE cycle input
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input wb_stb_i; // WISHBONE strobe input
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input wb_stb_i; // WISHBONE strobe input
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output wb_ack_o; // WISHBONE acknowledge output
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output wb_ack_o; // WISHBONE acknowledge output
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// DMA
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// DMA
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input [1:0] wb_ack_i; // DMA acknowledge input
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input [1:0] wb_ack_i; // DMA acknowledge input
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_req_o; // DMA request output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output [1:0] wb_nd_o; // DMA force new descriptor output
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output wb_rd_o; // DMA restart descriptor output
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output wb_rd_o; // DMA restart descriptor output
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// Tx
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// Tx
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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input mtx_clk_pad_i; // Transmit clock (from PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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output mtxen_pad_o; // Transmit enable (to PHY)
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output mtxerr_pad_o; // Transmit error (to PHY)
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output mtxerr_pad_o; // Transmit error (to PHY)
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// Rx
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// Rx
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input mrx_clk_pad_i; // Receive clock (from PHY)
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input mrx_clk_pad_i; // Receive clock (from PHY)
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input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
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input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
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input mrxdv_pad_i; // Receive data valid (from PHY)
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input mrxdv_pad_i; // Receive data valid (from PHY)
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input mrxerr_pad_i; // Receive data error (from PHY)
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input mrxerr_pad_i; // Receive data error (from PHY)
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// Common Tx and Rx
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// Common Tx and Rx
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input mcoll_pad_i; // Collision (from PHY)
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input mcoll_pad_i; // Collision (from PHY)
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input mcrs_pad_i; // Carrier sense (from PHY)
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input mcrs_pad_i; // Carrier sense (from PHY)
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// MII Management interface
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// MII Management interface
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input md_pad_i; // MII data input (from I/O cell)
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input md_pad_i; // MII data input (from I/O cell)
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output mdc_pad_o; // MII Management data clock (to PHY)
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output mdc_pad_o; // MII Management data clock (to PHY)
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output md_pad_o; // MII data output (to I/O cell)
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output md_pad_o; // MII data output (to I/O cell)
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output md_padoen_o; // MII data output enable (to I/O cell)
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output md_padoen_o; // MII data output enable (to I/O cell)
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output int_o; // Interrupt output
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output int_o; // Interrupt output
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wire [7:0] r_ClkDiv;
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wire [7:0] r_ClkDiv;
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wire r_MiiNoPre;
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wire r_MiiNoPre;
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wire [15:0] r_CtrlData;
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wire [15:0] r_CtrlData;
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wire [4:0] r_FIAD;
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wire [4:0] r_FIAD;
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wire [4:0] r_RGAD;
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wire [4:0] r_RGAD;
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wire r_WCtrlData;
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wire r_WCtrlData;
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wire r_RStat;
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wire r_RStat;
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wire r_ScanStat;
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wire r_ScanStat;
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wire NValid_stat;
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wire NValid_stat;
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wire Busy_stat;
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wire Busy_stat;
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wire LinkFail;
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wire LinkFail;
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wire r_MiiMRst;
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wire r_MiiMRst;
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wire [15:0] Prsd; // Read Status Data (data read from the PHY)
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wire [15:0] Prsd; // Read Status Data (data read from the PHY)
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wire WCtrlDataStart;
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wire WCtrlDataStart;
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wire RStatStart;
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wire RStatStart;
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wire UpdateMIIRX_DATAReg;
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wire UpdateMIIRX_DATAReg;
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wire TxStartFrm;
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wire TxStartFrm;
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wire TxEndFrm;
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wire TxEndFrm;
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wire TxUsedData;
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wire TxUsedData;
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wire [7:0] TxData;
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wire [7:0] TxData;
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wire TxRetry;
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wire TxRetry;
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wire TxAbort;
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wire TxAbort;
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wire TxUnderRun;
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wire TxUnderRun;
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wire TxDone;
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wire TxDone;
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// Connecting Miim module
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// Connecting Miim module
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eth_miim miim1
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eth_miim miim1
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(
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(
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.Clk(wb_clk_i), .Reset(r_MiiMRst), .Divider(r_ClkDiv),
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.Clk(wb_clk_i), .Reset(r_MiiMRst), .Divider(r_ClkDiv),
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.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
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.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
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.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
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.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
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.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
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.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
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.MdoEn(md_padoen_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
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.MdoEn(md_padoen_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
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.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
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.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
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.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
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.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
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);
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);
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wire RegCs; // Connected to registers
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wire RegCs; // Connected to registers
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wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
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wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
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wire r_DmaEn; // DMA enable
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wire r_DmaEn; // DMA enable
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wire r_Rst; // Reset
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wire r_Rst; // Reset
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wire r_LoopBck; // Loopback
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wire r_LoopBck; // Loopback
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wire r_TxEn; // Tx Enable
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wire r_TxEn; // Tx Enable
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wire r_RxEn; // Rx Enable
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wire r_RxEn; // Rx Enable
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|
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wire MRxDV_Lb; // Muxed MII receive data valid
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wire MRxDV_Lb; // Muxed MII receive data valid
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wire MRxErr_Lb; // Muxed MII Receive Error
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wire MRxErr_Lb; // Muxed MII Receive Error
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wire [3:0] MRxD_Lb; // Muxed MII Receive Data
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wire [3:0] MRxD_Lb; // Muxed MII Receive Data
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wire Transmitting; // Indication that TxEthMAC is transmitting
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wire Transmitting; // Indication that TxEthMAC is transmitting
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wire r_HugEn; // Huge packet enable
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wire r_HugEn; // Huge packet enable
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wire r_DlyCrcEn; // Delayed CRC enabled
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wire r_DlyCrcEn; // Delayed CRC enabled
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wire [15:0] r_MaxFL; // Maximum frame length
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wire [15:0] r_MaxFL; // Maximum frame length
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|
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wire [15:0] r_MinFL; // Minimum frame length
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wire [15:0] r_MinFL; // Minimum frame length
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wire [47:0] r_MAC; // MAC address
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wire [47:0] r_MAC; // MAC address
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|
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wire [7:0] r_RxBDAddress; // Receive buffer descriptor base address
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wire [7:0] r_RxBDNum; // Receive buffer descriptor number
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wire [6:0] r_IPGT; //
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wire [6:0] r_IPGT; //
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wire [6:0] r_IPGR1; //
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wire [6:0] r_IPGR1; //
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wire [6:0] r_IPGR2; //
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wire [6:0] r_IPGR2; //
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wire [5:0] r_CollValid; //
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wire [5:0] r_CollValid; //
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wire r_TPauseRq; // Transmit PAUSE request pulse
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wire r_TPauseRq; // Transmit PAUSE request pulse
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|
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wire [3:0] r_MaxRet; //
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wire [3:0] r_MaxRet; //
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wire r_NoBckof; //
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wire r_NoBckof; //
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wire r_ExDfrEn; //
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wire r_ExDfrEn; //
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wire RX_BD_ADR_Wr; // Write enable that writes RX_BD_ADR to the registers.
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wire RX_BD_NUM_Wr; // Write enable that writes RX_BD_NUM to the registers.
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wire TPauseRq; // Sinhronized Tx PAUSE request
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wire TPauseRq; // Sinhronized Tx PAUSE request
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wire [15:0] TxPauseTV; // Tx PAUSE timer value
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wire [15:0] TxPauseTV; // Tx PAUSE timer value
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wire r_TxFlow; // Tx flow control enable
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wire r_TxFlow; // Tx flow control enable
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wire r_IFG; // Minimum interframe gap for incoming packets
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wire r_IFG; // Minimum interframe gap for incoming packets
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|
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wire TxB_IRQ; // Interrupt Tx Buffer
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wire TxB_IRQ; // Interrupt Tx Buffer
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wire TxE_IRQ; // Interrupt Tx Error
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wire TxE_IRQ; // Interrupt Tx Error
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wire RxB_IRQ; // Interrupt Rx Buffer
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wire RxB_IRQ; // Interrupt Rx Buffer
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wire RxF_IRQ; // Interrupt Rx Frame
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wire RxF_IRQ; // Interrupt Rx Frame
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wire Busy_IRQ; // Interrupt Busy (lack of buffers)
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wire Busy_IRQ; // Interrupt Busy (lack of buffers)
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|
|
wire DWord;
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wire DWord;
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wire BDAck;
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wire BDAck;
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wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
|
wire [31:0] DMA_WB_DAT_O; // wb_dat_o that comes from the WishboneDMA module
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wire BDCs; // Buffer descriptor CS
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wire BDCs; // Buffer descriptor CS
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|
|
|
|
assign DWord = &wb_sel_i;
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assign DWord = &wb_sel_i;
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];
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assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10];
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assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10];
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assign wb_ack_o = RegCs | BDAck;
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assign wb_ack_o = RegCs | BDAck;
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assign wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
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assign wb_err_o = wb_stb_i & wb_cyc_i & ~DWord;
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|
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// Selecting the WISHBONE output data
|
// Selecting the WISHBONE output data
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assign wb_dat_o[31:0] = (RegCs & ~wb_we_i)? RegDataOut : DMA_WB_DAT_O;
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assign wb_dat_o[31:0] = (RegCs & ~wb_we_i)? RegDataOut : DMA_WB_DAT_O;
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|
|
|
|
// Connecting Ethernet registers
|
// Connecting Ethernet registers
|
eth_registers ethreg1
|
eth_registers ethreg1
|
(
|
(
|
.DataIn(wb_dat_i), .Address(wb_adr_i[7:2]), .Rw(wb_we_i),
|
.DataIn(wb_dat_i), .Address(wb_adr_i[7:2]), .Rw(wb_we_i),
|
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
|
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
|
.DataOut(RegDataOut), .r_DmaEn(r_DmaEn), .r_RecSmall(),
|
.DataOut(RegDataOut), .r_DmaEn(r_DmaEn), .r_RecSmall(),
|
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
|
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
|
.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD),
|
.r_DlyCrcEn(r_DlyCrcEn), .r_Rst(r_Rst), .r_FullD(r_FullD),
|
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
|
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
|
.r_IFG(r_IFG), .r_Pro(), .r_Iam(),
|
.r_IFG(r_IFG), .r_Pro(), .r_Iam(),
|
.r_Bro(), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
|
.r_Bro(), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
|
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ),
|
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ),
|
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
|
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
|
.r_IPGT(r_IPGT),
|
.r_IPGT(r_IPGT),
|
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
|
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
|
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
|
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
|
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
|
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
|
.r_MiiMRst(r_MiiMRst), .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
|
.r_MiiMRst(r_MiiMRst), .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
|
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
|
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
|
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
|
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
|
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
|
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
|
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
|
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
|
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
|
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
|
.r_RxBDAddress(r_RxBDAddress), .RX_BD_ADR_Wr(RX_BD_ADR_Wr), .int_o(int_o)
|
.r_RxBDNum(r_RxBDNum), .RX_BD_NUM_Wr(RX_BD_NUM_Wr), .int_o(int_o)
|
);
|
);
|
|
|
|
|
|
|
wire [7:0] RxData;
|
wire [7:0] RxData;
|
wire RxValid;
|
wire RxValid;
|
wire RxStartFrm;
|
wire RxStartFrm;
|
wire RxEndFrm;
|
wire RxEndFrm;
|
|
|
wire WillTransmit; // Will transmit (to RxEthMAC)
|
wire WillTransmit; // Will transmit (to RxEthMAC)
|
wire ResetCollision; // Reset Collision (for synchronizing collision)
|
wire ResetCollision; // Reset Collision (for synchronizing collision)
|
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
|
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
|
wire WillSendControlFrame;
|
wire WillSendControlFrame;
|
wire TxCtrlEndFrm;
|
wire TxCtrlEndFrm;
|
wire ReceivedPauseFrm;
|
wire ReceivedPauseFrm;
|
wire ReceiveEnd;
|
wire ReceiveEnd;
|
wire ReceivedPacketGood;
|
wire ReceivedPacketGood;
|
wire ReceivedLengthOK;
|
wire ReceivedLengthOK;
|
|
|
// Connecting MACControl
|
// Connecting MACControl
|
eth_maccontrol maccontrol1
|
eth_maccontrol maccontrol1
|
(
|
(
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
|
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
|
.TxPauseTV(TxPauseTV), .TxDataIn(TxData),
|
.TxPauseTV(TxPauseTV), .TxDataIn(TxData),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
|
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
|
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
|
.RxData(RxData), .RxValid(RxValid),
|
.RxData(RxData), .RxValid(RxValid),
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
|
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
|
.PassAll(r_PassAll), .TxFlow(r_TxFlow),
|
.PassAll(r_PassAll), .TxFlow(r_TxFlow),
|
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
|
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
|
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
|
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
|
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
|
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
|
.CrcEnOut(CrcEnOut), .TxReset(r_Rst),
|
.CrcEnOut(CrcEnOut), .TxReset(r_Rst),
|
.RxReset(r_Rst), .ReceivedLengthOK(ReceivedLengthOK),
|
.RxReset(r_Rst), .ReceivedLengthOK(ReceivedLengthOK),
|
.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
|
.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
|
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
|
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
|
.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
|
.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
|
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
|
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
|
.ReceivedPauseFrm(ReceivedPauseFrm)
|
.ReceivedPauseFrm(ReceivedPauseFrm)
|
);
|
);
|
|
|
|
|
|
|
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
|
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
|
wire Collision; // Synchronized Collision
|
wire Collision; // Synchronized Collision
|
|
|
reg CarrierSense_Tx1;
|
reg CarrierSense_Tx1;
|
reg CarrierSense_Tx2;
|
reg CarrierSense_Tx2;
|
reg Collision_Tx1;
|
reg Collision_Tx1;
|
reg Collision_Tx2;
|
reg Collision_Tx2;
|
|
|
reg RxEnSync; // Synchronized Receive Enable
|
reg RxEnSync; // Synchronized Receive Enable
|
reg CarrierSense_Rx1;
|
reg CarrierSense_Rx1;
|
reg RxCarrierSense; // Synchronized CarrierSense (to Rx clock)
|
reg RxCarrierSense; // Synchronized CarrierSense (to Rx clock)
|
reg WillTransmit_q;
|
reg WillTransmit_q;
|
reg WillTransmit_q2;
|
reg WillTransmit_q2;
|
|
|
|
|
|
|
// Muxed MII receive data valid
|
// Muxed MII receive data valid
|
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
|
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
|
|
|
// Muxed MII Receive Error
|
// Muxed MII Receive Error
|
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
|
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
|
|
|
// Muxed MII Receive Data
|
// Muxed MII Receive Data
|
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
|
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
|
|
|
|
|
|
|
// Connecting TxEthMAC
|
// Connecting TxEthMAC
|
eth_txethmac txethmac1
|
eth_txethmac txethmac1
|
(
|
(
|
.MTxClk(mtx_clk_pad_i), .Reset(r_Rst), .CarrierSense(TxCarrierSense),
|
.MTxClk(mtx_clk_pad_i), .Reset(r_Rst), .CarrierSense(TxCarrierSense),
|
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
|
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
|
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
|
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
|
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
|
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
|
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
|
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
|
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
|
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
|
.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
|
.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
|
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
|
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
|
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
|
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
|
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
|
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
|
.ResetCollision(ResetCollision)
|
.ResetCollision(ResetCollision)
|
);
|
);
|
|
|
|
|
|
|
|
|
wire [15:0] RxByteCnt;
|
wire [15:0] RxByteCnt;
|
wire RxByteCntEq0;
|
wire RxByteCntEq0;
|
wire RxByteCntGreat2;
|
wire RxByteCntGreat2;
|
wire RxByteCntMaxFrame;
|
wire RxByteCntMaxFrame;
|
wire RxCrcError;
|
wire RxCrcError;
|
wire RxStateIdle;
|
wire RxStateIdle;
|
wire RxStatePreamble;
|
wire RxStatePreamble;
|
wire RxStateSFD;
|
wire RxStateSFD;
|
wire [1:0] RxStateData;
|
wire [1:0] RxStateData;
|
|
|
|
|
|
|
|
|
// Connecting RxEthMAC
|
// Connecting RxEthMAC
|
eth_rxethmac rxethmac1
|
eth_rxethmac rxethmac1
|
(
|
(
|
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
|
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
|
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
|
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
|
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(r_Rst),
|
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(r_Rst),
|
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
|
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
|
.RxEndFrm(RxEndFrm), .CrcHash(), .CrcHashGood(),
|
.RxEndFrm(RxEndFrm), .CrcHash(), .CrcHashGood(),
|
.Broadcast(), .Multicast(), .ByteCnt(RxByteCnt),
|
.Broadcast(), .Multicast(), .ByteCnt(RxByteCnt),
|
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
|
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
|
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
|
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
|
.StateSFD(RxStateSFD), .StateData(RxStateData)
|
.StateSFD(RxStateSFD), .StateData(RxStateData)
|
);
|
);
|
|
|
|
|
// MII Carrier Sense Synchronization
|
// MII Carrier Sense Synchronization
|
always @ (posedge mtx_clk_pad_i or posedge r_Rst)
|
always @ (posedge mtx_clk_pad_i or posedge r_Rst)
|
begin
|
begin
|
if(r_Rst)
|
if(r_Rst)
|
begin
|
begin
|
CarrierSense_Tx1 <= #Tp 1'b0;
|
CarrierSense_Tx1 <= #Tp 1'b0;
|
CarrierSense_Tx2 <= #Tp 1'b0;
|
CarrierSense_Tx2 <= #Tp 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
CarrierSense_Tx1 <= #Tp mcrs_pad_i;
|
CarrierSense_Tx1 <= #Tp mcrs_pad_i;
|
CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
|
CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
|
end
|
end
|
end
|
end
|
|
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
|
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
|
|
|
|
|
// MII Collision Synchronization
|
// MII Collision Synchronization
|
always @ (posedge mtx_clk_pad_i or posedge r_Rst)
|
always @ (posedge mtx_clk_pad_i or posedge r_Rst)
|
begin
|
begin
|
if(r_Rst)
|
if(r_Rst)
|
begin
|
begin
|
Collision_Tx1 <= #Tp 1'b0;
|
Collision_Tx1 <= #Tp 1'b0;
|
Collision_Tx2 <= #Tp 1'b0;
|
Collision_Tx2 <= #Tp 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Collision_Tx1 <= #Tp mcoll_pad_i;
|
Collision_Tx1 <= #Tp mcoll_pad_i;
|
if(ResetCollision)
|
if(ResetCollision)
|
Collision_Tx2 <= #Tp 1'b0;
|
Collision_Tx2 <= #Tp 1'b0;
|
else
|
else
|
if(Collision_Tx1)
|
if(Collision_Tx1)
|
Collision_Tx2 <= #Tp 1'b1;
|
Collision_Tx2 <= #Tp 1'b1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Synchronized Collision
|
// Synchronized Collision
|
assign Collision = ~r_FullD & Collision_Tx2;
|
assign Collision = ~r_FullD & Collision_Tx2;
|
|
|
|
|
|
|
// Carrier sense is synchronized to receive clock.
|
// Carrier sense is synchronized to receive clock.
|
always @ (posedge mrx_clk_pad_i or posedge r_Rst)
|
always @ (posedge mrx_clk_pad_i or posedge r_Rst)
|
begin
|
begin
|
if(r_Rst)
|
if(r_Rst)
|
begin
|
begin
|
CarrierSense_Rx1 <= #Tp 1'h0;
|
CarrierSense_Rx1 <= #Tp 1'h0;
|
RxCarrierSense <= #Tp 1'h0;
|
RxCarrierSense <= #Tp 1'h0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
CarrierSense_Rx1 <= #Tp mcrs_pad_i;
|
CarrierSense_Rx1 <= #Tp mcrs_pad_i;
|
RxCarrierSense <= #Tp CarrierSense_Rx1;
|
RxCarrierSense <= #Tp CarrierSense_Rx1;
|
end
|
end
|
end
|
end
|
|
|
|
|
// Delayed WillTransmit
|
// Delayed WillTransmit
|
always @ (posedge mrx_clk_pad_i)
|
always @ (posedge mrx_clk_pad_i)
|
begin
|
begin
|
WillTransmit_q <= #Tp WillTransmit;
|
WillTransmit_q <= #Tp WillTransmit;
|
WillTransmit_q2 <= #Tp WillTransmit_q;
|
WillTransmit_q2 <= #Tp WillTransmit_q;
|
end
|
end
|
|
|
|
|
assign Transmitting = ~r_FullD & WillTransmit_q2;
|
assign Transmitting = ~r_FullD & WillTransmit_q2;
|
|
|
|
|
|
|
// Synchronized Receive Enable
|
// Synchronized Receive Enable
|
always @ (posedge mrx_clk_pad_i or posedge r_Rst)
|
always @ (posedge mrx_clk_pad_i or posedge r_Rst)
|
begin
|
begin
|
if(r_Rst)
|
if(r_Rst)
|
RxEnSync <= #Tp 1'b0;
|
RxEnSync <= #Tp 1'b0;
|
else
|
else
|
if(~RxCarrierSense | RxCarrierSense & Transmitting)
|
if(~RxCarrierSense | RxCarrierSense & Transmitting)
|
RxEnSync <= #Tp r_RxEn;
|
RxEnSync <= #Tp r_RxEn;
|
end
|
end
|
|
|
|
|
|
|
|
|
// Connecting WishboneDMA module
|
// Connecting WishboneDMA module
|
eth_wishbonedma wbdma
|
eth_wishbonedma wbdma
|
(
|
(
|
.WB_CLK_I(wb_clk_i), .WB_RST_I(wb_rst_i), .WB_DAT_I(wb_dat_i),
|
.WB_CLK_I(wb_clk_i), .WB_RST_I(wb_rst_i), .WB_DAT_I(wb_dat_i),
|
.WB_DAT_O(DMA_WB_DAT_O),
|
.WB_DAT_O(DMA_WB_DAT_O),
|
|
|
// WISHBONE slave
|
// WISHBONE slave
|
.WB_ADR_I(wb_adr_i[9:2]), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
|
.WB_ADR_I(wb_adr_i[9:2]), .WB_SEL_I(wb_sel_i), .WB_WE_I(wb_we_i),
|
.BDCs(BDCs), .WB_ACK_O(BDAck),
|
.BDCs(BDCs), .WB_ACK_O(BDAck),
|
.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
|
.WB_REQ_O(wb_req_o), .WB_ACK_I(wb_ack_i), .WB_ND_O(wb_nd_o),
|
.WB_RD_O(wb_rd_o),
|
.WB_RD_O(wb_rd_o),
|
|
|
//TX
|
//TX
|
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
|
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
|
.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0),
|
.TxUsedData(TxUsedData), .TxData(TxData), .StatusIzTxEthMACModula(16'h0),
|
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
|
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
|
.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV),
|
.TxDone(TxDone), .TPauseRq(TPauseRq), .TxPauseTV(TxPauseTV),
|
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), .WillSendControlFrame(WillSendControlFrame),
|
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad), .WillSendControlFrame(WillSendControlFrame),
|
.TxCtrlEndFrm(TxCtrlEndFrm),
|
.TxCtrlEndFrm(TxCtrlEndFrm),
|
|
|
// Register
|
// Register
|
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDAddress(r_RxBDAddress),
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.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_RxBDNum(r_RxBDNum),
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.r_DmaEn(r_DmaEn), .RX_BD_ADR_Wr(RX_BD_ADR_Wr),
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.r_DmaEn(r_DmaEn), .RX_BD_NUM_Wr(RX_BD_NUM_Wr),
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|
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//RX
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//RX
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
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.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
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.Busy_IRQ(Busy_IRQ), .RxF_IRQ(RxF_IRQ), .RxB_IRQ(RxB_IRQ),
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.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ)
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.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ)
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|
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);
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);
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// Connecting MacStatus module
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// Connecting MacStatus module
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eth_macstatus macstatus1
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eth_macstatus macstatus1
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(
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(
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.MRxClk(mrx_clk_pad_i), .Reset(r_Rst), .TransmitEnd(),
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.MRxClk(mrx_clk_pad_i), .Reset(r_Rst), .TransmitEnd(),
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.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
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.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
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.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
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.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
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.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
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.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
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.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
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.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
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.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
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.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
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.ReceivedPauseFrm(ReceivedPauseFrm)
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.ReceivedPauseFrm(ReceivedPauseFrm)
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);
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);
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|
|
|
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endmodule
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endmodule
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