//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth_cop.v ////
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//// eth_cop.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/10/10 16:43:59 mohor
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// Minor $display change.
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//
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// Revision 1.2 2002/09/09 12:54:13 mohor
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// Revision 1.2 2002/09/09 12:54:13 mohor
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// error acknowledge cycle termination added to display.
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// error acknowledge cycle termination added to display.
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//
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//
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// Revision 1.1 2002/08/14 17:16:07 mohor
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// Revision 1.1 2002/08/14 17:16:07 mohor
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// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
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// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
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// interfaces:
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// interfaces:
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// - Host connects to the master interface
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// - Host connects to the master interface
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// - Ethernet master (DMA) connects to the second master interface
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// - Ethernet master (DMA) connects to the second master interface
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// - Memory interface connects to the slave interface
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// - Memory interface connects to the slave interface
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// - Ethernet slave interface (access to registers and BDs) connects to second
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// - Ethernet slave interface (access to registers and BDs) connects to second
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// slave interface
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// slave interface
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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`include "tb_eth_defines.v"
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module eth_cop
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module eth_cop
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(
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(
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// WISHBONE common
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// WISHBONE common
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wb_clk_i, wb_rst_i,
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wb_clk_i, wb_rst_i,
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// WISHBONE MASTER 1
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// WISHBONE MASTER 1
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m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,
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m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,
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m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
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m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
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m1_wb_err_o,
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m1_wb_err_o,
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|
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// WISHBONE MASTER 2
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// WISHBONE MASTER 2
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m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,
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m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,
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m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
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m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
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m2_wb_err_o,
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m2_wb_err_o,
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|
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// WISHBONE slave 1
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// WISHBONE slave 1
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s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,
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s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,
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s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
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s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
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s1_wb_dat_o,
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s1_wb_dat_o,
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|
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// WISHBONE slave 2
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// WISHBONE slave 2
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s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,
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s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,
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s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
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s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
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s2_wb_dat_o
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s2_wb_dat_o
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);
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);
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parameter Tp=1;
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parameter Tp=1;
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// WISHBONE common
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// WISHBONE common
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input wb_clk_i, wb_rst_i;
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input wb_clk_i, wb_rst_i;
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|
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// WISHBONE MASTER 1
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// WISHBONE MASTER 1
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input [31:0] m1_wb_adr_i, m1_wb_dat_i;
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input [31:0] m1_wb_adr_i, m1_wb_dat_i;
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input [3:0] m1_wb_sel_i;
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input [3:0] m1_wb_sel_i;
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input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
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input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
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output [31:0] m1_wb_dat_o;
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output [31:0] m1_wb_dat_o;
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output m1_wb_ack_o, m1_wb_err_o;
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output m1_wb_ack_o, m1_wb_err_o;
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|
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// WISHBONE MASTER 2
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// WISHBONE MASTER 2
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input [31:0] m2_wb_adr_i, m2_wb_dat_i;
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input [31:0] m2_wb_adr_i, m2_wb_dat_i;
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input [3:0] m2_wb_sel_i;
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input [3:0] m2_wb_sel_i;
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input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
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input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
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output [31:0] m2_wb_dat_o;
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output [31:0] m2_wb_dat_o;
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output m2_wb_ack_o, m2_wb_err_o;
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output m2_wb_ack_o, m2_wb_err_o;
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// WISHBONE slave 1
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// WISHBONE slave 1
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input [31:0] s1_wb_dat_i;
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input [31:0] s1_wb_dat_i;
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input s1_wb_ack_i, s1_wb_err_i;
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input s1_wb_ack_i, s1_wb_err_i;
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output [31:0] s1_wb_adr_o, s1_wb_dat_o;
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output [31:0] s1_wb_adr_o, s1_wb_dat_o;
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output [3:0] s1_wb_sel_o;
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output [3:0] s1_wb_sel_o;
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output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;
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output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;
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|
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// WISHBONE slave 2
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// WISHBONE slave 2
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input [31:0] s2_wb_dat_i;
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input [31:0] s2_wb_dat_i;
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input s2_wb_ack_i, s2_wb_err_i;
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input s2_wb_ack_i, s2_wb_err_i;
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output [31:0] s2_wb_adr_o, s2_wb_dat_o;
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output [31:0] s2_wb_adr_o, s2_wb_dat_o;
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output [3:0] s2_wb_sel_o;
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output [3:0] s2_wb_sel_o;
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output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;
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output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;
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|
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reg m1_in_progress;
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reg m1_in_progress;
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reg m2_in_progress;
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reg m2_in_progress;
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reg [31:0] s1_wb_adr_o;
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reg [31:0] s1_wb_adr_o;
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reg [3:0] s1_wb_sel_o;
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reg [3:0] s1_wb_sel_o;
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reg s1_wb_we_o;
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reg s1_wb_we_o;
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reg [31:0] s1_wb_dat_o;
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reg [31:0] s1_wb_dat_o;
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reg s1_wb_cyc_o;
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reg s1_wb_cyc_o;
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reg s1_wb_stb_o;
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reg s1_wb_stb_o;
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reg [31:0] s2_wb_adr_o;
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reg [31:0] s2_wb_adr_o;
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reg [3:0] s2_wb_sel_o;
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reg [3:0] s2_wb_sel_o;
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reg s2_wb_we_o;
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reg s2_wb_we_o;
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reg [31:0] s2_wb_dat_o;
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reg [31:0] s2_wb_dat_o;
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reg s2_wb_cyc_o;
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reg s2_wb_cyc_o;
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reg s2_wb_stb_o;
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reg s2_wb_stb_o;
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|
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reg m1_wb_ack_o;
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reg m1_wb_ack_o;
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reg [31:0] m1_wb_dat_o;
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reg [31:0] m1_wb_dat_o;
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reg m2_wb_ack_o;
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reg m2_wb_ack_o;
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reg [31:0] m2_wb_dat_o;
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reg [31:0] m2_wb_dat_o;
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|
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reg m1_wb_err_o;
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reg m1_wb_err_o;
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reg m2_wb_err_o;
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reg m2_wb_err_o;
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|
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wire m_wb_access_finished;
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wire m_wb_access_finished;
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wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
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wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
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wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
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wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
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|
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if(wb_rst_i)
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if(wb_rst_i)
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begin
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begin
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m1_in_progress <=#Tp 0;
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m1_in_progress <=#Tp 0;
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m2_in_progress <=#Tp 0;
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m2_in_progress <=#Tp 0;
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s1_wb_adr_o <=#Tp 0;
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s1_wb_adr_o <=#Tp 0;
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s1_wb_sel_o <=#Tp 0;
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s1_wb_sel_o <=#Tp 0;
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s1_wb_we_o <=#Tp 0;
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s1_wb_we_o <=#Tp 0;
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s1_wb_dat_o <=#Tp 0;
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s1_wb_dat_o <=#Tp 0;
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s1_wb_cyc_o <=#Tp 0;
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s1_wb_cyc_o <=#Tp 0;
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s1_wb_stb_o <=#Tp 0;
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s1_wb_stb_o <=#Tp 0;
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s2_wb_adr_o <=#Tp 0;
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s2_wb_adr_o <=#Tp 0;
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s2_wb_sel_o <=#Tp 0;
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s2_wb_sel_o <=#Tp 0;
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s2_wb_we_o <=#Tp 0;
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s2_wb_we_o <=#Tp 0;
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s2_wb_dat_o <=#Tp 0;
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s2_wb_dat_o <=#Tp 0;
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s2_wb_cyc_o <=#Tp 0;
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s2_wb_cyc_o <=#Tp 0;
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s2_wb_stb_o <=#Tp 0;
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s2_wb_stb_o <=#Tp 0;
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end
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end
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else
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else
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begin
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begin
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case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
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case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
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5'b00_10_0, 5'b00_11_0 :
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5'b00_10_0, 5'b00_11_0 :
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begin
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begin
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m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
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m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
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if(`M1_ADDRESSED_S1)
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if(`M1_ADDRESSED_S1)
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begin
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begin
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s1_wb_adr_o <=#Tp m1_wb_adr_i;
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s1_wb_adr_o <=#Tp m1_wb_adr_i;
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s1_wb_sel_o <=#Tp m1_wb_sel_i;
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s1_wb_sel_o <=#Tp m1_wb_sel_i;
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s1_wb_we_o <=#Tp m1_wb_we_i;
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s1_wb_we_o <=#Tp m1_wb_we_i;
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s1_wb_dat_o <=#Tp m1_wb_dat_i;
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s1_wb_dat_o <=#Tp m1_wb_dat_i;
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s1_wb_cyc_o <=#Tp 1'b1;
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s1_wb_cyc_o <=#Tp 1'b1;
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s1_wb_stb_o <=#Tp 1'b1;
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s1_wb_stb_o <=#Tp 1'b1;
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end
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end
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else if(`M1_ADDRESSED_S2)
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else if(`M1_ADDRESSED_S2)
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begin
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begin
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s2_wb_adr_o <=#Tp m1_wb_adr_i;
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s2_wb_adr_o <=#Tp m1_wb_adr_i;
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s2_wb_sel_o <=#Tp m1_wb_sel_i;
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s2_wb_sel_o <=#Tp m1_wb_sel_i;
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s2_wb_we_o <=#Tp m1_wb_we_i;
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s2_wb_we_o <=#Tp m1_wb_we_i;
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s2_wb_dat_o <=#Tp m1_wb_dat_i;
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s2_wb_dat_o <=#Tp m1_wb_dat_i;
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s2_wb_cyc_o <=#Tp 1'b1;
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s2_wb_cyc_o <=#Tp 1'b1;
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s2_wb_stb_o <=#Tp 1'b1;
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s2_wb_stb_o <=#Tp 1'b1;
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end
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end
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else
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else
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$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
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end
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end
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5'b00_01_0 :
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5'b00_01_0 :
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begin
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begin
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m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m
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m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m
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if(`M2_ADDRESSED_S1)
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if(`M2_ADDRESSED_S1)
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begin
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begin
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s1_wb_adr_o <=#Tp m2_wb_adr_i;
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s1_wb_adr_o <=#Tp m2_wb_adr_i;
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s1_wb_sel_o <=#Tp m2_wb_sel_i;
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s1_wb_sel_o <=#Tp m2_wb_sel_i;
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s1_wb_we_o <=#Tp m2_wb_we_i;
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s1_wb_we_o <=#Tp m2_wb_we_i;
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s1_wb_dat_o <=#Tp m2_wb_dat_i;
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s1_wb_dat_o <=#Tp m2_wb_dat_i;
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s1_wb_cyc_o <=#Tp 1'b1;
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s1_wb_cyc_o <=#Tp 1'b1;
|
s1_wb_stb_o <=#Tp 1'b1;
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s1_wb_stb_o <=#Tp 1'b1;
|
end
|
end
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else if(`M2_ADDRESSED_S2)
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else if(`M2_ADDRESSED_S2)
|
begin
|
begin
|
s2_wb_adr_o <=#Tp m2_wb_adr_i;
|
s2_wb_adr_o <=#Tp m2_wb_adr_i;
|
s2_wb_sel_o <=#Tp m2_wb_sel_i;
|
s2_wb_sel_o <=#Tp m2_wb_sel_i;
|
s2_wb_we_o <=#Tp m2_wb_we_i;
|
s2_wb_we_o <=#Tp m2_wb_we_i;
|
s2_wb_dat_o <=#Tp m2_wb_dat_i;
|
s2_wb_dat_o <=#Tp m2_wb_dat_i;
|
s2_wb_cyc_o <=#Tp 1'b1;
|
s2_wb_cyc_o <=#Tp 1'b1;
|
s2_wb_stb_o <=#Tp 1'b1;
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s2_wb_stb_o <=#Tp 1'b1;
|
end
|
end
|
else
|
else
|
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
|
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
|
end
|
end
|
5'b10_10_1, 5'b10_11_1 :
|
5'b10_10_1, 5'b10_11_1 :
|
begin
|
begin
|
m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
|
m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
|
if(`M1_ADDRESSED_S1)
|
if(`M1_ADDRESSED_S1)
|
begin
|
begin
|
s1_wb_cyc_o <=#Tp 1'b0;
|
s1_wb_cyc_o <=#Tp 1'b0;
|
s1_wb_stb_o <=#Tp 1'b0;
|
s1_wb_stb_o <=#Tp 1'b0;
|
end
|
end
|
else if(`M1_ADDRESSED_S2)
|
else if(`M1_ADDRESSED_S2)
|
begin
|
begin
|
s2_wb_cyc_o <=#Tp 1'b0;
|
s2_wb_cyc_o <=#Tp 1'b0;
|
s2_wb_stb_o <=#Tp 1'b0;
|
s2_wb_stb_o <=#Tp 1'b0;
|
end
|
end
|
end
|
end
|
5'b01_01_1, 5'b01_11_1 :
|
5'b01_01_1, 5'b01_11_1 :
|
begin
|
begin
|
m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
|
m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
|
if(`M2_ADDRESSED_S1)
|
if(`M2_ADDRESSED_S1)
|
begin
|
begin
|
s1_wb_cyc_o <=#Tp 1'b0;
|
s1_wb_cyc_o <=#Tp 1'b0;
|
s1_wb_stb_o <=#Tp 1'b0;
|
s1_wb_stb_o <=#Tp 1'b0;
|
end
|
end
|
else if(`M2_ADDRESSED_S2)
|
else if(`M2_ADDRESSED_S2)
|
begin
|
begin
|
s2_wb_cyc_o <=#Tp 1'b0;
|
s2_wb_cyc_o <=#Tp 1'b0;
|
s2_wb_stb_o <=#Tp 1'b0;
|
s2_wb_stb_o <=#Tp 1'b0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
// Generating Ack for master 1
|
// Generating Ack for master 1
|
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
|
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
|
begin
|
begin
|
if(m1_in_progress)
|
if(m1_in_progress)
|
begin
|
begin
|
if(`M1_ADDRESSED_S1) begin
|
if(`M1_ADDRESSED_S1) begin
|
m1_wb_ack_o <= s1_wb_ack_i;
|
m1_wb_ack_o <= s1_wb_ack_i;
|
m1_wb_dat_o <= s1_wb_dat_i;
|
m1_wb_dat_o <= s1_wb_dat_i;
|
end
|
end
|
else if(`M1_ADDRESSED_S2) begin
|
else if(`M1_ADDRESSED_S2) begin
|
m1_wb_ack_o <= s2_wb_ack_i;
|
m1_wb_ack_o <= s2_wb_ack_i;
|
m1_wb_dat_o <= s2_wb_dat_i;
|
m1_wb_dat_o <= s2_wb_dat_i;
|
end
|
end
|
end
|
end
|
else
|
else
|
m1_wb_ack_o <= 0;
|
m1_wb_ack_o <= 0;
|
end
|
end
|
|
|
|
|
// Generating Ack for master 2
|
// Generating Ack for master 2
|
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
|
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
|
begin
|
begin
|
if(m2_in_progress)
|
if(m2_in_progress)
|
begin
|
begin
|
if(`M2_ADDRESSED_S1) begin
|
if(`M2_ADDRESSED_S1) begin
|
m2_wb_ack_o <= s1_wb_ack_i;
|
m2_wb_ack_o <= s1_wb_ack_i;
|
m2_wb_dat_o <= s1_wb_dat_i;
|
m2_wb_dat_o <= s1_wb_dat_i;
|
end
|
end
|
else if(`M2_ADDRESSED_S2) begin
|
else if(`M2_ADDRESSED_S2) begin
|
m2_wb_ack_o <= s2_wb_ack_i;
|
m2_wb_ack_o <= s2_wb_ack_i;
|
m2_wb_dat_o <= s2_wb_dat_i;
|
m2_wb_dat_o <= s2_wb_dat_i;
|
end
|
end
|
end
|
end
|
else
|
else
|
m2_wb_ack_o <= 0;
|
m2_wb_ack_o <= 0;
|
end
|
end
|
|
|
|
|
// Generating Err for master 1
|
// Generating Err for master 1
|
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
|
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
|
m1_wb_cyc_i or m1_wb_stb_i)
|
m1_wb_cyc_i or m1_wb_stb_i)
|
begin
|
begin
|
if(m1_in_progress) begin
|
if(m1_in_progress) begin
|
if(`M1_ADDRESSED_S1)
|
if(`M1_ADDRESSED_S1)
|
m1_wb_err_o <= s1_wb_err_i;
|
m1_wb_err_o <= s1_wb_err_i;
|
else if(`M1_ADDRESSED_S2)
|
else if(`M1_ADDRESSED_S2)
|
m1_wb_err_o <= s2_wb_err_i;
|
m1_wb_err_o <= s2_wb_err_i;
|
end
|
end
|
else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
|
else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
|
m1_wb_err_o <= 1'b1;
|
m1_wb_err_o <= 1'b1;
|
else
|
else
|
m1_wb_err_o <= 1'b0;
|
m1_wb_err_o <= 1'b0;
|
end
|
end
|
|
|
|
|
// Generating Err for master 2
|
// Generating Err for master 2
|
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
|
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
|
m2_wb_cyc_i or m2_wb_stb_i)
|
m2_wb_cyc_i or m2_wb_stb_i)
|
begin
|
begin
|
if(m2_in_progress) begin
|
if(m2_in_progress) begin
|
if(`M2_ADDRESSED_S1)
|
if(`M2_ADDRESSED_S1)
|
m2_wb_err_o <= s1_wb_err_i;
|
m2_wb_err_o <= s1_wb_err_i;
|
else if(`M2_ADDRESSED_S2)
|
else if(`M2_ADDRESSED_S2)
|
m2_wb_err_o <= s2_wb_err_i;
|
m2_wb_err_o <= s2_wb_err_i;
|
end
|
end
|
else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
|
else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
|
m2_wb_err_o <= 1'b1;
|
m2_wb_err_o <= 1'b1;
|
else
|
else
|
m2_wb_err_o <= 1'b0;
|
m2_wb_err_o <= 1'b0;
|
end
|
end
|
|
|
|
|
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
|
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
|
|
|
|
|
// Activity monitor
|
// Activity monitor
|
integer cnt;
|
integer cnt;
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
always @ (posedge wb_clk_i or posedge wb_rst_i)
|
begin
|
begin
|
if(wb_rst_i)
|
if(wb_rst_i)
|
cnt <=#Tp 0;
|
cnt <=#Tp 0;
|
else
|
else
|
if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
|
if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
|
cnt <=#Tp 0;
|
cnt <=#Tp 0;
|
else
|
else
|
if(s1_wb_cyc_o | s2_wb_cyc_o)
|
if(s1_wb_cyc_o | s2_wb_cyc_o)
|
cnt <=#Tp cnt+1;
|
cnt <=#Tp cnt+1;
|
end
|
end
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
if(cnt==1000) begin
|
if(cnt==1000) begin
|
$display("(%0t)(%m) ERROR: WB activity ??? ", $time);
|
$display("(%0t)(%m) ERROR: WB activity ??? ", $time);
|
if(s1_wb_cyc_o) begin
|
if(s1_wb_cyc_o) begin
|
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
|
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
|
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
|
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
|
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
|
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
|
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
|
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
|
end
|
end
|
else if(s2_wb_cyc_o) begin
|
else if(s2_wb_cyc_o) begin
|
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
|
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
|
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
|
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
|
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
|
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
|
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
|
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
|
end
|
end
|
|
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (posedge wb_clk_i)
|
always @ (posedge wb_clk_i)
|
begin
|
begin
|
if(s1_wb_err_i & s1_wb_cyc_o) begin
|
if(s1_wb_err_i & s1_wb_cyc_o) begin
|
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
|
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
|
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
|
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
|
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
|
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
|
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
|
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
|
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
|
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
|
$stop;
|
$stop;
|
end
|
end
|
if(s2_wb_err_i & s2_wb_cyc_o) begin
|
if(s2_wb_err_i & s2_wb_cyc_o) begin
|
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
|
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
|
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
|
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
|
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
|
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
|
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
|
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
|
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
|
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
endmodule
|
endmodule
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
