//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// tb_eth_top.v ////
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//// tb_eth_top.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/cores/ethmac/ ////
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//// http://www.opencores.org/cores/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/06 14:41:09 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1 2001/07/30 21:46:09 mohor
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// Revision 1.1 2001/07/30 21:46:09 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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`include "eth_defines.v"
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`include "eth_defines.v"
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`include "eth_timescale.v"
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`include "eth_timescale.v"
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module tb_eth_top();
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module tb_eth_top();
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parameter Tp = 1;
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parameter Tp = 1;
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reg WB_CLK_I;
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reg WB_CLK_I;
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reg WB_RST_I;
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reg WB_RST_I;
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reg [31:0] WB_DAT_I;
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reg [31:0] WB_DAT_I;
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reg [31:0] WB_ADR_I;
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reg [31:0] WB_ADR_I;
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reg [3:0] WB_SEL_I;
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reg [3:0] WB_SEL_I;
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reg WB_WE_I;
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reg WB_WE_I;
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reg WB_CYC_I;
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reg WB_CYC_I;
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reg WB_STB_I;
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reg WB_STB_I;
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reg [1:0] WB_ACK_I;
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reg [1:0] WB_ACK_I;
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wire [31:0] WB_DAT_O;
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wire [31:0] WB_DAT_O;
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wire WB_ACK_O;
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wire WB_ACK_O;
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wire WB_ERR_O;
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wire WB_ERR_O;
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wire [1:0] WB_REQ_O;
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wire [1:0] WB_REQ_O;
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wire [1:0] WB_ND_O;
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wire [1:0] WB_ND_O;
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wire WB_RD_O;
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wire WB_RD_O;
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reg MTxClk;
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reg MTxClk;
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wire [3:0] MTxD;
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wire [3:0] MTxD;
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wire MTxEn;
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wire MTxEn;
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wire MTxErr;
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wire MTxErr;
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reg MRxClk;
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reg MRxClk;
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reg [3:0] MRxD;
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reg [3:0] MRxD;
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reg MRxDV;
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reg MRxDV;
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reg MRxErr;
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reg MRxErr;
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reg MColl;
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reg MColl;
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reg MCrs;
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reg MCrs;
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reg Mdi_I;
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reg Mdi_I;
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wire Mdo_O;
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wire Mdo_O;
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wire Mdo_OE;
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wire Mdo_OE;
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wire Mdc_O;
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wire Mdc_O;
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reg GSR;
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reg GSR;
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reg WishboneBusy;
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reg WishboneBusy;
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reg StartTB;
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reg StartTB;
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reg [9:0] TxBDIndex;
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reg [9:0] TxBDIndex;
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reg [9:0] RxBDIndex;
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reg [9:0] RxBDIndex;
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// Connecting Ethernet top module
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// Connecting Ethernet top module
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eth_top ethtop
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eth_top ethtop
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(
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(
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// WISHBONE common
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// WISHBONE common
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.WB_CLK_I(WB_CLK_I), .WB_RST_I(WB_RST_I), .WB_DAT_I(WB_DAT_I), .WB_DAT_O(WB_DAT_O),
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.wb_clk_i(WB_CLK_I), .wb_rst_i(WB_RST_I), .wb_dat_i(WB_DAT_I), .wb_dat_o(WB_DAT_O),
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// WISHBONE slave
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// WISHBONE slave
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.WB_ADR_I(WB_ADR_I), .WB_SEL_I(WB_SEL_I), .WB_WE_I(WB_WE_I), .WB_CYC_I(WB_CYC_I),
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.wb_adr_i(WB_ADR_I), .wb_sel_i(WB_SEL_I), .wb_we_i(WB_WE_I), .wb_cyc_i(WB_CYC_I),
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.WB_STB_I(WB_STB_I), .WB_ACK_O(WB_ACK_O), .WB_ERR_O(WB_ERR_O), .WB_REQ_O(WB_REQ_O),
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.wb_stb_i(WB_STB_I), .wb_ack_o(WB_ACK_O), .wb_err_o(WB_ERR_O), .wb_req_o(WB_REQ_O),
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.WB_ACK_I(WB_ACK_I), .WB_ND_O(WB_ND_O), .WB_RD_O(WB_RD_O),
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.wb_ack_i(WB_ACK_I), .wb_nd_o(WB_ND_O), .wb_rd_o(WB_RD_O),
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//TX
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//TX
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.MTxClk_I(MTxClk), .MTxD_O(MTxD), .MTxEn_O(MTxEn), .MTxErr_O(MTxErr),
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.mtxclk_pad_i(MTxClk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
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//RX
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//RX
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.MRxClk_I(MRxClk), .MRxD_I(MRxD), .MRxDV_I(MRxDV), .MRxErr_I(MRxErr), .MColl_I(MColl), .MCrs_I(MCrs),
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.mrxclk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
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.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
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// MIIM
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// MIIM
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.Mdc_O(Mdc_O), .Mdi_I(Mdi_I), .Mdo_O(Mdo_O), .Mdo_OE(Mdo_OE)
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.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_pad_oe(Mdo_OE)
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);
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);
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initial
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initial
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begin
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begin
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WB_CLK_I = 1'b0;
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WB_CLK_I = 1'b0;
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WB_DAT_I = 32'hx;
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WB_DAT_I = 32'hx;
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WB_ADR_I = 32'hx;
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WB_ADR_I = 32'hx;
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WB_SEL_I = 4'hx;
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WB_SEL_I = 4'hx;
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WB_WE_I = 1'bx;
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WB_WE_I = 1'bx;
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WB_CYC_I = 1'b0;
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WB_CYC_I = 1'b0;
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WB_STB_I = 1'b0;
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WB_STB_I = 1'b0;
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WB_ACK_I = 2'h0;
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WB_ACK_I = 2'h0;
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MTxClk = 1'b0;
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MTxClk = 1'b0;
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MRxClk = 1'b0;
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MRxClk = 1'b0;
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MRxD = 4'h0;
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MRxD = 4'h0;
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MRxDV = 1'b0;
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MRxDV = 1'b0;
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MRxErr = 1'b0;
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MRxErr = 1'b0;
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MColl = 1'b0;
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MColl = 1'b0;
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MCrs = 1'b0;
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MCrs = 1'b0;
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Mdi_I = 1'b0;
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Mdi_I = 1'b0;
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WishboneBusy = 1'b0;
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WishboneBusy = 1'b0;
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TxBDIndex = 10'h0;
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TxBDIndex = 10'h0;
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RxBDIndex = 10'h0;
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RxBDIndex = 10'h0;
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end
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end
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// Reset pulse
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// Reset pulse
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initial
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initial
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begin
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begin
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GSR = 1'b0;
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GSR = 1'b0;
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WB_RST_I = 1'b0;
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WB_RST_I = 1'b0;
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#100 WB_RST_I = 1'b1;
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#100 WB_RST_I = 1'b1;
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GSR = 1'b1;
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GSR = 1'b1;
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#100 WB_RST_I = 1'b0;
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#100 WB_RST_I = 1'b0;
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GSR = 1'b0;
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GSR = 1'b0;
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#100 StartTB = 1'b1;
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#100 StartTB = 1'b1;
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end
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end
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assign glbl.GSR = GSR;
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assign glbl.GSR = GSR;
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// Generating WB_CLK_I clock
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// Generating WB_CLK_I clock
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always
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always
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begin
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begin
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// forever #10 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 50.0 MHz
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// forever #10 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 50.0 MHz
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forever #15 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 33.3 MHz
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forever #15 WB_CLK_I = ~WB_CLK_I; // 2*10 ns -> 33.3 MHz
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// forever #18 WB_CLK_I = ~WB_CLK_I; // 2*18 ns -> 27.7 MHz
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// forever #18 WB_CLK_I = ~WB_CLK_I; // 2*18 ns -> 27.7 MHz
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// forever #100 WB_CLK_I = ~WB_CLK_I;
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// forever #100 WB_CLK_I = ~WB_CLK_I;
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end
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end
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// Generating MTxClk clock
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// Generating MTxClk clock
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always
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always
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begin
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begin
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#3 forever #20 MTxClk = ~MTxClk; // 2*20 ns -> 25 MHz
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#3 forever #20 MTxClk = ~MTxClk; // 2*20 ns -> 25 MHz
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// #3 forever #200 MTxClk = ~MTxClk;
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// #3 forever #200 MTxClk = ~MTxClk;
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end
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end
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// Generating MRxClk clock
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// Generating MRxClk clock
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always
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always
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begin
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begin
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#16 forever #20 MRxClk = ~MRxClk; // 2*20 ns -> 25 MHz
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#16 forever #20 MRxClk = ~MRxClk; // 2*20 ns -> 25 MHz
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// #16 forever #250 MRxClk = ~MRxClk;
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// #16 forever #250 MRxClk = ~MRxClk;
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end
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end
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initial
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initial
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begin
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begin
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wait(StartTB); // Start of testbench
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wait(StartTB); // Start of testbench
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WishboneWrite(32'h00000800, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2}); // r_Rst = 1
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WishboneWrite(32'h00000800, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2}); // r_Rst = 1
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WishboneWrite(32'h00000000, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2}); // r_Rst = 0
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WishboneWrite(32'h00000000, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2}); // r_Rst = 0
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WishboneWrite(32'h00000080, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `RX_BD_ADR_ADR<<2});// r_RxBDAddress = 0x80
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WishboneWrite(32'h00000080, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `RX_BD_ADR_ADR<<2});// r_RxBDAddress = 0x80
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WishboneWrite(32'h0002A443, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
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WishboneWrite(32'h0002A443, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
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WishboneWrite(32'h00000004, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `CTRLMODER_ADR<<2});//r_TxFlow = 1
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WishboneWrite(32'h00000004, {`ETHERNET_SPACE, `REG_SPACE, 6'h0, `CTRLMODER_ADR<<2});//r_TxFlow = 1
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SendPacket(16'h0015, 1'b0);
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SendPacket(16'h0015, 1'b0);
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SendPacket(16'h0043, 1'b1); // Control frame
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SendPacket(16'h0043, 1'b1); // Control frame
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SendPacket(16'h0025, 1'b0);
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SendPacket(16'h0025, 1'b0);
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SendPacket(16'h0045, 1'b0);
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SendPacket(16'h0045, 1'b0);
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SendPacket(16'h0025, 1'b0);
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SendPacket(16'h0025, 1'b0);
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ReceivePacket(16'h0012, 1'b1); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
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ReceivePacket(16'h0012, 1'b1); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
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ReceivePacket(16'h0011, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0011, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0017, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0017, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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ReceivePacket(16'h0018, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
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WishboneRead({`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2}); // Read from MODER register
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WishboneRead({`ETHERNET_SPACE, `REG_SPACE, 6'h0, `MODER_ADR<<2}); // Read from MODER register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h0<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h0<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h1<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h1<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h2<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h2<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h3<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h3<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h4<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h4<<2)}); // Read from TxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h80<<2)}); // Read from RxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h80<<2)}); // Read from RxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h81<<2)}); // Read from RxBD register
|
WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h81<<2)}); // Read from RxBD register
|
WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h82<<2)}); // Read from RxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h82<<2)}); // Read from RxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h83<<2)}); // Read from RxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h83<<2)}); // Read from RxBD register
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WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h84<<2)}); // Read from RxBD register
|
WishboneRead({`ETHERNET_SPACE, `BD_SPACE, 2'h0, (10'h84<<2)}); // Read from RxBD register
|
|
|
#10000 $stop;
|
#10000 $stop;
|
end
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end
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|
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task WishboneWrite;
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task WishboneWrite;
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input [31:0] Data;
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input [31:0] Data;
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input [31:0] Address;
|
input [31:0] Address;
|
integer ii;
|
integer ii;
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|
|
begin
|
begin
|
wait (~WishboneBusy);
|
wait (~WishboneBusy);
|
WishboneBusy = 1;
|
WishboneBusy = 1;
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
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#1;
|
#1;
|
WB_ADR_I = Address;
|
WB_ADR_I = Address;
|
WB_DAT_I = Data;
|
WB_DAT_I = Data;
|
WB_WE_I = 1'b1;
|
WB_WE_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_SEL_I = 4'hf;
|
WB_SEL_I = 4'hf;
|
|
|
for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
|
for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
|
begin
|
begin
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
end
|
end
|
|
|
if(ii==20)
|
if(ii==20)
|
begin
|
begin
|
$display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
|
$display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
|
Data, Address, $time);
|
Data, Address, $time);
|
#50 $stop;
|
#50 $stop;
|
end
|
end
|
|
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
if(Address[31:16] == `ETHERNET_SPACE)
|
if(Address[31:16] == `ETHERNET_SPACE)
|
if(Address[15:12] == `REG_SPACE)
|
if(Address[15:12] == `REG_SPACE)
|
$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
|
$write("\nWrite to register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
|
else
|
else
|
if(Address[15:12] == `BD_SPACE)
|
if(Address[15:12] == `BD_SPACE)
|
if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
|
if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
|
begin
|
begin
|
$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address[9:2]);
|
$write("\nWrite to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)\n", Data, Address[9:2]);
|
if(Data[13])
|
if(Data[13])
|
$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
|
$write("Send Control packet (PAUSE = 0x%0h)\n", Data[31:16]);
|
end
|
end
|
else
|
else
|
$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
|
$write("\nWrite to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
|
else
|
else
|
$write("\nWB write Data: 0x%x Addr: 0x%0x", Data, Address);
|
$write("\nWB write Data: 0x%x Addr: 0x%0x", Data, Address);
|
else
|
else
|
$write("\nWARNING !!! WB write to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
|
$write("\nWARNING !!! WB write to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
|
#1;
|
#1;
|
WB_ADR_I = 32'hx;
|
WB_ADR_I = 32'hx;
|
WB_DAT_I = 32'hx;
|
WB_DAT_I = 32'hx;
|
WB_WE_I = 1'bx;
|
WB_WE_I = 1'bx;
|
WB_CYC_I = 1'b0;
|
WB_CYC_I = 1'b0;
|
WB_STB_I = 1'b0;
|
WB_STB_I = 1'b0;
|
WB_SEL_I = 4'hx;
|
WB_SEL_I = 4'hx;
|
#5 WishboneBusy = 0;
|
#5 WishboneBusy = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task WishboneRead;
|
task WishboneRead;
|
input [31:0] Address;
|
input [31:0] Address;
|
reg [31:0] Data;
|
reg [31:0] Data;
|
integer ii;
|
integer ii;
|
|
|
begin
|
begin
|
wait (~WishboneBusy);
|
wait (~WishboneBusy);
|
WishboneBusy = 1;
|
WishboneBusy = 1;
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
#1;
|
#1;
|
WB_ADR_I = Address;
|
WB_ADR_I = Address;
|
WB_WE_I = 1'b0;
|
WB_WE_I = 1'b0;
|
WB_CYC_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_SEL_I = 4'hf;
|
WB_SEL_I = 4'hf;
|
|
|
for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
|
for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
|
begin
|
begin
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
Data = WB_DAT_O;
|
Data = WB_DAT_O;
|
end
|
end
|
|
|
if(ii==20)
|
if(ii==20)
|
begin
|
begin
|
$display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
|
$display("\nERROR: Task WishboneRead(Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
|
Address, $time);
|
Address, $time);
|
#50 $stop;
|
#50 $stop;
|
end
|
end
|
|
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
if(Address[31:16] == `ETHERNET_SPACE)
|
if(Address[31:16] == `ETHERNET_SPACE)
|
if(Address[15:12] == `REG_SPACE)
|
if(Address[15:12] == `REG_SPACE)
|
$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
|
$write("\nRead from register (Data: 0x%x, Reg. Addr: 0x%0x)", Data, Address[9:2]);
|
else
|
else
|
if(Address[15:12] == `BD_SPACE)
|
if(Address[15:12] == `BD_SPACE)
|
if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
|
if(Address[9:2] < tb_eth_top.ethtop.r_RxBDAddress)
|
begin
|
begin
|
$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address[9:2]);
|
$write("\nRead from TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", Data, Address[9:2]);
|
end
|
end
|
else
|
else
|
$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
|
$write("\nRead from RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", Data, Address[9:2]);
|
else
|
else
|
$write("\nWB read Data: 0x%x Addr: 0x%0x", Data, Address);
|
$write("\nWB read Data: 0x%x Addr: 0x%0x", Data, Address);
|
else
|
else
|
$write("\nWARNING !!! WB read to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
|
$write("\nWARNING !!! WB read to non-ethernet space (Data: 0x%x, Addr: 0x%0x)", Data, Address);
|
#1;
|
#1;
|
WB_ADR_I = 32'hx;
|
WB_ADR_I = 32'hx;
|
WB_WE_I = 1'bx;
|
WB_WE_I = 1'bx;
|
WB_CYC_I = 1'b0;
|
WB_CYC_I = 1'b0;
|
WB_STB_I = 1'b0;
|
WB_STB_I = 1'b0;
|
WB_SEL_I = 4'hx;
|
WB_SEL_I = 4'hx;
|
#5 WishboneBusy = 0;
|
#5 WishboneBusy = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
|
|
task SendPacket;
|
task SendPacket;
|
input [15:0] Length;
|
input [15:0] Length;
|
input ControlFrame;
|
input ControlFrame;
|
reg Wrap;
|
reg Wrap;
|
reg [31:0] TempAddr;
|
reg [31:0] TempAddr;
|
reg [31:0] TempData;
|
reg [31:0] TempData;
|
|
|
begin
|
begin
|
if(TxBDIndex == 3) // Only 4 buffer descriptors are used
|
if(TxBDIndex == 3) // Only 4 buffer descriptors are used
|
Wrap = 1'b1;
|
Wrap = 1'b1;
|
else
|
else
|
Wrap = 1'b0;
|
Wrap = 1'b0;
|
|
|
TempAddr = {`ETHERNET_SPACE, `BD_SPACE, 2'h0, (TxBDIndex<<2)};
|
TempAddr = {`ETHERNET_SPACE, `BD_SPACE, 2'h0, (TxBDIndex<<2)};
|
TempData = {Length[15:0], 1'b1, Wrap, ControlFrame, 5'h0, TxBDIndex[7:0]}; // Ready and Wrap = 1
|
TempData = {Length[15:0], 1'b1, Wrap, ControlFrame, 5'h0, TxBDIndex[7:0]}; // Ready and Wrap = 1
|
|
|
#1;
|
#1;
|
if(TxBDIndex == 3) // Only 4 buffer descriptors are used
|
if(TxBDIndex == 3) // Only 4 buffer descriptors are used
|
TxBDIndex = 0;
|
TxBDIndex = 0;
|
else
|
else
|
TxBDIndex = TxBDIndex + 1;
|
TxBDIndex = TxBDIndex + 1;
|
|
|
fork
|
fork
|
begin
|
begin
|
WishboneWrite(TempData, TempAddr); // Writing status to TxBD
|
WishboneWrite(TempData, TempAddr); // Writing status to TxBD
|
end
|
end
|
|
|
begin
|
begin
|
if(~ControlFrame)
|
if(~ControlFrame)
|
WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
|
WaitingForTxDMARequest(4'h1, Length); // Delay, DMALength
|
end
|
end
|
join
|
join
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
|
input [15:0] LengthRx;
|
input [15:0] LengthRx;
|
input RxControlFrame;
|
input RxControlFrame;
|
reg WrapRx;
|
reg WrapRx;
|
reg [31:0] TempRxAddr;
|
reg [31:0] TempRxAddr;
|
reg [31:0] TempRxData;
|
reg [31:0] TempRxData;
|
reg abc;
|
reg abc;
|
begin
|
begin
|
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|
WrapRx = 1'b1;
|
WrapRx = 1'b1;
|
else
|
else
|
WrapRx = 1'b0;
|
WrapRx = 1'b0;
|
|
|
TempRxAddr = {`ETHERNET_SPACE, `BD_SPACE, 2'h0, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
|
TempRxAddr = {`ETHERNET_SPACE, `BD_SPACE, 2'h0, ((tb_eth_top.ethtop.r_RxBDAddress + RxBDIndex)<<2)};
|
|
|
TempRxData = {LengthRx[15:0], 1'b1, WrapRx, 6'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
|
TempRxData = {LengthRx[15:0], 1'b1, WrapRx, 6'h0, RxBDIndex[7:0]}; // Ready and WrapRx = 1 or 0
|
|
|
#1;
|
#1;
|
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|
if(RxBDIndex == 3) // Only 4 buffer descriptors are used
|
RxBDIndex = 0;
|
RxBDIndex = 0;
|
else
|
else
|
RxBDIndex = RxBDIndex + 1;
|
RxBDIndex = RxBDIndex + 1;
|
|
|
abc=1;
|
abc=1;
|
WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
|
WishboneWrite(TempRxData, TempRxAddr); // Writing status to RxBD
|
abc=0;
|
abc=0;
|
fork
|
fork
|
begin
|
begin
|
#200;
|
#200;
|
if(RxControlFrame)
|
if(RxControlFrame)
|
GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
|
GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
|
else
|
else
|
GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
|
GetDataOnMRxD(LengthRx); // LengthRx bytes is comming on MRxD[3:0] signals
|
end
|
end
|
|
|
begin
|
begin
|
if(RxControlFrame)
|
if(RxControlFrame)
|
WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
|
WaitingForRxDMARequest(4'h1, 16'h40); // Delay, DMALength = 64 bytes.
|
else
|
else
|
WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
|
WaitingForRxDMARequest(4'h1, LengthRx); // Delay, DMALength
|
end
|
end
|
join
|
join
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
task WaitingForTxDMARequest;
|
task WaitingForTxDMARequest;
|
input [3:0] Delay;
|
input [3:0] Delay;
|
input [15:0] DMALength;
|
input [15:0] DMALength;
|
integer pp;
|
integer pp;
|
reg [7:0]a, b, c, d;
|
reg [7:0]a, b, c, d;
|
|
|
for(pp=0; pp*4<DMALength; pp=pp+1)
|
for(pp=0; pp*4<DMALength; pp=pp+1)
|
begin
|
begin
|
a = 4*pp[7:0]+3;
|
a = 4*pp[7:0]+3;
|
b = 4*pp[7:0]+2;
|
b = 4*pp[7:0]+2;
|
c = 4*pp[7:0]+1;
|
c = 4*pp[7:0]+1;
|
d = 4*pp[7:0] ;
|
d = 4*pp[7:0] ;
|
@ (posedge WB_REQ_O[0]);
|
@ (posedge WB_REQ_O[0]);
|
repeat(Delay) @(posedge WB_CLK_I);
|
repeat(Delay) @(posedge WB_CLK_I);
|
|
|
wait (~WishboneBusy);
|
wait (~WishboneBusy);
|
WishboneBusy = 1;
|
WishboneBusy = 1;
|
#1;
|
#1;
|
WB_DAT_I = {a, b, c, d};
|
WB_DAT_I = {a, b, c, d};
|
WB_ADR_I = {`ETHERNET_SPACE, `TX_DATA, pp[11:0]};
|
WB_ADR_I = {`ETHERNET_SPACE, `TX_DATA, pp[11:0]};
|
$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
|
$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
|
|
|
WB_WE_I = 1'b1;
|
WB_WE_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_SEL_I = 4'hf;
|
WB_SEL_I = 4'hf;
|
WB_ACK_I[0] = 1'b1;
|
WB_ACK_I[0] = 1'b1;
|
|
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
#1;
|
#1;
|
WB_ADR_I = 32'hx;
|
WB_ADR_I = 32'hx;
|
WB_DAT_I = 32'hx;
|
WB_DAT_I = 32'hx;
|
WB_WE_I = 1'bx;
|
WB_WE_I = 1'bx;
|
WB_CYC_I = 1'b0;
|
WB_CYC_I = 1'b0;
|
WB_STB_I = 1'b0;
|
WB_STB_I = 1'b0;
|
WB_SEL_I = 4'hx;
|
WB_SEL_I = 4'hx;
|
WB_ACK_I[0] = 1'b0;
|
WB_ACK_I[0] = 1'b0;
|
#5 WishboneBusy = 0;
|
#5 WishboneBusy = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task WaitingForRxDMARequest;
|
task WaitingForRxDMARequest;
|
input [3:0] Delay;
|
input [3:0] Delay;
|
input [15:0] DMALengthRx;
|
input [15:0] DMALengthRx;
|
integer rr;
|
integer rr;
|
|
|
for(rr=0; rr*4<DMALengthRx; rr=rr+1)
|
for(rr=0; rr*4<DMALengthRx; rr=rr+1)
|
begin
|
begin
|
@ (posedge WB_REQ_O[1]);
|
@ (posedge WB_REQ_O[1]);
|
repeat(Delay) @(posedge WB_CLK_I);
|
repeat(Delay) @(posedge WB_CLK_I);
|
|
|
wait (~WishboneBusy);
|
wait (~WishboneBusy);
|
WishboneBusy = 1;
|
WishboneBusy = 1;
|
#1;
|
#1;
|
WB_ADR_I = {`ETHERNET_SPACE, `RX_DATA, rr[11:0]};
|
WB_ADR_I = {`ETHERNET_SPACE, `RX_DATA, rr[11:0]};
|
$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
|
$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
|
|
|
WB_WE_I = 1'b1;
|
WB_WE_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_CYC_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_STB_I = 1'b1;
|
WB_SEL_I = 4'hf;
|
WB_SEL_I = 4'hf;
|
WB_ACK_I[1] = 1'b1;
|
WB_ACK_I[1] = 1'b1;
|
|
|
@ (posedge WB_CLK_I);
|
@ (posedge WB_CLK_I);
|
#1;
|
#1;
|
WB_ADR_I = 32'hx;
|
WB_ADR_I = 32'hx;
|
WB_WE_I = 1'bx;
|
WB_WE_I = 1'bx;
|
WB_CYC_I = 1'b0;
|
WB_CYC_I = 1'b0;
|
WB_STB_I = 1'b0;
|
WB_STB_I = 1'b0;
|
WB_SEL_I = 4'hx;
|
WB_SEL_I = 4'hx;
|
WB_ACK_I[1] = 1'b0;
|
WB_ACK_I[1] = 1'b0;
|
#5 WishboneBusy = 0;
|
#5 WishboneBusy = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
task GetDataOnMRxD;
|
task GetDataOnMRxD;
|
input [15:0] Len;
|
input [15:0] Len;
|
integer tt;
|
integer tt;
|
|
|
begin
|
begin
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxDV=1'b1;
|
MRxDV=1'b1;
|
|
|
for(tt=0; tt<15; tt=tt+1)
|
for(tt=0; tt<15; tt=tt+1)
|
begin
|
begin
|
MRxD=4'h5; // preamble
|
MRxD=4'h5; // preamble
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
end
|
end
|
MRxD=4'hd; // SFD
|
MRxD=4'hd; // SFD
|
|
|
for(tt=0; tt<Len; tt=tt+1)
|
for(tt=0; tt<Len; tt=tt+1)
|
begin
|
begin
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxD=tt[3:0];
|
MRxD=tt[3:0];
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxD=tt[7:4];
|
MRxD=tt[7:4];
|
end
|
end
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxDV=1'b0;
|
MRxDV=1'b0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task GetControlDataOnMRxD;
|
task GetControlDataOnMRxD;
|
input [15:0] Timer;
|
input [15:0] Timer;
|
reg [127:0] Packet;
|
reg [127:0] Packet;
|
reg [127:0] Data;
|
reg [127:0] Data;
|
reg [31:0] Crc;
|
reg [31:0] Crc;
|
integer tt;
|
integer tt;
|
|
|
begin
|
begin
|
Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
|
Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
|
Crc = 32'h6014fe08; // not a correct value
|
Crc = 32'h6014fe08; // not a correct value
|
|
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxDV=1'b1;
|
MRxDV=1'b1;
|
|
|
for(tt=0; tt<15; tt=tt+1)
|
for(tt=0; tt<15; tt=tt+1)
|
begin
|
begin
|
MRxD=4'h5; // preamble
|
MRxD=4'h5; // preamble
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
end
|
end
|
MRxD=4'hd; // SFD
|
MRxD=4'hd; // SFD
|
|
|
for(tt=0; tt<32; tt=tt+1)
|
for(tt=0; tt<32; tt=tt+1)
|
begin
|
begin
|
Data = Packet << (tt*4);
|
Data = Packet << (tt*4);
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxD=Data[127:124];
|
MRxD=Data[127:124];
|
end
|
end
|
|
|
for(tt=0; tt<2; tt=tt+1) // timer
|
for(tt=0; tt<2; tt=tt+1) // timer
|
begin
|
begin
|
Data[15:0] = Timer << (tt*8);
|
Data[15:0] = Timer << (tt*8);
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxD=Data[11:8];
|
MRxD=Data[11:8];
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxD=Data[15:12];
|
MRxD=Data[15:12];
|
end
|
end
|
|
|
for(tt=0; tt<42; tt=tt+1) // padding
|
for(tt=0; tt<42; tt=tt+1) // padding
|
begin
|
begin
|
Data[7:0] = 8'h0;
|
Data[7:0] = 8'h0;
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxD=Data[3:0];
|
MRxD=Data[3:0];
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxD=Data[3:0];
|
MRxD=Data[3:0];
|
end
|
end
|
|
|
for(tt=0; tt<4; tt=tt+1) // crc
|
for(tt=0; tt<4; tt=tt+1) // crc
|
begin
|
begin
|
Data[31:0] = Crc << (tt*8);
|
Data[31:0] = Crc << (tt*8);
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxD=Data[27:24];
|
MRxD=Data[27:24];
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxD=Data[31:28];
|
MRxD=Data[31:28];
|
end
|
end
|
|
|
|
|
|
|
@ (posedge MRxClk);
|
@ (posedge MRxClk);
|
MRxDV=1'b0;
|
MRxDV=1'b0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|