//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// tb_ethernet_with_cop.v ////
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//// tb_ethernet_with_cop.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/11 13:29:28 mohor
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// Revision 1.2 2002/10/11 13:29:28 mohor
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// Bist signals added.
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// Bist signals added.
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//
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//
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// Revision 1.1 2002/09/18 16:40:40 mohor
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// Revision 1.1 2002/09/18 16:40:40 mohor
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// Simple testbench that includes eth_cop, eth_host and eth_memory modules.
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// Simple testbench that includes eth_cop, eth_host and eth_memory modules.
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// This testbench is used for testing the whole environment. Use tb_ethernet
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// This testbench is used for testing the whole environment. Use tb_ethernet
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// testbench for testing just the ethernet MAC core (many tests).
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// testbench for testing just the ethernet MAC core (many tests).
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//
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//
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//
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//
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//
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//
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//
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//
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`include "tb_eth_defines.v"
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`include "tb_eth_defines.v"
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`include "eth_defines.v"
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module tb_ethernet_with_cop();
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module tb_ethernet_with_cop();
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parameter Tp = 1;
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parameter Tp = 1;
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reg wb_clk_o;
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reg wb_clk_o;
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reg wb_rst_o;
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reg wb_rst_o;
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reg mtx_clk;
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reg mtx_clk;
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reg mrx_clk;
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reg mrx_clk;
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wire [3:0] MTxD;
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wire [3:0] MTxD;
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wire MTxEn;
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wire MTxEn;
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wire MTxErr;
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wire MTxErr;
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reg [3:0] MRxD; // This goes to PHY
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reg [3:0] MRxD; // This goes to PHY
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reg MRxDV; // This goes to PHY
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reg MRxDV; // This goes to PHY
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reg MRxErr; // This goes to PHY
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reg MRxErr; // This goes to PHY
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reg MColl; // This goes to PHY
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reg MColl; // This goes to PHY
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reg MCrs; // This goes to PHY
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reg MCrs; // This goes to PHY
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wire Mdi_I;
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wire Mdi_I;
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wire Mdo_O;
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wire Mdo_O;
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wire Mdo_OE;
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wire Mdo_OE;
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wire Mdc_O;
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wire Mdc_O;
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integer tx_log;
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integer tx_log;
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integer rx_log;
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integer rx_log;
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reg StartTB;
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reg StartTB;
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`ifdef ETH_XILINX_RAMB4
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`ifdef ETH_XILINX_RAMB4
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reg gsr;
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reg gsr;
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`endif
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`endif
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integer packet_ready_cnt, send_packet_cnt;
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integer packet_ready_cnt, send_packet_cnt;
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// Ethernet Slave Interface signals
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// Ethernet Slave Interface signals
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wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
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wire [31:0] eth_sl_wb_adr_i, eth_sl_wb_dat_o, eth_sl_wb_dat_i;
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wire [3:0] eth_sl_wb_sel_i;
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wire [3:0] eth_sl_wb_sel_i;
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wire eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
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wire eth_sl_wb_we_i, eth_sl_wb_cyc_i, eth_sl_wb_stb_i, eth_sl_wb_ack_o, eth_sl_wb_err_o;
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// Memory Slave Interface signals
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// Memory Slave Interface signals
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wire [31:0] mem_sl_wb_adr_i, mem_sl_wb_dat_o, mem_sl_wb_dat_i;
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wire [31:0] mem_sl_wb_adr_i, mem_sl_wb_dat_o, mem_sl_wb_dat_i;
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wire [3:0] mem_sl_wb_sel_i;
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wire [3:0] mem_sl_wb_sel_i;
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wire mem_sl_wb_we_i, mem_sl_wb_cyc_i, mem_sl_wb_stb_i, mem_sl_wb_ack_o, mem_sl_wb_err_o;
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wire mem_sl_wb_we_i, mem_sl_wb_cyc_i, mem_sl_wb_stb_i, mem_sl_wb_ack_o, mem_sl_wb_err_o;
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// Ethernet Master Interface signals
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// Ethernet Master Interface signals
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wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
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wire [31:0] eth_ma_wb_adr_o, eth_ma_wb_dat_i, eth_ma_wb_dat_o;
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wire [3:0] eth_ma_wb_sel_o;
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wire [3:0] eth_ma_wb_sel_o;
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wire eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
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wire eth_ma_wb_we_o, eth_ma_wb_cyc_o, eth_ma_wb_stb_o, eth_ma_wb_ack_i, eth_ma_wb_err_i;
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`ifdef ETH_WISHBONE_B3
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`ifdef ETH_WISHBONE_B3
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wire [2:0] eth_ma_wb_cti_o;
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wire [2:0] eth_ma_wb_cti_o;
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wire [1:0] eth_ma_wb_bte_o;
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wire [1:0] eth_ma_wb_bte_o;
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`endif
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`endif
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// Host Master Interface signals
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// Host Master Interface signals
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wire [31:0] host_ma_wb_adr_o, host_ma_wb_dat_i, host_ma_wb_dat_o;
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wire [31:0] host_ma_wb_adr_o, host_ma_wb_dat_i, host_ma_wb_dat_o;
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wire [3:0] host_ma_wb_sel_o;
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wire [3:0] host_ma_wb_sel_o;
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wire host_ma_wb_we_o, host_ma_wb_cyc_o, host_ma_wb_stb_o, host_ma_wb_ack_i, host_ma_wb_err_i;
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wire host_ma_wb_we_o, host_ma_wb_cyc_o, host_ma_wb_stb_o, host_ma_wb_ack_i, host_ma_wb_err_i;
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eth_cop i_eth_cop
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eth_cop i_eth_cop
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(
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(
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// WISHBONE common
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// WISHBONE common
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.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
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.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
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// WISHBONE MASTER 1 Ethernet Master Interface is connected here
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// WISHBONE MASTER 1 Ethernet Master Interface is connected here
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.m1_wb_adr_i(eth_ma_wb_adr_o), .m1_wb_sel_i(eth_ma_wb_sel_o), .m1_wb_we_i (eth_ma_wb_we_o),
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.m1_wb_adr_i(eth_ma_wb_adr_o), .m1_wb_sel_i(eth_ma_wb_sel_o), .m1_wb_we_i (eth_ma_wb_we_o),
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.m1_wb_dat_o(eth_ma_wb_dat_i), .m1_wb_dat_i(eth_ma_wb_dat_o), .m1_wb_cyc_i(eth_ma_wb_cyc_o),
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.m1_wb_dat_o(eth_ma_wb_dat_i), .m1_wb_dat_i(eth_ma_wb_dat_o), .m1_wb_cyc_i(eth_ma_wb_cyc_o),
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.m1_wb_stb_i(eth_ma_wb_stb_o), .m1_wb_ack_o(eth_ma_wb_ack_i), .m1_wb_err_o(eth_ma_wb_err_i),
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.m1_wb_stb_i(eth_ma_wb_stb_o), .m1_wb_ack_o(eth_ma_wb_ack_i), .m1_wb_err_o(eth_ma_wb_err_i),
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// WISHBONE MASTER 2 Host Interface is connected here
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// WISHBONE MASTER 2 Host Interface is connected here
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.m2_wb_adr_i(host_ma_wb_adr_o), .m2_wb_sel_i(host_ma_wb_sel_o), .m2_wb_we_i (host_ma_wb_we_o),
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.m2_wb_adr_i(host_ma_wb_adr_o), .m2_wb_sel_i(host_ma_wb_sel_o), .m2_wb_we_i (host_ma_wb_we_o),
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.m2_wb_dat_o(host_ma_wb_dat_i), .m2_wb_dat_i(host_ma_wb_dat_o), .m2_wb_cyc_i(host_ma_wb_cyc_o),
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.m2_wb_dat_o(host_ma_wb_dat_i), .m2_wb_dat_i(host_ma_wb_dat_o), .m2_wb_cyc_i(host_ma_wb_cyc_o),
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.m2_wb_stb_i(host_ma_wb_stb_o), .m2_wb_ack_o(host_ma_wb_ack_i), .m2_wb_err_o(host_ma_wb_err_i),
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.m2_wb_stb_i(host_ma_wb_stb_o), .m2_wb_ack_o(host_ma_wb_ack_i), .m2_wb_err_o(host_ma_wb_err_i),
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// WISHBONE slave 1 Ethernet Slave Interface is connected here
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// WISHBONE slave 1 Ethernet Slave Interface is connected here
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.s1_wb_adr_o(eth_sl_wb_adr_i), .s1_wb_sel_o(eth_sl_wb_sel_i), .s1_wb_we_o (eth_sl_wb_we_i),
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.s1_wb_adr_o(eth_sl_wb_adr_i), .s1_wb_sel_o(eth_sl_wb_sel_i), .s1_wb_we_o (eth_sl_wb_we_i),
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.s1_wb_cyc_o(eth_sl_wb_cyc_i), .s1_wb_stb_o(eth_sl_wb_stb_i), .s1_wb_ack_i(eth_sl_wb_ack_o),
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.s1_wb_cyc_o(eth_sl_wb_cyc_i), .s1_wb_stb_o(eth_sl_wb_stb_i), .s1_wb_ack_i(eth_sl_wb_ack_o),
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.s1_wb_err_i(eth_sl_wb_err_o), .s1_wb_dat_i(eth_sl_wb_dat_o), .s1_wb_dat_o(eth_sl_wb_dat_i),
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.s1_wb_err_i(eth_sl_wb_err_o), .s1_wb_dat_i(eth_sl_wb_dat_o), .s1_wb_dat_o(eth_sl_wb_dat_i),
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// WISHBONE slave 2 Memory Interface is connected here
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// WISHBONE slave 2 Memory Interface is connected here
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.s2_wb_adr_o(mem_sl_wb_adr_i), .s2_wb_sel_o(mem_sl_wb_sel_i), .s2_wb_we_o (mem_sl_wb_we_i),
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.s2_wb_adr_o(mem_sl_wb_adr_i), .s2_wb_sel_o(mem_sl_wb_sel_i), .s2_wb_we_o (mem_sl_wb_we_i),
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.s2_wb_cyc_o(mem_sl_wb_cyc_i), .s2_wb_stb_o(mem_sl_wb_stb_i), .s2_wb_ack_i(mem_sl_wb_ack_o),
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.s2_wb_cyc_o(mem_sl_wb_cyc_i), .s2_wb_stb_o(mem_sl_wb_stb_i), .s2_wb_ack_i(mem_sl_wb_ack_o),
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.s2_wb_err_i(mem_sl_wb_err_o), .s2_wb_dat_i(mem_sl_wb_dat_o), .s2_wb_dat_o(mem_sl_wb_dat_i)
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.s2_wb_err_i(mem_sl_wb_err_o), .s2_wb_dat_i(mem_sl_wb_dat_o), .s2_wb_dat_o(mem_sl_wb_dat_i)
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);
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);
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// Connecting Ethernet top module
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// Connecting Ethernet top module
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eth_top ethtop
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eth_top ethtop
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(
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(
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// WISHBONE common
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// WISHBONE common
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.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
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.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
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// WISHBONE slave
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// WISHBONE slave
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.wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i), .wb_we_i(eth_sl_wb_we_i),
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.wb_adr_i(eth_sl_wb_adr_i[11:2]), .wb_sel_i(eth_sl_wb_sel_i), .wb_we_i(eth_sl_wb_we_i),
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.wb_cyc_i(eth_sl_wb_cyc_i), .wb_stb_i(eth_sl_wb_stb_i), .wb_ack_o(eth_sl_wb_ack_o),
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.wb_cyc_i(eth_sl_wb_cyc_i), .wb_stb_i(eth_sl_wb_stb_i), .wb_ack_o(eth_sl_wb_ack_o),
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.wb_err_o(eth_sl_wb_err_o), .wb_dat_i(eth_sl_wb_dat_i), .wb_dat_o(eth_sl_wb_dat_o),
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.wb_err_o(eth_sl_wb_err_o), .wb_dat_i(eth_sl_wb_dat_i), .wb_dat_o(eth_sl_wb_dat_o),
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// WISHBONE master
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// WISHBONE master
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.m_wb_adr_o(eth_ma_wb_adr_o), .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
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.m_wb_adr_o(eth_ma_wb_adr_o), .m_wb_sel_o(eth_ma_wb_sel_o), .m_wb_we_o(eth_ma_wb_we_o),
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.m_wb_dat_i(eth_ma_wb_dat_i), .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
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.m_wb_dat_i(eth_ma_wb_dat_i), .m_wb_dat_o(eth_ma_wb_dat_o), .m_wb_cyc_o(eth_ma_wb_cyc_o),
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.m_wb_stb_o(eth_ma_wb_stb_o), .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
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.m_wb_stb_o(eth_ma_wb_stb_o), .m_wb_ack_i(eth_ma_wb_ack_i), .m_wb_err_i(eth_ma_wb_err_i),
|
|
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`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
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.m_wb_cti_o(eth_ma_wb_cti_o), .m_wb_bte_o(eth_ma_wb_bte_o),
|
.m_wb_cti_o(eth_ma_wb_cti_o), .m_wb_bte_o(eth_ma_wb_bte_o),
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`endif
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`endif
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//TX
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//TX
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.mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
|
.mtx_clk_pad_i(mtx_clk), .mtxd_pad_o(MTxD), .mtxen_pad_o(MTxEn), .mtxerr_pad_o(MTxErr),
|
|
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//RX
|
//RX
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.mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
|
.mrx_clk_pad_i(mrx_clk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
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.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
|
.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
|
|
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// MIIM
|
// MIIM
|
.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
|
.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoe_o(Mdo_OE),
|
|
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.int_o()
|
.int_o()
|
|
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// Bist
|
// Bist
|
`ifdef ETH_BIST
|
`ifdef ETH_BIST
|
,
|
,
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.scanb_rst (1'b0),
|
.scanb_rst (1'b0),
|
.scanb_clk (1'b0),
|
.scanb_clk (1'b0),
|
.scanb_si (1'b0),
|
.scanb_si (1'b0),
|
.scanb_so (),
|
.scanb_so (),
|
.scanb_en (1'b0)
|
.scanb_en (1'b0)
|
`endif
|
`endif
|
|
|
);
|
);
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|
|
|
|
|
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// Connecting Memory Interface Module
|
// Connecting Memory Interface Module
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eth_memory i_eth_memory
|
eth_memory i_eth_memory
|
(
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(
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// WISHBONE common
|
// WISHBONE common
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.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
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.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
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|
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// WISHBONE slave: Memory Interface is connected here
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// WISHBONE slave: Memory Interface is connected here
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.wb_adr_i(mem_sl_wb_adr_i), .wb_sel_i(mem_sl_wb_sel_i), .wb_we_i (mem_sl_wb_we_i),
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.wb_adr_i(mem_sl_wb_adr_i), .wb_sel_i(mem_sl_wb_sel_i), .wb_we_i (mem_sl_wb_we_i),
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.wb_cyc_i(mem_sl_wb_cyc_i), .wb_stb_i(mem_sl_wb_stb_i), .wb_ack_o(mem_sl_wb_ack_o),
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.wb_cyc_i(mem_sl_wb_cyc_i), .wb_stb_i(mem_sl_wb_stb_i), .wb_ack_o(mem_sl_wb_ack_o),
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.wb_err_o(mem_sl_wb_err_o), .wb_dat_o(mem_sl_wb_dat_o), .wb_dat_i(mem_sl_wb_dat_i)
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.wb_err_o(mem_sl_wb_err_o), .wb_dat_o(mem_sl_wb_dat_o), .wb_dat_i(mem_sl_wb_dat_i)
|
);
|
);
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|
|
|
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// Connecting Host Interface
|
// Connecting Host Interface
|
eth_host eth_host
|
eth_host eth_host
|
(
|
(
|
// WISHBONE common
|
// WISHBONE common
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.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
|
.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
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|
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// WISHBONE master
|
// WISHBONE master
|
.wb_adr_o(host_ma_wb_adr_o), .wb_sel_o(host_ma_wb_sel_o), .wb_we_o (host_ma_wb_we_o),
|
.wb_adr_o(host_ma_wb_adr_o), .wb_sel_o(host_ma_wb_sel_o), .wb_we_o (host_ma_wb_we_o),
|
.wb_dat_i(host_ma_wb_dat_i), .wb_dat_o(host_ma_wb_dat_o), .wb_cyc_o(host_ma_wb_cyc_o),
|
.wb_dat_i(host_ma_wb_dat_i), .wb_dat_o(host_ma_wb_dat_o), .wb_cyc_o(host_ma_wb_cyc_o),
|
.wb_stb_o(host_ma_wb_stb_o), .wb_ack_i(host_ma_wb_ack_i), .wb_err_i(host_ma_wb_err_i)
|
.wb_stb_o(host_ma_wb_stb_o), .wb_ack_i(host_ma_wb_ack_i), .wb_err_i(host_ma_wb_err_i)
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
// Reset pulse
|
// Reset pulse
|
initial
|
initial
|
begin
|
begin
|
MCrs=0; // This should come from PHY
|
MCrs=0; // This should come from PHY
|
MColl=0; // This should come from PHY
|
MColl=0; // This should come from PHY
|
MRxD=0; // This should come from PHY
|
MRxD=0; // This should come from PHY
|
MRxDV=0; // This should come from PHY
|
MRxDV=0; // This should come from PHY
|
MRxErr=0; // This should come from PHY
|
MRxErr=0; // This should come from PHY
|
packet_ready_cnt = 0;
|
packet_ready_cnt = 0;
|
send_packet_cnt = 0;
|
send_packet_cnt = 0;
|
tx_log = $fopen("ethernet_tx.log");
|
tx_log = $fopen("ethernet_tx.log");
|
rx_log = $fopen("ethernet_rx.log");
|
rx_log = $fopen("ethernet_rx.log");
|
wb_rst_o = 1'b1;
|
wb_rst_o = 1'b1;
|
`ifdef ETH_XILINX_RAMB4
|
`ifdef ETH_XILINX_RAMB4
|
gsr = 1'b0;
|
gsr = 1'b0;
|
#100 gsr = 1'b1;
|
#100 gsr = 1'b1;
|
#100 gsr = 1'b0;
|
#100 gsr = 1'b0;
|
`endif
|
`endif
|
#100 wb_rst_o = 1'b0;
|
#100 wb_rst_o = 1'b0;
|
#100 StartTB = 1'b1;
|
#100 StartTB = 1'b1;
|
end
|
end
|
|
|
`ifdef ETH_XILINX_RAMB4
|
`ifdef ETH_XILINX_RAMB4
|
assign glbl.GSR = gsr;
|
assign glbl.GSR = gsr;
|
`endif
|
`endif
|
|
|
|
|
|
|
// Generating wb_clk_o clock
|
// Generating wb_clk_o clock
|
initial
|
initial
|
begin
|
begin
|
wb_clk_o=0;
|
wb_clk_o=0;
|
// forever #20 wb_clk_o = ~wb_clk_o; // 2*20 ns -> 25 MHz
|
// forever #20 wb_clk_o = ~wb_clk_o; // 2*20 ns -> 25 MHz
|
forever #12.5 wb_clk_o = ~wb_clk_o; // 2*12.5 ns -> 40 MHz
|
forever #12.5 wb_clk_o = ~wb_clk_o; // 2*12.5 ns -> 40 MHz
|
end
|
end
|
|
|
// Generating mtx_clk clock
|
// Generating mtx_clk clock
|
initial
|
initial
|
begin
|
begin
|
mtx_clk=0;
|
mtx_clk=0;
|
#3 forever #20 mtx_clk = ~mtx_clk; // 2*20 ns -> 25 MHz
|
#3 forever #20 mtx_clk = ~mtx_clk; // 2*20 ns -> 25 MHz
|
end
|
end
|
|
|
// Generating mrx_clk clock
|
// Generating mrx_clk clock
|
initial
|
initial
|
begin
|
begin
|
mrx_clk=0;
|
mrx_clk=0;
|
#16 forever #20 mrx_clk = ~mrx_clk; // 2*20 ns -> 25 MHz
|
#16 forever #20 mrx_clk = ~mrx_clk; // 2*20 ns -> 25 MHz
|
end
|
end
|
|
|
reg [31:0] tmp;
|
reg [31:0] tmp;
|
initial
|
initial
|
begin
|
begin
|
wait(StartTB); // Start of testbench
|
wait(StartTB); // Start of testbench
|
|
|
|
|
eth_host.wb_write(`ETH_MODER, 4'hf, 32'h0); // Reset OFF
|
eth_host.wb_write(`ETH_MODER, 4'hf, 32'h0); // Reset OFF
|
eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
|
eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
|
eth_host.wb_write(`ETH_MAC_ADDR1, 4'hf, 32'h0002); // Set ETH_MAC_ADDR1 register
|
eth_host.wb_write(`ETH_MAC_ADDR1, 4'hf, 32'h0002); // Set ETH_MAC_ADDR1 register
|
eth_host.wb_write(`ETH_MAC_ADDR0, 4'hf, 32'h03040506); // Set ETH_MAC_ADDR0 register
|
eth_host.wb_write(`ETH_MAC_ADDR0, 4'hf, 32'h03040506); // Set ETH_MAC_ADDR0 register
|
|
|
initialize_txbd(3);
|
initialize_txbd(3);
|
initialize_rxbd(4);
|
initialize_rxbd(4);
|
|
|
// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
|
// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
|
// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
|
// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
|
// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN |
|
// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN |
|
// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
|
// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
|
// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_BRO |
|
// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_BRO |
|
// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
|
// `ETH_MODER_CRCEN | `ETH_MODER_PAD); // Set MODER register
|
// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
|
// eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
|
// `ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK); // Set MODER register
|
// `ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK); // Set MODER register
|
eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
|
eth_host.wb_write(`ETH_MODER, 4'hf, `ETH_MODER_RXEN | `ETH_MODER_TXEN | `ETH_MODER_PRO |
|
`ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK |
|
`ETH_MODER_CRCEN | `ETH_MODER_PAD | `ETH_MODER_LOOPBCK |
|
`ETH_MODER_FULLD); // Set MODER register
|
`ETH_MODER_FULLD); // Set MODER register
|
eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
|
eth_host.wb_read(`ETH_MODER, 4'hf, tmp);
|
|
|
set_packet(16'h364, 8'h1);
|
set_packet(16'h364, 8'h1);
|
set_packet(16'h234, 8'h11);
|
set_packet(16'h234, 8'h11);
|
send_packet;
|
send_packet;
|
repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
|
repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
|
|
|
// repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
|
// repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
|
set_packet(16'h534, 8'h21);
|
set_packet(16'h534, 8'h21);
|
// set_packet(16'h34, 8'h31);
|
// set_packet(16'h34, 8'h31);
|
|
|
/*
|
/*
|
eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h4); // Enable Tx Flow control
|
eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h4); // Enable Tx Flow control
|
eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h5); // Enable Tx Flow control
|
eth_host.wb_write(`ETH_CTRLMODER, 4'hf, 32'h5); // Enable Tx Flow control
|
eth_host.wb_write(`ETH_TX_CTRL, 4'hf, 32'h10013); // Send Control frame with PAUSE_TV=0x0013
|
eth_host.wb_write(`ETH_TX_CTRL, 4'hf, 32'h10013); // Send Control frame with PAUSE_TV=0x0013
|
*/
|
*/
|
|
|
send_packet;
|
send_packet;
|
repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
|
repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
|
send_packet;
|
send_packet;
|
repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
|
repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
|
|
|
/*
|
/*
|
send_packet;
|
send_packet;
|
*/
|
*/
|
|
|
|
|
repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
|
repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
|
|
|
/*
|
/*
|
GetDataOnMRxD(113, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
GetDataOnMRxD(113, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
|
|
repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
|
repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
|
|
|
GetDataOnMRxD(500, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
GetDataOnMRxD(500, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
|
|
repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
|
repeat (1000) @(posedge mrx_clk); // Waiting for TxEthMac to finish transmit
|
|
|
|
|
GetDataOnMRxD(1200, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
GetDataOnMRxD(1200, `BROADCAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
|
|
|
|
GetDataOnMRxD(1000, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
GetDataOnMRxD(1000, `UNICAST_XFR); // LengthRx bytes is comming on MRxD[3:0] signals
|
|
|
repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
|
repeat (10000) @(posedge wb_clk_o); // Waiting for TxEthMac to finish transmit
|
|
|
*/
|
*/
|
// Reading and printing interrupts
|
// Reading and printing interrupts
|
eth_host.wb_read(`ETH_INT, 4'hf, tmp);
|
eth_host.wb_read(`ETH_INT, 4'hf, tmp);
|
$display("Print irq = 0x%0x", tmp);
|
$display("Print irq = 0x%0x", tmp);
|
|
|
//Clearing all interrupts
|
//Clearing all interrupts
|
eth_host.wb_write(`ETH_INT, 4'hf, 32'h60);
|
eth_host.wb_write(`ETH_INT, 4'hf, 32'h60);
|
|
|
// Reading and printing interrupts
|
// Reading and printing interrupts
|
eth_host.wb_read(`ETH_INT, 4'hf, tmp);
|
eth_host.wb_read(`ETH_INT, 4'hf, tmp);
|
$display("Print irq = 0x%0x", tmp);
|
$display("Print irq = 0x%0x", tmp);
|
|
|
$display("\n\n End of simulation");
|
$display("\n\n End of simulation");
|
$stop;
|
$stop;
|
|
|
|
|
|
|
end
|
end
|
|
|
|
|
`ifdef ETH_WISHBONE_B3
|
`ifdef ETH_WISHBONE_B3
|
|
|
integer single_cnt_tx, burst_cnt_tx, burst_cnt;
|
integer single_cnt_tx, burst_cnt_tx, burst_cnt;
|
integer single_cnt_rx, burst_cnt_rx;
|
integer single_cnt_rx, burst_cnt_rx;
|
|
|
initial
|
initial
|
begin
|
begin
|
single_cnt_tx=0; burst_cnt_tx=0; burst_cnt=0;
|
single_cnt_tx=0; burst_cnt_tx=0; burst_cnt=0;
|
single_cnt_rx=0; burst_cnt_rx=0;
|
single_cnt_rx=0; burst_cnt_rx=0;
|
end
|
end
|
|
|
// Single and burst cycle watcher
|
// Single and burst cycle watcher
|
always @ (posedge wb_clk_o)
|
always @ (posedge wb_clk_o)
|
begin
|
begin
|
if(eth_ma_wb_ack_i) begin
|
if(eth_ma_wb_ack_i) begin
|
if(eth_ma_wb_cyc_o & eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b000) begin
|
if(eth_ma_wb_cyc_o & eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b000) begin
|
if(burst_cnt!==0)
|
if(burst_cnt!==0)
|
$display("(%0t)(%m) ERROR !!! burst_cnt should be 0 because this is a single access", $time);
|
$display("(%0t)(%m) ERROR !!! burst_cnt should be 0 because this is a single access", $time);
|
else
|
else
|
single_cnt_rx=single_cnt_rx+1;
|
single_cnt_rx=single_cnt_rx+1;
|
end
|
end
|
else if(eth_ma_wb_cyc_o & !eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b000) begin
|
else if(eth_ma_wb_cyc_o & !eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b000) begin
|
if(burst_cnt!==0)
|
if(burst_cnt!==0)
|
$display("(%0t)(%m) ERROR !!! burst_cnt should be 0 because this is a single access", $time);
|
$display("(%0t)(%m) ERROR !!! burst_cnt should be 0 because this is a single access", $time);
|
else
|
else
|
single_cnt_tx=single_cnt_tx+1;
|
single_cnt_tx=single_cnt_tx+1;
|
end
|
end
|
else if(eth_ma_wb_cyc_o & eth_ma_wb_cti_o==3'b010) begin // burst in progress
|
else if(eth_ma_wb_cyc_o & eth_ma_wb_cti_o==3'b010) begin // burst in progress
|
burst_cnt=burst_cnt+1;
|
burst_cnt=burst_cnt+1;
|
end
|
end
|
else if(eth_ma_wb_cyc_o & eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b111 & burst_cnt==(`ETH_BURST_LENGTH-1)) begin
|
else if(eth_ma_wb_cyc_o & eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b111 & burst_cnt==(`ETH_BURST_LENGTH-1)) begin
|
burst_cnt_rx=burst_cnt_rx+1;
|
burst_cnt_rx=burst_cnt_rx+1;
|
burst_cnt=0;
|
burst_cnt=0;
|
end
|
end
|
else if(eth_ma_wb_cyc_o & !eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b111 & burst_cnt==(`ETH_BURST_LENGTH-1)) begin
|
else if(eth_ma_wb_cyc_o & !eth_ma_wb_we_o & eth_ma_wb_cti_o==3'b111 & burst_cnt==(`ETH_BURST_LENGTH-1)) begin
|
burst_cnt_tx=burst_cnt_tx+1;
|
burst_cnt_tx=burst_cnt_tx+1;
|
burst_cnt=0;
|
burst_cnt=0;
|
end
|
end
|
else
|
else
|
$display("(%0t)(%m) ERROR !!! Unknown cycle type or sequence", $time);
|
$display("(%0t)(%m) ERROR !!! Unknown cycle type or sequence", $time);
|
end
|
end
|
end
|
end
|
`endif // ETH_WISHBONE_B3
|
`endif // ETH_WISHBONE_B3
|
|
|
|
|
|
|
task initialize_txbd;
|
task initialize_txbd;
|
input [6:0] txbd_num;
|
input [6:0] txbd_num;
|
|
|
integer i;
|
integer i;
|
integer bd_status_addr, buf_addr, bd_ptr_addr;
|
integer bd_status_addr, buf_addr, bd_ptr_addr;
|
|
|
for(i=0; i<txbd_num; i=i+1) begin
|
for(i=0; i<txbd_num; i=i+1) begin
|
buf_addr = `TX_BUF_BASE + i * 32'h600;
|
buf_addr = `TX_BUF_BASE + i * 32'h600;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_status_addr = `TX_BD_BASE + i * 8;
|
bd_ptr_addr = bd_status_addr + 4;
|
bd_ptr_addr = bd_status_addr + 4;
|
|
|
// Initializing BD - status
|
// Initializing BD - status
|
if(i==txbd_num-1)
|
if(i==txbd_num-1)
|
eth_host.wb_write(bd_status_addr, 4'hf, 32'h00007800); // last BD: + WRAP
|
eth_host.wb_write(bd_status_addr, 4'hf, 32'h00007800); // last BD: + WRAP
|
else
|
else
|
eth_host.wb_write(bd_status_addr, 4'hf, 32'h00005800); // IRQ + PAD + CRC
|
eth_host.wb_write(bd_status_addr, 4'hf, 32'h00005800); // IRQ + PAD + CRC
|
|
|
eth_host.wb_write(bd_ptr_addr, 4'hf, buf_addr); // Initializing BD - pointer
|
eth_host.wb_write(bd_ptr_addr, 4'hf, buf_addr); // Initializing BD - pointer
|
end
|
end
|
endtask // initialize_txbd
|
endtask // initialize_txbd
|
|
|
|
|
task initialize_rxbd;
|
task initialize_rxbd;
|
input [6:0] rxbd_num;
|
input [6:0] rxbd_num;
|
|
|
integer i;
|
integer i;
|
integer bd_status_addr, buf_addr, bd_ptr_addr;
|
integer bd_status_addr, buf_addr, bd_ptr_addr;
|
|
|
for(i=0; i<rxbd_num; i=i+1) begin
|
for(i=0; i<rxbd_num; i=i+1) begin
|
buf_addr = `RX_BUF_BASE + i * 32'h600;
|
buf_addr = `RX_BUF_BASE + i * 32'h600;
|
bd_status_addr = `RX_BD_BASE + i * 8;
|
bd_status_addr = `RX_BD_BASE + i * 8;
|
bd_ptr_addr = bd_status_addr + 4;
|
bd_ptr_addr = bd_status_addr + 4;
|
|
|
// Initializing BD - status
|
// Initializing BD - status
|
if(i==rxbd_num-1)
|
if(i==rxbd_num-1)
|
eth_host.wb_write(bd_status_addr, 4'hf, 32'h0000e000); // last BD: + WRAP
|
eth_host.wb_write(bd_status_addr, 4'hf, 32'h0000e000); // last BD: + WRAP
|
else
|
else
|
eth_host.wb_write(bd_status_addr, 4'hf, 32'h0000c000); // IRQ + PAD + CRC
|
eth_host.wb_write(bd_status_addr, 4'hf, 32'h0000c000); // IRQ + PAD + CRC
|
|
|
eth_host.wb_write(bd_ptr_addr, 4'hf, buf_addr); // Initializing BD - pointer
|
eth_host.wb_write(bd_ptr_addr, 4'hf, buf_addr); // Initializing BD - pointer
|
end
|
end
|
endtask // initialize_rxbd
|
endtask // initialize_rxbd
|
|
|
|
|
task set_packet;
|
task set_packet;
|
input [15:0] len;
|
input [15:0] len;
|
input [7:0] start_data;
|
input [7:0] start_data;
|
|
|
integer i, sd;
|
integer i, sd;
|
integer bd_status_addr, bd_ptr_addr, buffer, bd;
|
integer bd_status_addr, bd_ptr_addr, buffer, bd;
|
|
|
begin
|
begin
|
sd = start_data;
|
sd = start_data;
|
bd_status_addr = `TX_BD_BASE + packet_ready_cnt * 8;
|
bd_status_addr = `TX_BD_BASE + packet_ready_cnt * 8;
|
bd_ptr_addr = bd_status_addr + 4;
|
bd_ptr_addr = bd_status_addr + 4;
|
|
|
// Reading BD + buffer pointer
|
// Reading BD + buffer pointer
|
eth_host.wb_read(bd_status_addr, 4'hf, bd);
|
eth_host.wb_read(bd_status_addr, 4'hf, bd);
|
eth_host.wb_read(bd_ptr_addr, 4'hf, buffer);
|
eth_host.wb_read(bd_ptr_addr, 4'hf, buffer);
|
|
|
while(bd & `ETH_TX_BD_READY) begin // Buffer is ready. Don't touch !!!
|
while(bd & `ETH_TX_BD_READY) begin // Buffer is ready. Don't touch !!!
|
repeat(100) @(posedge wb_clk_o);
|
repeat(100) @(posedge wb_clk_o);
|
i=i+1;
|
i=i+1;
|
eth_host.wb_read(bd_status_addr, 4'hf, bd);
|
eth_host.wb_read(bd_status_addr, 4'hf, bd);
|
if(i>1000) begin
|
if(i>1000) begin
|
$display("(%0t)(%m)Waiting for TxBD ready to clear timeout", $time);
|
$display("(%0t)(%m)Waiting for TxBD ready to clear timeout", $time);
|
$stop;
|
$stop;
|
end
|
end
|
end
|
end
|
|
|
// First write might not be word allign.
|
// First write might not be word allign.
|
if(buffer[1:0]==1) begin
|
if(buffer[1:0]==1) begin
|
eth_host.wb_write(buffer-1, 4'h7, {8'h0, sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2});
|
eth_host.wb_write(buffer-1, 4'h7, {8'h0, sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2});
|
sd=sd+3;
|
sd=sd+3;
|
i=3;
|
i=3;
|
end
|
end
|
else if(buffer[1:0]==2) begin
|
else if(buffer[1:0]==2) begin
|
eth_host.wb_write(buffer-2, 4'h3, {16'h0, sd[7:0], sd[7:0]+3'h1});
|
eth_host.wb_write(buffer-2, 4'h3, {16'h0, sd[7:0], sd[7:0]+3'h1});
|
sd=sd+2;
|
sd=sd+2;
|
i=2;
|
i=2;
|
end
|
end
|
else if(buffer[1:0]==3) begin
|
else if(buffer[1:0]==3) begin
|
eth_host.wb_write(buffer-3, 4'h1, {24'h0, sd[7:0]});
|
eth_host.wb_write(buffer-3, 4'h1, {24'h0, sd[7:0]});
|
sd=sd+1;
|
sd=sd+1;
|
i=1;
|
i=1;
|
end
|
end
|
else
|
else
|
i=0;
|
i=0;
|
|
|
|
|
for(i=i; i<len-4; i=i+4) begin // Last 0-3 bytes are not written
|
for(i=i; i<len-4; i=i+4) begin // Last 0-3 bytes are not written
|
eth_host.wb_write(buffer+i, 4'hf, {sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2, sd[7:0]+3'h3});
|
eth_host.wb_write(buffer+i, 4'hf, {sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2, sd[7:0]+3'h3});
|
sd=sd+4;
|
sd=sd+4;
|
end
|
end
|
|
|
|
|
// Last word
|
// Last word
|
if(len-i==3)
|
if(len-i==3)
|
eth_host.wb_write(buffer+i, 4'he, {sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2, 8'h0});
|
eth_host.wb_write(buffer+i, 4'he, {sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2, 8'h0});
|
else if(len-i==2)
|
else if(len-i==2)
|
eth_host.wb_write(buffer+i, 4'hc, {sd[7:0], sd[7:0]+3'h1, 16'h0});
|
eth_host.wb_write(buffer+i, 4'hc, {sd[7:0], sd[7:0]+3'h1, 16'h0});
|
else if(len-i==1)
|
else if(len-i==1)
|
eth_host.wb_write(buffer+i, 4'h8, {sd[7:0], 24'h0});
|
eth_host.wb_write(buffer+i, 4'h8, {sd[7:0], 24'h0});
|
else if(len-i==4)
|
else if(len-i==4)
|
eth_host.wb_write(buffer+i, 4'hf, {sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2, sd[7:0]+3'h3});
|
eth_host.wb_write(buffer+i, 4'hf, {sd[7:0], sd[7:0]+3'h1, sd[7:0]+3'h2, sd[7:0]+3'h3});
|
else
|
else
|
$display("(%0t)(%m) ERROR", $time);
|
$display("(%0t)(%m) ERROR", $time);
|
|
|
|
|
// Checking WRAP bit
|
// Checking WRAP bit
|
if(bd & `ETH_TX_BD_WRAP)
|
if(bd & `ETH_TX_BD_WRAP)
|
packet_ready_cnt = 0;
|
packet_ready_cnt = 0;
|
else
|
else
|
packet_ready_cnt = packet_ready_cnt+1;
|
packet_ready_cnt = packet_ready_cnt+1;
|
|
|
// Writing len to bd
|
// Writing len to bd
|
bd = bd | (len<<16);
|
bd = bd | (len<<16);
|
eth_host.wb_write(bd_status_addr, 4'hf, bd);
|
eth_host.wb_write(bd_status_addr, 4'hf, bd);
|
|
|
end
|
end
|
endtask // set_packet
|
endtask // set_packet
|
|
|
|
|
task send_packet;
|
task send_packet;
|
|
|
integer bd_status_addr, bd_ptr_addr, buffer, bd;
|
integer bd_status_addr, bd_ptr_addr, buffer, bd;
|
|
|
begin
|
begin
|
bd_status_addr = `TX_BD_BASE + send_packet_cnt * 8;
|
bd_status_addr = `TX_BD_BASE + send_packet_cnt * 8;
|
bd_ptr_addr = bd_status_addr + 4;
|
bd_ptr_addr = bd_status_addr + 4;
|
|
|
// Reading BD + buffer pointer
|
// Reading BD + buffer pointer
|
eth_host.wb_read(bd_status_addr, 4'hf, bd);
|
eth_host.wb_read(bd_status_addr, 4'hf, bd);
|
eth_host.wb_read(bd_ptr_addr, 4'hf, buffer);
|
eth_host.wb_read(bd_ptr_addr, 4'hf, buffer);
|
|
|
if(bd & `ETH_TX_BD_WRAP)
|
if(bd & `ETH_TX_BD_WRAP)
|
send_packet_cnt=0;
|
send_packet_cnt=0;
|
else
|
else
|
send_packet_cnt=send_packet_cnt+1;
|
send_packet_cnt=send_packet_cnt+1;
|
|
|
// Setting ETH_TX_BD_READY bit
|
// Setting ETH_TX_BD_READY bit
|
bd = bd | `ETH_TX_BD_READY;
|
bd = bd | `ETH_TX_BD_READY;
|
eth_host.wb_write(bd_status_addr, 4'hf, bd);
|
eth_host.wb_write(bd_status_addr, 4'hf, bd);
|
end
|
end
|
|
|
|
|
endtask // send_packet
|
endtask // send_packet
|
|
|
|
|
task GetDataOnMRxD;
|
task GetDataOnMRxD;
|
input [15:0] Len;
|
input [15:0] Len;
|
input [31:0] TransferType;
|
input [31:0] TransferType;
|
integer tt;
|
integer tt;
|
|
|
begin
|
begin
|
@ (posedge mrx_clk);
|
@ (posedge mrx_clk);
|
#1MRxDV=1'b1;
|
#1MRxDV=1'b1;
|
|
|
for(tt=0; tt<15; tt=tt+1)
|
for(tt=0; tt<15; tt=tt+1)
|
begin
|
begin
|
MRxD=4'h5; // preamble
|
MRxD=4'h5; // preamble
|
@ (posedge mrx_clk);
|
@ (posedge mrx_clk);
|
#1;
|
#1;
|
end
|
end
|
|
|
MRxD=4'hd; // SFD
|
MRxD=4'hd; // SFD
|
|
|
for(tt=1; tt<(Len+1); tt=tt+1)
|
for(tt=1; tt<(Len+1); tt=tt+1)
|
begin
|
begin
|
@ (posedge mrx_clk);
|
@ (posedge mrx_clk);
|
#1;
|
#1;
|
if(TransferType == `UNICAST_XFR && tt == 1)
|
if(TransferType == `UNICAST_XFR && tt == 1)
|
MRxD= 4'h0; // Unicast transfer
|
MRxD= 4'h0; // Unicast transfer
|
else if(TransferType == `BROADCAST_XFR && tt < 7)
|
else if(TransferType == `BROADCAST_XFR && tt < 7)
|
MRxD = 4'hf;
|
MRxD = 4'hf;
|
else
|
else
|
MRxD=tt[3:0]; // Multicast transfer
|
MRxD=tt[3:0]; // Multicast transfer
|
|
|
@ (posedge mrx_clk);
|
@ (posedge mrx_clk);
|
#1;
|
#1;
|
if(TransferType == `BROADCAST_XFR && tt < 7)
|
if(TransferType == `BROADCAST_XFR && tt < 7)
|
MRxD = 4'hf;
|
MRxD = 4'hf;
|
else
|
else
|
MRxD=tt[7:4];
|
MRxD=tt[7:4];
|
end
|
end
|
|
|
@ (posedge mrx_clk);
|
@ (posedge mrx_clk);
|
#1;
|
#1;
|
MRxDV=1'b0;
|
MRxDV=1'b0;
|
end
|
end
|
endtask // GetDataOnMRxD
|
endtask // GetDataOnMRxD
|
|
|
|
|
endmodule
|
endmodule
|
|
|