//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// tb_cop.v ////
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//// tb_cop.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/??????/ ////
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//// http://www.opencores.org/projects/??????/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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module tb_cop();
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module tb_cop();
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parameter Tp = 1;
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parameter Tp = 1;
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reg wb_clk_o;
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reg wb_clk_o;
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reg wb_rst_o;
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reg wb_rst_o;
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// WISHBONE master 1 (input)
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// WISHBONE master 1 (input)
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reg [31:0] m1_wb_adr_o;
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reg [31:0] m1_wb_adr_o;
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reg [3:0] m1_wb_sel_o;
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reg [3:0] m1_wb_sel_o;
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reg m1_wb_we_o;
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reg m1_wb_we_o;
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wire [31:0] m1_wb_dat_i;
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wire [31:0] m1_wb_dat_i;
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reg [31:0] m1_wb_dat_o;
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reg [31:0] m1_wb_dat_o;
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reg m1_wb_cyc_o;
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reg m1_wb_cyc_o;
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reg m1_wb_stb_o;
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reg m1_wb_stb_o;
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wire m1_wb_ack_i;
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wire m1_wb_ack_i;
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wire m1_wb_err_i;
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wire m1_wb_err_i;
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// WISHBONE master 2 (input)
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// WISHBONE master 2 (input)
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reg [31:0] m2_wb_adr_o;
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reg [31:0] m2_wb_adr_o;
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reg [3:0] m2_wb_sel_o;
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reg [3:0] m2_wb_sel_o;
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reg m2_wb_we_o;
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reg m2_wb_we_o;
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wire [31:0] m2_wb_dat_i;
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wire [31:0] m2_wb_dat_i;
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reg [31:0] m2_wb_dat_o;
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reg [31:0] m2_wb_dat_o;
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reg m2_wb_cyc_o;
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reg m2_wb_cyc_o;
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reg m2_wb_stb_o;
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reg m2_wb_stb_o;
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wire m2_wb_ack_i;
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wire m2_wb_ack_i;
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wire m2_wb_err_i;
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wire m2_wb_err_i;
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// WISHBONE slave 1 (output)
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// WISHBONE slave 1 (output)
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wire [31:0] s1_wb_adr_i;
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wire [31:0] s1_wb_adr_i;
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wire [3:0] s1_wb_sel_i;
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wire [3:0] s1_wb_sel_i;
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wire s1_wb_we_i;
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wire s1_wb_we_i;
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reg [31:0] s1_wb_dat_o;
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reg [31:0] s1_wb_dat_o;
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wire [31:0] s1_wb_dat_i;
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wire [31:0] s1_wb_dat_i;
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wire s1_wb_cyc_i;
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wire s1_wb_cyc_i;
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wire s1_wb_stb_i;
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wire s1_wb_stb_i;
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reg s1_wb_ack_o;
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reg s1_wb_ack_o;
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reg s1_wb_err_o;
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reg s1_wb_err_o;
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// WISHBONE slave 2 (output)
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// WISHBONE slave 2 (output)
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wire [31:0] s2_wb_adr_i;
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wire [31:0] s2_wb_adr_i;
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wire [3:0] s2_wb_sel_i;
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wire [3:0] s2_wb_sel_i;
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wire s2_wb_we_i;
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wire s2_wb_we_i;
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reg [31:0] s2_wb_dat_o;
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reg [31:0] s2_wb_dat_o;
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wire [31:0] s2_wb_dat_i;
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wire [31:0] s2_wb_dat_i;
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wire s2_wb_cyc_i;
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wire s2_wb_cyc_i;
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wire s2_wb_stb_i;
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wire s2_wb_stb_i;
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reg s2_wb_ack_o;
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reg s2_wb_ack_o;
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reg s2_wb_err_o;
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reg s2_wb_err_o;
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reg Wishbone1Busy;
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reg Wishbone1Busy;
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reg Wishbone2Busy;
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reg Wishbone2Busy;
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reg StartTB;
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reg StartTB;
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eth_cop i_eth_cop
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eth_cop i_eth_cop
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(
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(
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// WISHBONE common
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// WISHBONE common
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.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
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.wb_clk_i(wb_clk_o), .wb_rst_i(wb_rst_o),
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// WISHBONE MASTER 1
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// WISHBONE MASTER 1
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.m1_wb_adr_i(m1_wb_adr_o), .m1_wb_sel_i(m1_wb_sel_o), .m1_wb_we_i (m1_wb_we_o), .m1_wb_dat_o(m1_wb_dat_i),
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.m1_wb_adr_i(m1_wb_adr_o), .m1_wb_sel_i(m1_wb_sel_o), .m1_wb_we_i (m1_wb_we_o), .m1_wb_dat_o(m1_wb_dat_i),
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.m1_wb_dat_i(m1_wb_dat_o), .m1_wb_cyc_i(m1_wb_cyc_o), .m1_wb_stb_i(m1_wb_stb_o), .m1_wb_ack_o(m1_wb_ack_i),
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.m1_wb_dat_i(m1_wb_dat_o), .m1_wb_cyc_i(m1_wb_cyc_o), .m1_wb_stb_i(m1_wb_stb_o), .m1_wb_ack_o(m1_wb_ack_i),
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.m1_wb_err_o(m1_wb_err_i),
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.m1_wb_err_o(m1_wb_err_i),
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// WISHBONE MASTER 2
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// WISHBONE MASTER 2
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.m2_wb_adr_i(m2_wb_adr_o), .m2_wb_sel_i(m2_wb_sel_o), .m2_wb_we_i (m2_wb_we_o), .m2_wb_dat_o(m2_wb_dat_i),
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.m2_wb_adr_i(m2_wb_adr_o), .m2_wb_sel_i(m2_wb_sel_o), .m2_wb_we_i (m2_wb_we_o), .m2_wb_dat_o(m2_wb_dat_i),
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.m2_wb_dat_i(m2_wb_dat_o), .m2_wb_cyc_i(m2_wb_cyc_o), .m2_wb_stb_i(m2_wb_stb_o), .m2_wb_ack_o(m2_wb_ack_i),
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.m2_wb_dat_i(m2_wb_dat_o), .m2_wb_cyc_i(m2_wb_cyc_o), .m2_wb_stb_i(m2_wb_stb_o), .m2_wb_ack_o(m2_wb_ack_i),
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.m2_wb_err_o(m2_wb_err_i),
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.m2_wb_err_o(m2_wb_err_i),
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// WISHBONE slave 1
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// WISHBONE slave 1
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.s1_wb_adr_o(s1_wb_adr_i), .s1_wb_sel_o(s1_wb_sel_i), .s1_wb_we_o (s1_wb_we_i), .s1_wb_cyc_o(s1_wb_cyc_i),
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.s1_wb_adr_o(s1_wb_adr_i), .s1_wb_sel_o(s1_wb_sel_i), .s1_wb_we_o (s1_wb_we_i), .s1_wb_cyc_o(s1_wb_cyc_i),
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.s1_wb_stb_o(s1_wb_stb_i), .s1_wb_ack_i(s1_wb_ack_o), .s1_wb_err_i(s1_wb_err_o), .s1_wb_dat_i(s1_wb_dat_o),
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.s1_wb_stb_o(s1_wb_stb_i), .s1_wb_ack_i(s1_wb_ack_o), .s1_wb_err_i(s1_wb_err_o), .s1_wb_dat_i(s1_wb_dat_o),
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.s1_wb_dat_o(s1_wb_dat_i),
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.s1_wb_dat_o(s1_wb_dat_i),
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// WISHBONE slave 2
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// WISHBONE slave 2
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.s2_wb_adr_o(s2_wb_adr_i), .s2_wb_sel_o(s2_wb_sel_i), .s2_wb_we_o (s2_wb_we_i), .s2_wb_cyc_o(s2_wb_cyc_i),
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.s2_wb_adr_o(s2_wb_adr_i), .s2_wb_sel_o(s2_wb_sel_i), .s2_wb_we_o (s2_wb_we_i), .s2_wb_cyc_o(s2_wb_cyc_i),
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.s2_wb_stb_o(s2_wb_stb_i), .s2_wb_ack_i(s2_wb_ack_o), .s2_wb_err_i(s2_wb_err_o), .s2_wb_dat_i(s2_wb_dat_o),
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.s2_wb_stb_o(s2_wb_stb_i), .s2_wb_ack_i(s2_wb_ack_o), .s2_wb_err_i(s2_wb_err_o), .s2_wb_dat_i(s2_wb_dat_o),
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.s2_wb_dat_o(s2_wb_dat_i)
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.s2_wb_dat_o(s2_wb_dat_i)
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);
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);
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/*
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/*
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s1_wb_adr_i m_wb_adr_i
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s1_wb_adr_i m_wb_adr_i
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s1_wb_sel_i m_wb_sel_i
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s1_wb_sel_i m_wb_sel_i
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s1_wb_we_i m_wb_we_i
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s1_wb_we_i m_wb_we_i
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s1_wb_dat_o m_wb_dat_o
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s1_wb_dat_o m_wb_dat_o
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s1_wb_dat_i m_wb_dat_i
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s1_wb_dat_i m_wb_dat_i
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s1_wb_cyc_i m_wb_cyc_i
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s1_wb_cyc_i m_wb_cyc_i
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s1_wb_stb_i m_wb_stb_i
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s1_wb_stb_i m_wb_stb_i
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s1_wb_ack_o m_wb_ack_o
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s1_wb_ack_o m_wb_ack_o
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s1_wb_err_o m_wb_err_o
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s1_wb_err_o m_wb_err_o
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*/
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*/
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initial
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initial
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begin
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begin
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s1_wb_ack_o = 0;
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s1_wb_ack_o = 0;
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s1_wb_err_o = 0;
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s1_wb_err_o = 0;
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s1_wb_dat_o = 0;
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s1_wb_dat_o = 0;
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s2_wb_ack_o = 0;
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s2_wb_ack_o = 0;
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s2_wb_err_o = 0;
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s2_wb_err_o = 0;
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s2_wb_dat_o = 0;
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s2_wb_dat_o = 0;
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// WISHBONE master 1 (input)
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// WISHBONE master 1 (input)
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m1_wb_adr_o = 0;
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m1_wb_adr_o = 0;
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m1_wb_sel_o = 0;
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m1_wb_sel_o = 0;
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m1_wb_we_o = 0;
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m1_wb_we_o = 0;
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m1_wb_dat_o = 0;
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m1_wb_dat_o = 0;
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m1_wb_cyc_o = 0;
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m1_wb_cyc_o = 0;
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m1_wb_stb_o = 0;
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m1_wb_stb_o = 0;
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// WISHBONE master 2 (input)
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// WISHBONE master 2 (input)
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m2_wb_adr_o = 0;
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m2_wb_adr_o = 0;
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m2_wb_sel_o = 0;
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m2_wb_sel_o = 0;
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m2_wb_we_o = 0;
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m2_wb_we_o = 0;
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m2_wb_dat_o = 0;
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m2_wb_dat_o = 0;
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m2_wb_cyc_o = 0;
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m2_wb_cyc_o = 0;
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m2_wb_stb_o = 0;
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m2_wb_stb_o = 0;
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Wishbone1Busy = 1'b0;
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Wishbone1Busy = 1'b0;
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Wishbone2Busy = 1'b0;
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Wishbone2Busy = 1'b0;
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end
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end
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// Reset pulse
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// Reset pulse
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initial
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initial
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begin
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begin
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wb_rst_o = 1'b1;
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wb_rst_o = 1'b1;
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#100 wb_rst_o = 1'b0;
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#100 wb_rst_o = 1'b0;
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#100 StartTB = 1'b1;
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#100 StartTB = 1'b1;
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end
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end
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// Generating WB_CLK_I clock
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// Generating WB_CLK_I clock
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always
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always
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begin
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begin
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wb_clk_o = 0;
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wb_clk_o = 0;
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forever #15 wb_clk_o = ~wb_clk_o; // 2*15 ns -> 33.3 MHz
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forever #15 wb_clk_o = ~wb_clk_o; // 2*15 ns -> 33.3 MHz
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end
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end
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integer seed_wb1, seed_wb2;
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integer seed_wb1, seed_wb2;
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integer jj, kk;
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integer jj, kk;
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initial
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initial
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begin
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begin
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seed_wb1 = 0;
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seed_wb1 = 0;
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seed_wb2 = 5;
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seed_wb2 = 5;
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end
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end
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initial
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initial
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begin
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begin
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wait(StartTB); // Start of testbench
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wait(StartTB); // Start of testbench
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fork
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fork
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begin
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begin
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for(jj=0; jj<100; jj=jj+1)
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for(jj=0; jj<100; jj=jj+1)
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begin
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begin
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if(seed_wb1[3:0]<4)
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if(seed_wb1[3:0]<4)
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begin
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begin
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$display("(%0t) m1 write to eth start (Data = Addr = 0x%0x)", $time, {21'h1a0000, seed_wb1[10:0]}); //0xd0000xxx
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$display("(%0t) m1 write to eth start (Data = Addr = 0x%0x)", $time, {21'h1a0000, seed_wb1[10:0]}); //0xd0000xxx
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Wishbone1Write({21'h1a0000, seed_wb1[10:0]}, {21'h1a0000, seed_wb1[10:0]});
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Wishbone1Write({21'h1a0000, seed_wb1[10:0]}, {21'h1a0000, seed_wb1[10:0]});
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end
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end
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else
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else
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if(seed_wb1[3:0]<=7 && seed_wb1[3:0]>=4)
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if(seed_wb1[3:0]<=7 && seed_wb1[3:0]>=4)
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begin
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begin
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$display("(%0t) m1 read to eth start (Addr = 0x%0x)", $time, {21'h1a0000, seed_wb1[10:0]});
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$display("(%0t) m1 read to eth start (Addr = 0x%0x)", $time, {21'h1a0000, seed_wb1[10:0]});
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Wishbone1Read({21'h1a0000, seed_wb1[10:0]});
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Wishbone1Read({21'h1a0000, seed_wb1[10:0]});
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end
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end
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else
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else
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if(seed_wb1[3:0]<=11 && seed_wb1[3:0]>=8)
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if(seed_wb1[3:0]<=11 && seed_wb1[3:0]>=8)
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begin
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begin
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$display("(%0t) m1 write to memory start (Data = Addr = 0x%0x)", $time, {21'h000040, seed_wb1[10:0]}); //0x00020xxx
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$display("(%0t) m1 write to memory start (Data = Addr = 0x%0x)", $time, {21'h000040, seed_wb1[10:0]}); //0x00020xxx
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Wishbone1Write({21'h1a0000, seed_wb1[10:0]}, {21'h000040, seed_wb1[10:0]});
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Wishbone1Write({21'h1a0000, seed_wb1[10:0]}, {21'h000040, seed_wb1[10:0]});
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end
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end
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else
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else
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if(seed_wb1[3:0]>=12)
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if(seed_wb1[3:0]>=12)
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begin
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begin
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$display("(%0t) m1 read to memory start (Addr = 0x%0x)", $time, {21'h000040, seed_wb1[10:0]});
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$display("(%0t) m1 read to memory start (Addr = 0x%0x)", $time, {21'h000040, seed_wb1[10:0]});
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Wishbone1Read({21'h000040, seed_wb1[10:0]});
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Wishbone1Read({21'h000040, seed_wb1[10:0]});
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end
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end
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#1 seed_wb1 = $random(seed_wb1);
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#1 seed_wb1 = $random(seed_wb1);
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$display("seed_wb1[4:0] = 0x%0x", seed_wb1[4:0]);
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$display("seed_wb1[4:0] = 0x%0x", seed_wb1[4:0]);
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repeat(seed_wb1[4:0]) @ (posedge wb_clk_o);
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repeat(seed_wb1[4:0]) @ (posedge wb_clk_o);
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end
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end
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end
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end
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begin
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begin
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for(kk=0; kk<100; kk=kk+1)
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for(kk=0; kk<100; kk=kk+1)
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begin
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begin
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if(seed_wb2[3:0]<4)
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if(seed_wb2[3:0]<4)
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begin
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begin
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$display("(%0t) m2 write to eth start (Data = Addr = 0x%0x)", $time, {21'h1a0000, seed_wb2[10:0]}); //0xd0000xxx
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$display("(%0t) m2 write to eth start (Data = Addr = 0x%0x)", $time, {21'h1a0000, seed_wb2[10:0]}); //0xd0000xxx
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Wishbone2Write({21'h1a0000, seed_wb2[10:0]}, {21'h1a0000, seed_wb2[10:0]});
|
Wishbone2Write({21'h1a0000, seed_wb2[10:0]}, {21'h1a0000, seed_wb2[10:0]});
|
end
|
end
|
else
|
else
|
if(seed_wb2[3:0]<=7 && seed_wb2[3:0]>=4)
|
if(seed_wb2[3:0]<=7 && seed_wb2[3:0]>=4)
|
begin
|
begin
|
$display("(%0t) m2 read to eth start (Addr = 0x%0x)", $time, {21'h1a0000, seed_wb2[10:0]});
|
$display("(%0t) m2 read to eth start (Addr = 0x%0x)", $time, {21'h1a0000, seed_wb2[10:0]});
|
Wishbone2Read({21'h1a0000, seed_wb2[10:0]});
|
Wishbone2Read({21'h1a0000, seed_wb2[10:0]});
|
end
|
end
|
else
|
else
|
if(seed_wb2[3:0]<=11 && seed_wb2[3:0]>=8)
|
if(seed_wb2[3:0]<=11 && seed_wb2[3:0]>=8)
|
begin
|
begin
|
$display("(%0t) m2 write to memory start (Data = Addr = 0x%0x)", $time, {21'h000040, seed_wb2[10:0]}); //0x00020xxx
|
$display("(%0t) m2 write to memory start (Data = Addr = 0x%0x)", $time, {21'h000040, seed_wb2[10:0]}); //0x00020xxx
|
Wishbone2Write({21'h1a0000, seed_wb2[10:0]}, {21'h000040, seed_wb2[10:0]});
|
Wishbone2Write({21'h1a0000, seed_wb2[10:0]}, {21'h000040, seed_wb2[10:0]});
|
end
|
end
|
else
|
else
|
if(seed_wb2[3:0]>=12)
|
if(seed_wb2[3:0]>=12)
|
begin
|
begin
|
$display("(%0t) m2 read to memory start (Addr = 0x%0x)", $time, {21'h000040, seed_wb2[10:0]});
|
$display("(%0t) m2 read to memory start (Addr = 0x%0x)", $time, {21'h000040, seed_wb2[10:0]});
|
Wishbone2Read({21'h000040, seed_wb2[10:0]});
|
Wishbone2Read({21'h000040, seed_wb2[10:0]});
|
end
|
end
|
|
|
#1 seed_wb2 = $random(seed_wb2);
|
#1 seed_wb2 = $random(seed_wb2);
|
$display("seed_wb2[4:0] = 0x%0x", seed_wb2[4:0]);
|
$display("seed_wb2[4:0] = 0x%0x", seed_wb2[4:0]);
|
repeat(seed_wb2[4:0]) @ (posedge wb_clk_o);
|
repeat(seed_wb2[4:0]) @ (posedge wb_clk_o);
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
|
|
join
|
join
|
|
|
#10000 $stop;
|
#10000 $stop;
|
end
|
end
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
task Wishbone1Write;
|
task Wishbone1Write;
|
input [31:0] Data;
|
input [31:0] Data;
|
input [31:0] Address;
|
input [31:0] Address;
|
integer ii;
|
integer ii;
|
|
|
begin
|
begin
|
wait (~Wishbone1Busy);
|
wait (~Wishbone1Busy);
|
Wishbone1Busy = 1;
|
Wishbone1Busy = 1;
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
#1;
|
#1;
|
m1_wb_adr_o = Address;
|
m1_wb_adr_o = Address;
|
m1_wb_dat_o = Data;
|
m1_wb_dat_o = Data;
|
m1_wb_we_o = 1'b1;
|
m1_wb_we_o = 1'b1;
|
m1_wb_cyc_o = 1'b1;
|
m1_wb_cyc_o = 1'b1;
|
m1_wb_stb_o = 1'b1;
|
m1_wb_stb_o = 1'b1;
|
m1_wb_sel_o = 4'hf;
|
m1_wb_sel_o = 4'hf;
|
|
|
wait(m1_wb_ack_i | m1_wb_err_i); // waiting for acknowledge response
|
wait(m1_wb_ack_i | m1_wb_err_i); // waiting for acknowledge response
|
|
|
// Writing information about the access to the screen
|
// Writing information about the access to the screen
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
if(m1_wb_ack_i)
|
if(m1_wb_ack_i)
|
$display("(%0t) Master1 write cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
$display("(%0t) Master1 write cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
else
|
else
|
$display("(%0t) Master1 write cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
$display("(%0t) Master1 write cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
|
|
#1;
|
#1;
|
m1_wb_adr_o = 32'hx;
|
m1_wb_adr_o = 32'hx;
|
m1_wb_dat_o = 32'hx;
|
m1_wb_dat_o = 32'hx;
|
m1_wb_we_o = 1'bx;
|
m1_wb_we_o = 1'bx;
|
m1_wb_cyc_o = 1'b0;
|
m1_wb_cyc_o = 1'b0;
|
m1_wb_stb_o = 1'b0;
|
m1_wb_stb_o = 1'b0;
|
m1_wb_sel_o = 4'hx;
|
m1_wb_sel_o = 4'hx;
|
#5 Wishbone1Busy = 0;
|
#5 Wishbone1Busy = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task Wishbone1Read;
|
task Wishbone1Read;
|
input [31:0] Address;
|
input [31:0] Address;
|
reg [31:0] Data;
|
reg [31:0] Data;
|
integer ii;
|
integer ii;
|
|
|
begin
|
begin
|
wait (~Wishbone1Busy);
|
wait (~Wishbone1Busy);
|
Wishbone1Busy = 1;
|
Wishbone1Busy = 1;
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
#1;
|
#1;
|
m1_wb_adr_o = Address;
|
m1_wb_adr_o = Address;
|
m1_wb_we_o = 1'b0;
|
m1_wb_we_o = 1'b0;
|
m1_wb_cyc_o = 1'b1;
|
m1_wb_cyc_o = 1'b1;
|
m1_wb_stb_o = 1'b1;
|
m1_wb_stb_o = 1'b1;
|
m1_wb_sel_o = 4'hf;
|
m1_wb_sel_o = 4'hf;
|
|
|
wait(m1_wb_ack_i | m1_wb_err_i); // waiting for acknowledge response
|
wait(m1_wb_ack_i | m1_wb_err_i); // waiting for acknowledge response
|
Data = m1_wb_dat_i;
|
Data = m1_wb_dat_i;
|
|
|
// Writing information about the access to the screen
|
// Writing information about the access to the screen
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
if(m1_wb_ack_i)
|
if(m1_wb_ack_i)
|
$display("(%0t) Master1 read cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
$display("(%0t) Master1 read cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
else
|
else
|
$display("(%0t) Master1 read cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
$display("(%0t) Master1 read cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
|
|
#1;
|
#1;
|
m1_wb_adr_o = 32'hx;
|
m1_wb_adr_o = 32'hx;
|
m1_wb_dat_o = 32'hx;
|
m1_wb_dat_o = 32'hx;
|
m1_wb_we_o = 1'bx;
|
m1_wb_we_o = 1'bx;
|
m1_wb_cyc_o = 1'b0;
|
m1_wb_cyc_o = 1'b0;
|
m1_wb_stb_o = 1'b0;
|
m1_wb_stb_o = 1'b0;
|
m1_wb_sel_o = 4'hx;
|
m1_wb_sel_o = 4'hx;
|
#5 Wishbone1Busy = 0;
|
#5 Wishbone1Busy = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
task Wishbone2Write;
|
task Wishbone2Write;
|
input [31:0] Data;
|
input [31:0] Data;
|
input [31:0] Address;
|
input [31:0] Address;
|
integer ii;
|
integer ii;
|
|
|
begin
|
begin
|
wait (~Wishbone2Busy);
|
wait (~Wishbone2Busy);
|
Wishbone2Busy = 1;
|
Wishbone2Busy = 1;
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
#1;
|
#1;
|
m2_wb_adr_o = Address;
|
m2_wb_adr_o = Address;
|
m2_wb_dat_o = Data;
|
m2_wb_dat_o = Data;
|
m2_wb_we_o = 1'b1;
|
m2_wb_we_o = 1'b1;
|
m2_wb_cyc_o = 1'b1;
|
m2_wb_cyc_o = 1'b1;
|
m2_wb_stb_o = 1'b1;
|
m2_wb_stb_o = 1'b1;
|
m2_wb_sel_o = 4'hf;
|
m2_wb_sel_o = 4'hf;
|
|
|
wait(m2_wb_ack_i | m2_wb_err_i); // waiting for acknowledge response
|
wait(m2_wb_ack_i | m2_wb_err_i); // waiting for acknowledge response
|
|
|
// Writing information about the access to the screen
|
// Writing information about the access to the screen
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
if(m2_wb_ack_i)
|
if(m2_wb_ack_i)
|
$display("(%0t) Master2 write cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
$display("(%0t) Master2 write cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
else
|
else
|
$display("(%0t) Master2 write cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
$display("(%0t) Master2 write cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
|
|
#1;
|
#1;
|
m2_wb_adr_o = 32'hx;
|
m2_wb_adr_o = 32'hx;
|
m2_wb_dat_o = 32'hx;
|
m2_wb_dat_o = 32'hx;
|
m2_wb_we_o = 1'bx;
|
m2_wb_we_o = 1'bx;
|
m2_wb_cyc_o = 1'b0;
|
m2_wb_cyc_o = 1'b0;
|
m2_wb_stb_o = 1'b0;
|
m2_wb_stb_o = 1'b0;
|
m2_wb_sel_o = 4'hx;
|
m2_wb_sel_o = 4'hx;
|
#5 Wishbone2Busy = 0;
|
#5 Wishbone2Busy = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
task Wishbone2Read;
|
task Wishbone2Read;
|
input [31:0] Address;
|
input [31:0] Address;
|
reg [31:0] Data;
|
reg [31:0] Data;
|
integer ii;
|
integer ii;
|
|
|
begin
|
begin
|
wait (~Wishbone2Busy);
|
wait (~Wishbone2Busy);
|
Wishbone2Busy = 1;
|
Wishbone2Busy = 1;
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
#1;
|
#1;
|
m2_wb_adr_o = Address;
|
m2_wb_adr_o = Address;
|
m2_wb_we_o = 1'b0;
|
m2_wb_we_o = 1'b0;
|
m2_wb_cyc_o = 1'b1;
|
m2_wb_cyc_o = 1'b1;
|
m2_wb_stb_o = 1'b1;
|
m2_wb_stb_o = 1'b1;
|
m2_wb_sel_o = 4'hf;
|
m2_wb_sel_o = 4'hf;
|
|
|
wait(m2_wb_ack_i | m2_wb_err_i); // waiting for acknowledge response
|
wait(m2_wb_ack_i | m2_wb_err_i); // waiting for acknowledge response
|
Data = m2_wb_dat_i;
|
Data = m2_wb_dat_i;
|
|
|
// Writing information about the access to the screen
|
// Writing information about the access to the screen
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
if(m2_wb_ack_i)
|
if(m2_wb_ack_i)
|
$display("(%0t) Master2 read cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
$display("(%0t) Master2 read cycle finished ok(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
else
|
else
|
$display("(%0t) Master2 read cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
$display("(%0t) Master2 read cycle finished with error(Data: 0x%0x, Addr: 0x%0x)", $time, Data, Address);
|
|
|
#1;
|
#1;
|
m2_wb_adr_o = 32'hx;
|
m2_wb_adr_o = 32'hx;
|
m2_wb_dat_o = 32'hx;
|
m2_wb_dat_o = 32'hx;
|
m2_wb_we_o = 1'bx;
|
m2_wb_we_o = 1'bx;
|
m2_wb_cyc_o = 1'b0;
|
m2_wb_cyc_o = 1'b0;
|
m2_wb_stb_o = 1'b0;
|
m2_wb_stb_o = 1'b0;
|
m2_wb_sel_o = 4'hx;
|
m2_wb_sel_o = 4'hx;
|
#5 Wishbone2Busy = 0;
|
#5 Wishbone2Busy = 0;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
integer seed_ack_s1, seed_ack_s2;
|
integer seed_ack_s1, seed_ack_s2;
|
integer cnt_s1, cnt_s2;
|
integer cnt_s1, cnt_s2;
|
initial
|
initial
|
begin
|
begin
|
seed_ack_s1 = 1;
|
seed_ack_s1 = 1;
|
cnt_s1 = 1;
|
cnt_s1 = 1;
|
seed_ack_s2 = 2;
|
seed_ack_s2 = 2;
|
cnt_s2 = 32'h88888888;
|
cnt_s2 = 32'h88888888;
|
end
|
end
|
|
|
// Response from slave 1
|
// Response from slave 1
|
always @ (posedge wb_clk_o or posedge wb_rst_o)
|
always @ (posedge wb_clk_o or posedge wb_rst_o)
|
begin
|
begin
|
#1 seed_ack_s1 = $random(seed_ack_s1);
|
#1 seed_ack_s1 = $random(seed_ack_s1);
|
|
|
wait(s1_wb_cyc_i & s1_wb_stb_i);
|
wait(s1_wb_cyc_i & s1_wb_stb_i);
|
|
|
s1_wb_dat_o = cnt_s1;
|
s1_wb_dat_o = cnt_s1;
|
repeat(seed_ack_s1[3:0]) @ (posedge wb_clk_o);
|
repeat(seed_ack_s1[3:0]) @ (posedge wb_clk_o);
|
|
|
#Tp s1_wb_ack_o = 1'b1;
|
#Tp s1_wb_ack_o = 1'b1;
|
|
|
if(~s1_wb_we_i)
|
if(~s1_wb_we_i)
|
cnt_s1=cnt_s1+1;
|
cnt_s1=cnt_s1+1;
|
|
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
#Tp s1_wb_ack_o = 1'b0;
|
#Tp s1_wb_ack_o = 1'b0;
|
end
|
end
|
|
|
// Response from slave 2
|
// Response from slave 2
|
always @ (posedge wb_clk_o or posedge wb_rst_o)
|
always @ (posedge wb_clk_o or posedge wb_rst_o)
|
begin
|
begin
|
#1 seed_ack_s2 = $random(seed_ack_s2);
|
#1 seed_ack_s2 = $random(seed_ack_s2);
|
|
|
wait(s2_wb_cyc_i & s2_wb_stb_i);
|
wait(s2_wb_cyc_i & s2_wb_stb_i);
|
|
|
s2_wb_dat_o = cnt_s2;
|
s2_wb_dat_o = cnt_s2;
|
repeat(seed_ack_s2[3:0]) @ (posedge wb_clk_o);
|
repeat(seed_ack_s2[3:0]) @ (posedge wb_clk_o);
|
|
|
#Tp s2_wb_ack_o = 1'b1;
|
#Tp s2_wb_ack_o = 1'b1;
|
|
|
if(~s1_wb_we_i)
|
if(~s1_wb_we_i)
|
cnt_s2=cnt_s2+1;
|
cnt_s2=cnt_s2+1;
|
|
|
@ (posedge wb_clk_o);
|
@ (posedge wb_clk_o);
|
#Tp s2_wb_ack_o = 1'b0;
|
#Tp s2_wb_ack_o = 1'b0;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|