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Ethernet IP CoreSpecification


Author: Igor Mohor
IgorM@opencores.org



Rev. 1.13
 DATE \@ "MMMM d, yyyy" \* MERGEFORMAT April 15, 2002














This page has been intentionally left blank.
Revision History
Rev.DateAuthorDescription0.113/03/01Igor MohorFirst Draft0.217/03/01Igor MohorMDC clock divider changed. Instead of the clock select bits CLKS[2:0] the clock divider bits CLKDIV[7:0] are used. 1.021/03/01Igor MohorMII module completed. Revision changed to 1.0 due to cvs demands. 1.116/04/01IMDMA support and buffer descriptors added. 1.224/05/01IMRegisters revised.1.305/06/01IMStatus is written to the status registers. DMA channels 2 and 3 are not used any more. Figures that are implementation specific removed from the document.1.403/07/01IMCOLLCONF register changed bit width. BCKPRESS and BCKPNBEN bit removed from MODER. LOOPBCK added. 1.521/07/01IMSignal RD0_O (Restart Descriptor for channel 0) added. Per packet CRC, BD changed.1.603/12/01IMBD section rewritten. 1.705/12/01IMTX_BD_NUM register used instead of RX_BD_BASE_ADDR register. 1.807/01/02IMMinor typos fixed1.930/01/02IMRST bit in MODER register is 1 after reset, initial collision window changed.1.1018/02/02IMAddress recognition system added. Buffer Descriptors changed. DMA section changed. Ports changed. 1.1102/03/02IMTypos fixed, INT_SOURCE and INT_MASK registers changed. 1.1215/03/02IMTX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description changed. 1.1315/04/02Jeanne WiegelmannDocument revised.
List of Contents
 TOC \o "1-3" \h \z  HYPERLINK \l "_Toc6650098" Introduction      PAGEREF _Toc6650098 \h 1
 HYPERLINK \l "_Toc6650100" IO Ports   PAGEREF _Toc6650100 \h 2
 HYPERLINK \l "_Toc6650101" 2.1 Ethernet Core IO ports         PAGEREF _Toc6650101 \h 2
 HYPERLINK \l "_Toc6650102" 2.1.1 Host Interface Ports (common ports)  PAGEREF _Toc6650102 \h 2
 HYPERLINK \l "_Toc6650103" 2.1.2 Host Interface Ports (internal DMA ports)    PAGEREF _Toc6650103 \h 3
 HYPERLINK \l "_Toc6650104" 2.1.3 Host Interface ports (external DMA ports)    PAGEREF _Toc6650104 \h 4
 HYPERLINK \l "_Toc6650105" 2.1.4 PHY Interface ports  PAGEREF _Toc6650105 \h 5
 HYPERLINK \l "_Toc6650106" 2.1.5 Reset Signals        PAGEREF _Toc6650106 \h 7
 HYPERLINK \l "_Toc6650108" Registers  PAGEREF _Toc6650108 \h 8
 HYPERLINK \l "_Toc6650109" 3.1 MODER (Mode Register)  PAGEREF _Toc6650109 \h 9
 HYPERLINK \l "_Toc6650110" 3.2 INT_SOURCE (Interrupt Source Register)         PAGEREF _Toc6650110 \h 11
 HYPERLINK \l "_Toc6650111" 3.3 INT_MASK (Interrupt Mask Register)    PAGEREF _Toc6650111 \h 12
 HYPERLINK \l "_Toc6650112" 3.4 IPGT (Back to Back Inter Packet Gap Register)         PAGEREF _Toc6650112 \h 13
 HYPERLINK \l "_Toc6650113" 3.5 IPGR1 (Non Back to Back Inter Packet Gap Register 1)  PAGEREF _Toc6650113 \h 13
 HYPERLINK \l "_Toc6650114" 3.6 IPGR2 (Non Back to Back Inter Packet Gap Register 2)  PAGEREF _Toc6650114 \h 14
 HYPERLINK \l "_Toc6650115" 3.7 PACKETLEN (Packet Length Register)    PAGEREF _Toc6650115 \h 14
 HYPERLINK \l "_Toc6650116" 3.8 COLLCONF (Collision and Retry Configuration Register)         PAGEREF _Toc6650116 \h 15
 HYPERLINK \l "_Toc6650117" 3.9 TX_BD_NUM (Transmit BD Number Reg.)   PAGEREF _Toc6650117 \h 15
 HYPERLINK \l "_Toc6650118" 3.10 CTRLMODER (Control Module Mode Register)     PAGEREF _Toc6650118 \h 16
 HYPERLINK \l "_Toc6650119" 3.11 MIIMODER (MII Mode Register)         PAGEREF _Toc6650119 \h 16
 HYPERLINK \l "_Toc6650120" 3.12 MIICOMMAND (MII Command Register)    PAGEREF _Toc6650120 \h 17
 HYPERLINK \l "_Toc6650121" 3.13 MIIADDRESS (MII Address Register)    PAGEREF _Toc6650121 \h 17
 HYPERLINK \l "_Toc6650122" 3.14 MIITX_DATA (MII Transmit Data)       PAGEREF _Toc6650122 \h 17
 HYPERLINK \l "_Toc6650123" 3.15 MIIRX_DATA (MII Receive Data)        PAGEREF _Toc6650123 \h 18
 HYPERLINK \l "_Toc6650124" 3.16 MIISTATUS (MII Status Register)      PAGEREF _Toc6650124 \h 18
 HYPERLINK \l "_Toc6650125" 3.17 MAC_ADDR0 (MAC Address Register 0)   PAGEREF _Toc6650125 \h 19
 HYPERLINK \l "_Toc6650126" 3.18 MAC_ADDR1 (MAC Address Register 1)   PAGEREF _Toc6650126 \h 19
 HYPERLINK \l "_Toc6650127" 3.19 HASH0 (HASH Register 0)      PAGEREF _Toc6650127 \h 20
 HYPERLINK \l "_Toc6650128" 3.20 HASH1 (HASH Register 1)      PAGEREF _Toc6650128 \h 20
 HYPERLINK \l "_Toc6650130" Operation         PAGEREF _Toc6650130 \h 21
 HYPERLINK \l "_Toc6650131" 4.1 Host Interface Operation      PAGEREF _Toc6650131 \h 22
 HYPERLINK \l "_Toc6650132" 4.1.1 Configuration Registers     PAGEREF _Toc6650132 \h 22
 HYPERLINK \l "_Toc6650133" 4.1.2 External/Internal DMA Operation     PAGEREF _Toc6650133 \h 22
 HYPERLINK \l "_Toc6650134" 4.1.3 Buffer Descriptors (BD)     PAGEREF _Toc6650134 \h 22
 HYPERLINK \l "_Toc6650135" 4.1.4 Frame Transmission  PAGEREF _Toc6650135 \h 27
 HYPERLINK \l "_Toc6650136" 4.1.5 Frame Reception     PAGEREF _Toc6650136 \h 29
 HYPERLINK \l "_Toc6650137" 4.2. DMA Operation        PAGEREF _Toc6650137 \h 30
 HYPERLINK \l "_Toc6650138" 4.3 TX Ethernet MAC       PAGEREF _Toc6650138 \h 30
 HYPERLINK \l "_Toc6650139" 4.4 RX Ethernet MAC       PAGEREF _Toc6650139 \h 31
 HYPERLINK \l "_Toc6650140" 4.5 MAC Control Module    PAGEREF _Toc6650140 \h 31
 HYPERLINK \l "_Toc6650141" 4.5.1 Control Frame Detection     PAGEREF _Toc6650141 \h 32
 HYPERLINK \l "_Toc6650142" 4.5.2 Control Frame Generation    PAGEREF _Toc6650142 \h 32
 HYPERLINK \l "_Toc6650143" 4.5.3 TX/RX MAC Interface         PAGEREF _Toc6650143 \h 33
 HYPERLINK \l "_Toc6650144" 4.5.4 PAUSE Timer         PAGEREF _Toc6650144 \h 33
 HYPERLINK \l "_Toc6650145" 4.5.5 Slot Timer  PAGEREF _Toc6650145 \h 34
 HYPERLINK \l "_Toc6650146" 4.6 MII Management Module         PAGEREF _Toc6650146 \h 34
 HYPERLINK \l "_Toc6650147" 4.6.1 Operation Controller        PAGEREF _Toc6650147 \h 35
 HYPERLINK \l "_Toc6650148" 4.6.2 Shift Registers Operation   PAGEREF _Toc6650148 \h 36
 HYPERLINK \l "_Toc6650149" 4.6.3 Output Control Module Operation     PAGEREF _Toc6650149 \h 37
 HYPERLINK \l "_Toc6650150" 4.6.4 Clock Generator Operation   PAGEREF _Toc6650150 \h 37
 HYPERLINK \l "_Toc6650152" Architecture      PAGEREF _Toc6650152 \h 38
 HYPERLINK \l "_Toc6650153" 5.1 Host Interface        PAGEREF _Toc6650153 \h 40
 HYPERLINK \l "_Toc6650154" 5.2 TX Ethernet MAC       PAGEREF _Toc6650154 \h 40
 HYPERLINK \l "_Toc6650155" 5.3 RX Ethernet MAC       PAGEREF _Toc6650155 \h 40
 HYPERLINK \l "_Toc6650156" 5.4 MAC Control Module    PAGEREF _Toc6650156 \h 40
 HYPERLINK \l "_Toc6650157" 5.4.1 Control Frame Detector      PAGEREF _Toc6650157 \h 41
 HYPERLINK \l "_Toc6650158" 5.4.2 Control Frame Generator     PAGEREF _Toc6650158 \h 41
 HYPERLINK \l "_Toc6650159" 5.4.3 TX/RX Ethernet MAC Interface        PAGEREF _Toc6650159 \h 41
 HYPERLINK \l "_Toc6650160" 5.4.4 PAUSE Timer         PAGEREF _Toc6650160 \h 41
 HYPERLINK \l "_Toc6650161" 5.4.5 Slot Timer  PAGEREF _Toc6650161 \h 41
 HYPERLINK \l "_Toc6650162" 5.5 MII Management Module         PAGEREF _Toc6650162 \h 42
 HYPERLINK \l "_Toc6650163" 5.5.1 Operation Control Module    PAGEREF _Toc6650163 \h 42
 HYPERLINK \l "_Toc6650164" 5.5.2 Output Control Module       PAGEREF _Toc6650164 \h 42
 HYPERLINK \l "_Toc6650165" 5.5.3 Shift Register      PAGEREF _Toc6650165 \h 42
 HYPERLINK \l "_Toc6650166" 5.5.4 Clock Generator     PAGEREF _Toc6650166 \h 42

List of Tables
 TOC \h \z \t "Caption,1"  HYPERLINK \l "_Toc4153344" Table 1: Host Interface Ports (common ports)        PAGEREF _Toc4153344 \h 3
 HYPERLINK \l "_Toc4153345" Table 2: Host Interface Ports (internal DMA used)  PAGEREF _Toc4153345 \h 4
 HYPERLINK \l "_Toc4153346" Table 3: Host Interface Ports (external DMA is used)       PAGEREF _Toc4153346 \h 5
 HYPERLINK \l "_Toc4153347" Table 4: PHY Interface Ports       PAGEREF _Toc4153347 \h 7
 HYPERLINK \l "_Toc4153348" Table 5: Register List     PAGEREF _Toc4153348 \h 9
 HYPERLINK \l "_Toc4153349" Table 6: MODER Register    PAGEREF _Toc4153349 \h 11
 HYPERLINK \l "_Toc4153350" Table 7: INT_SOURCE Register      PAGEREF _Toc4153350 \h 11
 HYPERLINK \l "_Toc4153351" Table 8: INT_MASK Register        PAGEREF _Toc4153351 \h 12
 HYPERLINK \l "_Toc4153352" Table 9: IPGT Register    PAGEREF _Toc4153352 \h 13
 HYPERLINK \l "_Toc4153353" Table 10: IPGR1 Register  PAGEREF _Toc4153353 \h 13
 HYPERLINK \l "_Toc4153354" Table 11: IPGR2 Register  PAGEREF _Toc4153354 \h 14
 HYPERLINK \l "_Toc4153355" Table 12: PACKETLEN Register      PAGEREF _Toc4153355 \h 14
 HYPERLINK \l "_Toc4153356" Table 13: COLLCONF Register       PAGEREF _Toc4153356 \h 15
 HYPERLINK \l "_Toc4153357" Table 14: TX_BD_NUM Register      PAGEREF _Toc4153357 \h 15
 HYPERLINK \l "_Toc4153358" Table 15: CTRLMODER Register      PAGEREF _Toc4153358 \h 16
 HYPERLINK \l "_Toc4153359" Table 16: MIIMODER Register       PAGEREF _Toc4153359 \h 16
 HYPERLINK \l "_Toc4153360" Table 17: MIICOMMAND Register     PAGEREF _Toc4153360 \h 17
 HYPERLINK \l "_Toc4153361" Table 18: MIIADDRESS Register     PAGEREF _Toc4153361 \h 17
 HYPERLINK \l "_Toc4153362" Table 19: MIITX_DATA Register     PAGEREF _Toc4153362 \h 18
 HYPERLINK \l "_Toc4153363" Table 20: MIIRX_DATA Register     PAGEREF _Toc4153363 \h 18
 HYPERLINK \l "_Toc4153364" Table 21: MIISTATUS Register      PAGEREF _Toc4153364 \h 18
 HYPERLINK \l "_Toc4153365" Table 22: MAC_ADDR0 Register      PAGEREF _Toc4153365 \h 19
 HYPERLINK \l "_Toc4153366" Table 23: MAC_ADDR1 Register      PAGEREF _Toc4153366 \h 19
 HYPERLINK \l "_Toc4153367" Table 24: HASH0 Register  PAGEREF _Toc4153367 \h 20
 HYPERLINK \l "_Toc4153368" Table 25: HASH1 Register  PAGEREF _Toc4153368 \h 20
 HYPERLINK \l "_Toc4153369" Table 26: Tx Buffer Descriptor    PAGEREF _Toc4153369 \h 25
 HYPERLINK \l "_Toc4153370" Table 27: Tx Buffer pointer when internal DMA is used     PAGEREF _Toc4153370 \h 25
 HYPERLINK \l "_Toc4153371" Table 28: Rx Buffer Descriptor    PAGEREF _Toc4153371 \h 27
 HYPERLINK \l "_Toc4153372" Table 29: Rx Buffer pointer when internal DMA is used     PAGEREF _Toc4153372 \h 27

List of Figures
 TOC \h \z \t "Caption 1,1"  HYPERLINK \l "_Toc4750722" Figure 1: Tx Buffer Descriptor   PAGEREF _Toc4750722 \h 23
 HYPERLINK \l "_Toc4750723" Figure 2: Rx Buffer Descriptor    PAGEREF _Toc4750723 \h 25
 HYPERLINK \l "_Toc4750724" Figure 3: Structure of the PAUSE control frame    PAGEREF _Toc4750724 \h 32
 HYPERLINK \l "_Toc4750725" Figure 4: Architecture Overview   PAGEREF _Toc4750725 \h 39


Introduction
The Ethernet IP Core consists of five modules:
The MAC (Media Access Control) module, formed by transmit, receive, and control module
The MII (Media Independent Interface) Management module
The Host Interface
The Ethernet IP Core is capable of operating at 10 or 100 Mbps for Ethernet and Fast Ethernet applications. An external PHY is needed for the complete Ethernet solution.

IO Ports
2.1 Ethernet Core IO ports
The Ethernet IP Core uses three types of signals to connect to media: 
WISHBONE signals to connect to the Host Interface.
Common signals
Signals when the Internal DMA is used 
Signals when the External DMA is used
MII Management signals to connect to the PHY
Reset signals (for resetting different parts of the Ethernet IP Core
When internal or external DMA is used, different signals are used for the Host Interface.

2.1.1 Host Interface Ports (common ports)
The table below contains the common ports connecting the Ethernet IP Core to the Host Interface. The Host Interface is WISHBONE Rev. B compliant. 



All signals listed below are active HIGH, unless otherwise noted. Signal direction is with respect to the Ethernet IP Core. 

PortWidthDirectionDescriptionCLK_I1IClock InputRST_I1IReset InputADDR_I32IAddress InputDATA_I32IData InputDATA_O32OData OutputSEL_I4ISelect Input Array
Indicates which bytes are valid on the data bus. Whenever this signal is not 1111b during a valid access, the ERR_O is asserted.WE_I1IWrite Input
Indicates a Write Cycle when asserted high or a Read Cycle when asserted low. STB_I1IStrobe Input
Indicates the beginning of a valid transfer cycle.CYC_I1ICycle Input
Indicates that a valid bus cycle is in progress.ACK_O1OAcknowledgment Output
Indicates a normal Cycle termination.ERR_O1OError Acknowledgment Output
Indicates an abnormal cycle termination.INTA_O1OInterrupt Output A. Table  SEQ Table \* ARABIC 1: Host Interface Ports (common ports)

2.1.2 Host Interface Ports (internal DMA ports)
The table below contains the ports connecting the Ethernet IP Core to the Host Interface when the internal DMA is selected. The Host Interface is WISHBONE Rev. B compliant. 



All signals listed below are active HIGH, unless otherwise noted. Signal direction is with respect to the Ethernet IP Core. 

PortWidthDirectionDescriptionM_ADDR_O32OAddress OutputM_DATA_I32IData InputM_DATA_O32OData OutputM_SEL_O4ISelect Output Array
Indicates which bytes are valid on the data bus. Whenever this signal is not 1111b during a valid access, the ERR_I is asserted.M_WE_O1OWrite Output
Indicates a Write Cycle when asserted high or a Read Cycle when asserted low. M_STB_O1OStrobe Output
Indicates the beginning of a valid transfer cycle.M_CYC_O1OCycle Output
Indicates that a valid bus cycle is in progress.M_ACK_I1IAcknowledgment Input
Indicates a normal cycle termination.M_ERR_I1IError Acknowledgment Input
Indicates an abnormal cycle termination.Table  SEQ Table \* ARABIC 2: Host Interface Ports (internal DMA used)

2.1.3 Host Interface ports (external DMA ports)
The below table contains the ports connecting the Ethernet IP Core to the Host Interface when external DMA is used. The host interface is WISHBONE Rev. B compliant. 



All signals listed below are active HIGH, unless otherwise noted. Signal direction is with respect to the Ethernet IP Core. 

PortWidthDirectionDescriptionREQ0_O1OExternal DMA request to channel 0REQ1_O1OExternal DMA request to channel 1ACK0_I1IExternal DMA acknowledgment channel 0ACK1_I1IExternal DMA acknowledgment channel 1ND0_O1OForce Next Descriptor advancing for channel 0ND1_O1OForce Next Descriptor advancing for channel 1RD0_O1ORestart Descriptor for channel 0Table  SEQ Table \* ARABIC 3: Host Interface Ports (external DMA is used)

2.1.4 PHY Interface ports
The table below contains the ports connecting the Ethernet IP Core to the PHY Interface. All signals listed below are active HIGH, unless otherwise noted. Signal direction is with respect to the Ethernet IP Core. 

PortWidthDirectionDescriptionMTxClk1ITransmit Nibble or Symbol Clock. The PHY provides the MTxClk signal. It operates at a frequency of 25 MHz (100 Mbps) or 2.5 MHz (10 Mbps). The clock is used as a timing reference for the transfer of MTxD[3:0], MtxEn, and MTxErr. MTxD[3:0]4OTransmit Data Nibble. Signals are the transmit data nibbles. They are synchronized to the rising edge of MTxClk. When MTxEn is asserted, PHY accepts the MTxD. MTxEn1OTransmit Enable. When asserted, this signal indicates to the PHY that the data MTxD[3:0] is valid and the transmission can start. The transmission starts with the first nibble of the preamble. The signal remains asserted until all nibbles to be transmitted are presented to the PHY. It is deasserted prior to the first MTxClk, following the final nibble of a frame. MTxErr1OTransmit Coding Error. When asserted for one MTxClk clock period while MTxEn is also asserted, this signal causes the PHY to transmit one or more symbols that are not part of the valid data or delimiter set somewhere in the frame being transmitted to indicate that there has been a transmit coding error. MRxClk1IReceive Nibble or Symbol Clock. The PHY provides the MRxClk signal. It operates at a frequency of 25 MHz (100 Mbps) or 2.5 MHz (10 Mbps). The clock is used as a timing reference for the reception of MRxD[3:0], MRxDV, and MRxErr. MRxDV1IReceive Data Valid. The PHY asserts this signal to indicate to the Rx MAC that it is presenting the valid nibbles on the MRxD[3:0] signals. The signal is asserted synchronously to the MRxClk. MRxDV is asserted from the first recovered nibble of the frame to the final recovered nibble. It is then deasserted prior to the first MRxClk that follows the final nibble. MRxD
[3:0]4IReceive Data Nibble. These signals are the receive data nibble. They are synchronized to the rising edge of MRxClk. When MRxDV is asserted, the PHY sends a data nibble to the Rx MAC. For a correctly interpreted frame, seven bytes of a preamble and a completely formed SFD must be passed across the interface. MRxErr1IReceive Error. The PHY asserts this signal to indicate to the Rx MAC that a media error was detected during the transmission of the current frame. MRxErr is synchronous to the MRxClk and is asserted for one or more MRxClk clock periods and then deasserted. MColl1ICollision Detected. The PHY asynchronously asserts the collision signal MColl after the collision has been detected on the media. When deasserted, no collision is detected on the media.MCrS1ICarrier Sense. The PHY asynchronously asserts the carrier sense MCrS signal after the medium is detected in a non-idle state. When deasserted, this signal indicates that the media is in an idle state (and the transmission can start).MDC1OManagement Data Clock. This is a clock for the MDIO serial data channel. MDIO1I/OManagement Data Input/Output. Bi-directional serial data channel for PHY/STA communication. Table  SEQ Table \* ARABIC 4: PHY Interface Ports

2.1.5 Reset Signals
You may reset the MAC sub-modules using one or more separate signals. To reset the PHY, assert its RESET signal either through the boars system control register or by writing an appropriate bit in the PHY register.

Registers
This section describes all base, control, and status registers inside the Ethernet IP Core. The Address field indicates a relative address in hexadecimal. Width specifies the number of bits in the register, and Access specifies the valid access types to that register. RW stands for read and write access, RO for read-only access. A C appended to RW or RO indicates that some or all of the bits are cleared after a read. 

NameAddressWidthAccessDescriptionMODER0x0032RWMode RegisterINT_SOURCE0x0432RWInterrupt Source RegisterINT_MASK0x0832RWInterrupt Mask RegisterIPGT0x0C32RWBack to Back Inter Packet Gap RegisterIPGR10x1032RWNon Back to Back Inter Packet Gap Register 1IPGR20x1432RWNon Back to Back Inter Packet Gap Register 2PACKETLEN0x1832RWPacket Length (minimum and maximum) RegisterCOLLCONF0x1C32RWCollision and Retry ConfigurationRX_BD_NUM0x208RWReceive Buffer Descriptor NumberCTRLMODER0x2432RWControl Module Mode RegisterMIIMODER0x2832RWMII Mode RegisterMIICOMMAND0x2C32RWMII Commend RegisterMIIADDRESS0x3032RWMII Address Register
Contains the PHY address and the register within the PHY addressMIITX_DATA0x3432RWMII Transmit Data
The data to be transmitted to the PHYMIIRX_DATA0x3832RWMII Receive Data
The data received from the PHYMIISTATUS0x3C32RWMII Status RegisterMAC_ADDR00x4032RWMAC Individual Address0
The LSB four bytes of the individual address are written to this register.MAC_ADDR10x4432RWMAC Individual Address1
The MSB two bytes of the individual address are written to this register.ETH_HASH0_ADR0x4832RWHASH0 RegisterETH_HASH1_ADR0x4C32RWHASH1 RegisterTable  SEQ Table \* ARABIC 5: Register List

3.1 MODER (Mode Register)
Bit #AccessDescription31-17Reserved16RWRECSMALL  Receive Small Packets
0 = Packets smaller than MINFL are ignored.
1 = Packets smaller than MINFL are accepted.15RWPAD  Padding enabled
0 = Do not add pads to short frames. 
1 = Add pads to short frames (until the minimum frame length is equal to MINFL). 14RWHUGEN  Huge Packets Enable
0 = The maximum frame length is MAXFL. All additional bytes are discarded. 
1 = Frames up 64 KB are transmitted. 13RWCRCEN  CRC Enable
0 = Tx MAC does not append the CRC (passed frames already contain the CRC.
1 = Tx MAC appends the CRC to every frame.12RWDLYCRCEN  Delayed CRC Enabled
0 = Normal operation (CRC calculation starts immediately after the SFD).
1 = CRC calculation starts 4 bytes after the SFD.11RWRST  Reset MAC
0 = Normal operation.
1 = MAC is reset.10RWFULLD  Full Duplex
0 = Half duplex mode. 
1 = Full duplex mode. 9RWEXDFREN  Excess Defer Enabled 
0 = When the excessive deferral limit is reached, a packet is aborted.
1 = MAC waits for the carrier indefinitely.8RWNOBCKOF  No Backoff
0 = Normal operation (a binary exponential backoff algorithm is used).
1 = Tx MAC starts retransmitting immediately after the collision. 7RWLOOPBCK  Loop Back
0 = Normal operation. 
1 = TX is looped back to the RX. 6RWIFG  Interframe Gap for Incoming frames
0 = Normal operation (minimum IFG is required for a frame to be accepted).
1 = All frames are accepted regardless to the IFG.5RWPRO  Promiscuous
0 = Check the destination address of the incoming frames.
1 = Receive the frame regardless of its address.4RWIAM  Individual Address Mode
0 = Normal operation (physical address is checked when the frame is received.
1 = The individual hash table is used to check all individual addresses received.3RWBRO  Broadcast Address
0 = Receive all frames containing the broadcast address.
1 = Reject all frames containing the broadcast address unless the PRO bit = 1.2RWNOPRE  No Preamble
0 = Normal operation (7-byte preamble).
1 = No preamble is sent.1RWTXEN  Transmit Enable
0 = Transmit is disabled.
1 = Transmit is enabled.0RWRXEN  Receive Enable
0 = Receive is disabled.
1 = Receive is enabled.Table  SEQ Table \* ARABIC 6: MODER Register
Reset Value:
   MODER: 0000A800h

3.2 INT_SOURCE (Interrupt Source Register)
Bit #AccessDescription31-7Reserved6RWRXC  Receive Control Frame 
This bit indicates that the control frame was received. It is cleared by writing 1 to it.5RWTXC  Transmit Control Frame 
This bit indicates that a control frame was transmitted. It is cleared by writing 1 to it.4RWBUSY  Busy 
This bit indicates that a buffer was received and discarded due to a lack of buffers. It is cleared by writing 1 to it.3RWRXE - Receive Error
This bit indicates that an error occurred while receiving data. It is cleared by writing 1 to it.2RWRXB - Receive Frame
This bit indicates that a frame was received. It is cleared by writing 1 to it.1RWTXE - Transmit Error
This bit indicates that a buffer was not transmitted due to a transmit error.  It is cleared by writing 1 to it.0RWTXB  Transmit Buffer
This bit indicates that a buffer has been transmitted. It is cleared by writing 1 to it.Table  SEQ Table \* ARABIC 7: INT_SOURCE Register
Reset Value:
 INT_SOURCE: 00000000h

3.3 INT_MASK (Interrupt Mask Register)
Bit #AccessDescription31-7Reserved6RWRXC_M  Receive Control Frame Mask
0 = Event masked
1 = Event causes an interrupt5RWTXC_M  Transmit Control Frame Mask
0 = Event masked
1 = Event causes an interrupt4RWBUSY_M  Busy Mask
0 = Event masked
1 = Event causes an interrupt3RWRXE_M  Receive Error Mask
0 = Event masked
1 = Event causes an interrupt2RWRXF_M  Receive Frame Mask
0 = Event masked
1 = Event causes an interrupt1RWTXE_M  Transmit Error Mask
0 = Event masked
1 = Event causes an interrupt0RWTXB_M  Transmit Buffer Mask
0 = Event masked
1 = Event causes an interruptTable  SEQ Table \* ARABIC 8: INT_MASK Register
Reset Value:
    INT_MASK: 00000000h

3.4 IPGT (Back to Back Inter Packet Gap Register)
Bit #AccessDescription31-7Reserved6-0RWIPGT  Back to Back Inter Packet Gap
Full Duplex: The recommended value is 0x15, which equals 0.96 (s IPG (100 Mbps) or 9.6 (s (10 Mbps). The desired period in nibble times minus 6 should be written to the register.
Half Duplex: The recommended value and default is 0x12, which equals 0.96 (s IPG (100 Mbps) or 9.6 (s (10 Mbps). The desired period in nibble times minus 3 should be written to the register.Table  SEQ Table \* ARABIC 9: IPGT Register
Reset Value:
    IPGT: 00000012h

3.5 IPGR1 (Non Back to Back Inter Packet Gap Register 1)
Bit #AccessDescription31-7Reserved6-0RWIPGR1  Non Back to Back Inter Packet Gap 1
When a carrier sense appears within the IPGR1 window, Tx MAC defers and the IPGR counter is reset.
When a carrier sense appears later than the IPGR1 window, the IPGR counter continues counting. The recommended and default value for this register is 0xC. It must be within the range [0,IPGR2].Table  SEQ Table \* ARABIC 10: IPGR1 Register
Reset Value:
     IPGR1: 0000000Ch

3.6 IPGR2 (Non Back to Back Inter Packet Gap Register 2)
Bit #AccessDescription31-7Reserved6-0RWIPGR2  Non Back to Back Inter Packet Gap 2
The recommended and default value is 0x12, which equals to 0.96 (s IPG (100 Mbit/s) or 9.6 (s (10 Mbit/s).Table  SEQ Table \* ARABIC 11: IPGR2 Register
Reset Value:
      IPGR2: 00000012h

3.7 PACKETLEN (Packet Length Register)
Bit #AccessDescription31-16RWMINFL  Minimum Frame Length
The minimum Ethernet packet is 64 bytes long. If a reception of smaller frames is needed, assert the RECSMALL bit (in the mode register MODER) or change the value of this register. 
To transmit small packets, assert the PAD bit or the MINFL value (see the PAD bit description in the MODER register). 15-0RWMAXFL  Maximum Frame Length
The maximum Ethernet packet is 1518 bytes long. To support this and to leave some additional space for the tags, a default maximum packet length equals 1536 bytes (0x0600). If there is a need to support bigger packets, you can assert the HUGEN bit or increase the value of the MAXFL field (see the HUGEN bit description in the MODER).Table  SEQ Table \* ARABIC 12: PACKETLEN Register
Reset Value:
  PACKETLEN: 00400600h

3.8 COLLCONF (Collision and Retry Configuration Register)
Bit #AccessDescription31-20Reserved19-16RWMAXRET  Maximum Retry
This field specifies the maximum number of consequential retransmission attempts after the collision is detected. When the maximum number has been reached, the Tx MAC reports an error and stops transmitting the current packet. According to the Ethernet standard, the MAXRET default value is set to 0xf (15).15-6Reserved5-0RWCOLLVALID  Collision Valid
This field specifies a collision time window. A collision that occurs later than the time window is reported as a Late Collisions and transmission of the current packet is aborted. The default value equals 0x3f (by default, a late collision is every collision that occurs 64 bytes (63 + 1) from the preamble). Table  SEQ Table \* ARABIC 13: COLLCONF Register
Reset Value:
  COLLCONF: 000F003fh

3.9 TX_BD_NUM (Transmit BD Number Reg.)
Bit #AccessDescription31:8Reserved9:0RWTransmit Buffer Descriptor (Tx BD) Number
Number of the Tx BD (when external DMA is used) 
or
Number of the Tx BD multiplied by 2 (when internal DMA is used) Table  SEQ Table \* ARABIC 14: TX_BD_NUM Register
Reset Value:
        TX_BD_NUM: 00000080h

3.10 CTRLMODER (Control Module Mode Register)
Bit #AccessDescription31-3Reserved2RWTXFLOW  Transmit Flow Control
0 = PAUSE control frames are blocked.
1 = PAUSE control frames are allowed to be sent.1RWRXFLOW  Receive Flow Control
0 = Received PAUSE control frames are ignored.
1 = The transmit function (Tx MAC) is blocked when a PAUSE control frame is received.0RWPASSALL  Pass All Receive Frames
0 = Control frames are not passed to the host. The MAC Control module is enabled.
1 = All received frames are passed to the host. The MAC Control module is disabled.Table  SEQ Table \* ARABIC 15: CTRLMODER Register
Reset Value:
     CTRLMODER: 00000000h

3.11 MIIMODER (MII Mode Register) 
Bit #AccessDescription31-11Reserved10RWMIIMRST  Reset of the MIIM module9Reserved8RWMIINOPRE  No Preamble
0 = 32-bit preamble sent
1 = No preamble send7-0RWCLKDIV  Clock Divider
The field is a host clock divider factor. The host clock can be divided by an even number, greater then 1. The default value is 0x64 (100).Table  SEQ Table \* ARABIC 16: MIIMODER Register
Reset Value:
      MIIMODER: 00000064h

3.12 MIICOMMAND (MII Command Register)
Bit #AccessDescription31-3Reserved2RWWCTRLDATA  Write Control Data1RWRSTAT  Read Status0RWSCANSTAT  Scan StatusTable  SEQ Table \* ARABIC 17: MIICOMMAND Register
Reset Value:
   MIICOMMAND: 00000000h

3.13 MIIADDRESS (MII Address Register)
Bit #AccessDescription31-13Reserved12-8RWRGAD  Register Address (within the PHY selected by the FIAD[4:0])7-5Reserved4-0RWFIAD  PHY AddressTable  SEQ Table \* ARABIC 18: MIIADDRESS Register
Reset Value:
      MIIADDRESS: 00000000h

3.14 MIITX_DATA (MII Transmit Data)
Bit #AccessDescription31-16Reserved15-0RWCTRLDATA  Control Data (data to be written to the PHY)Table  SEQ Table \* ARABIC 19: MIITX_DATA Register
Reset Value:
      MIITX_DATA: 00000000h

3.15 MIIRX_DATA (MII Receive Data)
Bit #AccessDescription31-16Reserved15-0RWPRSD  Received Data (data read from the PHY)Table  SEQ Table \* ARABIC 20: MIIRX_DATA Register
Reset Value:
 MIIRX_DATA: 00000000h

3.16 MIISTATUS (MII Status Register)
Bit #AccessDescription31-3Reserved2RNVALID  Invalid
0 = The data in the MSTATUS register is valid.
1 = The data in the MSTATUS register is invalid.1RBUSY
0 = The MII is ready.
1 = The MII is busy (operation in progress).0RCLINKFAIL:
0 = The link is OK.
1 = The link failed.
The Link fail condition occurred (now the link might be OK). After a read, this bit is cleared. Another status read gets a new status.Table  SEQ Table \* ARABIC 21: MIISTATUS Register
Reset Value:
     MIISTATUS: 00000000h

3.17 MAC_ADDR0 (MAC Address Register 0)
Bit #AccessDescription31-24RWByte 2 of the Ethernet MAC address (individual address)23-16RWByte 3 of the Ethernet MAC address (individual address)15-8RWByte 4 of the Ethernet MAC address (individual address)7-0RWByte 5 of the Ethernet MAC address (individual address)Table  SEQ Table \* ARABIC 22: MAC_ADDR0 Register
Reset Value:
 MAC_ADDR0: 00000000h

Note: When an address is transmitted, byte 0 is sent first and byte 5 last.

3.18 MAC_ADDR1 (MAC Address Register 1)
Bit #AccessDescription31-16Reserved15-8RWByte 0 of the Ethernet MAC address (individual address)7-0RWByte 1 of the Ethernet MAC address (individual address)Table  SEQ Table \* ARABIC 23: MAC_ADDR1 Register
Reset Value:
       MAC_ADDR1: 00000000h

Note: When an address is transmitted, byte 0 is sent first and byte 5 last.

3.19 HASH0 (HASH Register 0)
Bit #AccessDescription31-0RWHash0 valueTable  SEQ Table \* ARABIC 24: HASH0 Register
Reset Value: 
  HASH0: 00000000h

3.20 HASH1 (HASH Register 1)
Bit #AccessDescription31-0RWHash1 valueTable  SEQ Table \* ARABIC 25: HASH1 Register
Reset Value:
    HASH1: 00000000h


Operation
This section describes the Ethernet IP Core operation. 
The core consists of five modules: 
The host interface connects the Ethernet Core to the rest of the system via the WISHBONE (using DMA transfers). Registers are also part of the host interface. 
The TX Ethernet MAC performs transmit functions.
The RX Ethernet MAC performs receive functions.
The MAC Control Module performs full duplex flow control functions.
The MII Management Module performs PHY control and gathers the status information from it.
All modules combined deliver full-function 10/100 Mbps Media Access Control. The Ethernet IP Core can operate in half- or full-duplex mode and is based on the CSMA/CD (Carrier Sense Multiple Access / Collision Detection) protocol.. 
When a station wants to transmit in half-duplex mode, it must observe the activity on the media (Carrier Sense). As soon as the media is idle (no transmission), any station can start transmitting (Multiple Access). If two or more stations are transmitting at the same time, a collision on the media is detected. All stations stop transmitting and back off for some random time. After the back-off time, the station checks the activity on the media again. If the media is idle, it starts transmitting. All other stations wait for the current transmission to end. 
In full-duplex mode, the Carrier Sense and the Collision Detect signals are ignored. The MAC Control module takes care of sending and receiving the PAUSE control frame to achieve Flow control (see the TXFLOW and RXFLOW bit description in the CTRLMODER register for more information). 
The MII Management module provides a media independent interface (MII) to the external PHY. This way, the configuration and status registers of the PHY can be read from/written to. 

4.1 Host Interface Operation
The host interface connects the Ethernet IP Core to the rest of the system (RISC, memory) via the WISHBONE bus. The WISHBONE serves to access the configuration registers and the memory. Currently, only DMA transfers are supported for transferring the data from/to the memory. 

4.1.1 Configuration Registers
The function of the configuration registers is transparent and can be easily understood by reading the Registers section (Chapter  REF _Ref4387033 \r \h 3). 

4.1.2 External/Internal DMA Operation
The Ethernet MAC can use an external or internal DMA engine:
An External DMA core is needed. This mode is not recommended because it will soon be obsolete.
The Ethernet IP core uses Internal DMA resources. 
The selection between external and internal DMA is made in the eth_defines.v file. 

4.1.3 Buffer Descriptors (BD)
The transmission and the reception processes are based on the descriptors. The Transmit Descriptors (TxD) are used for transmission while the Receive Descriptors (RxD) are used for reception. 
When using an internal DMA, the buffer descriptors are 64 bits long. The first 32 bits are reserved for length and status while the last 32 bits contain the pointer to the associated buffer (where data is stored). The Ethernet MAC core has an internal RAM that can store up to 128 BDs (for both Rx and Tx).
When using external DMA, buffer descriptors are 32 bits long. Status and length information is stored to these 32 bits. Pointers to the associated buffers are stored in the external DMA core (additional descriptors that are part of the DMA). The Ethernet MAC core has an internal RAM that can store up to 256 descriptors (for both Rx and Tx).
The first 32 bits are the same for both, internal and external DMA operation. The difference lies in the buffer pointer (read the above section).
The internal memory saves all descriptors at addresses from 0x400 to 0x800 (128 64bit descriptors when the internal DMA is used or 256 32bit descriptors when the external DMA is used). The transmit descriptors are located between the start address (0x400) and the address that equals the value written in the TX_BD_NUM register (page  PAGEREF _Ref532008757 \h 15) multiplied by 4. This register holds the number of the Tx buffer descriptors used multiplied by 2. The receive descriptors are located between the start address (0x400), plus the address number written in the TX_BD_NUM multiplied by 4, and the descriptor end address (0x800). 
The transmit and receive status of the packet is written to the associated buffer descriptor once its transmission/reception is finished. 

4.1.3.1 Tx Buffer Descriptors
The transmit descriptors contain information about associated buffers (length, status). When the internal DMA is selected, they also contain pointers to the buffers holding the relevant data.

ADDR = Offset + 0
31302928272625242322212019181716LEN1514131211109876543210RDIRQWRPADCRCReservedURRTRY[3:0]RLLCDFCS
ADDR = Offset + 4
31302928272625242322212019181716TXPNT1514131211109876543210TXPNTFigure  SEQ Figure \* ARABIC 1: Tx Buffer Descriptor

Bit #AccessDescription31-16RWLEN  Length
Number of bytes associated with the BD to be transmitted. 15RWRD  Tx BD Ready
0 = The buffer associated with this buffer descriptor is not ready, and you are free to manipulate it. After the data from the associated buffer has been transmitted or after an error condition occurred, this bit is cleared to 0. 
1 = The data buffer is ready for transmission or is currently being transmitted. You are not allowed to manipulate this descriptor once this bit is set. 14RWIRQ  Interrupt Request Enable
0 = No interrupt is generated after the transmission. 
1 = When data associated with this buffer descriptor is sent, a TXB or TXE interrupt will be asserted (see  REF _Ref532014672 \h  \* MERGEFORMAT 3.2 INT_SOURCE (Interrupt Source Register) for more details). 13RWWR  Wrap
0 = This buffer descriptor is not the last descriptor in the buffer descriptor table. 
1 = This buffer descriptor is the last descriptor in the buffer descriptor table. After this buffer descriptor was used, the first buffer descriptor in the table will be used again. 12RWPAD  Pad Enable
0 = No pads will be add at the end of short packets. 
1 = Pads will be added to the end of short packets. 11RWCRC  CRC Enable
0 = CRC wont be added at the end of the packet.
1 = CRC will be added at the end of the packet.10:9Reserved8RWUR  Underrun 
Underrun occurred while sending this buffer.7:4RWRTRY  Retry Count 
This bit indicates the number of retries before the frame was successfully sent. 3RWRL  Retransmission Limit 
This bit is set when the transmitter fails. (Retry Limit + 1) attempts to successfully transmit a message due to repeated collisions on the medium. The Retry Limit is set in the COLLCONF register on page  PAGEREF _Ref1709320 \h 15. 2RWLC  Late Collision
Late collision occurred while sending this buffer. The transmission is stopped and this bit is written. Late collision is defined in the COLLCONF register on page  PAGEREF _Ref1709320 \h 15.1RWDF  Defer Indication
The frame was deferred before being sent successfully, i.e. the transmitter had to wait for Carrier Sense before sending because the line was busy. This is not a collision indication. Collisions are indicated in RTRY. 0RWCS  Carrier Sense Lost
This bit is set when Carrier Sense is lost during a frame transmission. The Ethernet controller writes CS after it finishes sending the buffer.Table  SEQ Table \* ARABIC 26: Tx Buffer Descriptor

Bit #AccessDescription31-0RWTXPNT  Transmit Pointer
This is the buffer pointer when the associated frame is stored. Table  SEQ Table \* ARABIC 27: Tx Buffer Pointer When Internal DMA is Used

4.1.3.2 Rx Buffer Descriptors
The receive BDs contain information about the received frames (length, status). When the internal DMA is selected, they also contain pointers to the buffers holding the relevant data.

ADDR = Offset + 0
31302928272625242322212019181716LEN1514131211109876543210EIRQWRReservedMORISDNTLSFCRCLC
ADDR = Offset + 4
31302928272625242322212019181716RXPNT1514131211109876543210RXPNTFigure  SEQ Figure \* ARABIC 2: Rx Buffer Descriptor

Bit #AccessDescription31-16RWLEN  Number of the received bytes associated with this BD. 15RWE  Empty
0 = The data buffer associated with this buffer descriptor has been filled with data or has stopped because an error occurred. The core can read or write this BD. As long as this bit is zero, this buffer descriptor wont be used. 
1 = The data buffer is empty (and ready for receiving data) or currently receiving data. 14RWIRQ  Interrupt Request Enable
0 = No interrupt is generated after the reception. 
1 = When data is received (or error occurs), an RXF interrupt will be asserted (See  REF _Ref532014672 \h  \* MERGEFORMAT 3.2 INT_SOURCE (Interrupt Source Register) for more details).13RWWRAP
0 = This buffer descriptor is not the last descriptor in the buffer descriptor table. 
1 = This buffer descriptor is the last descriptor in the buffer descriptor table. After this buffer descriptor is used, the first Rx buffer descriptor in the table will be used again. 12:8Reserved.7RWM  Miss
0 = The frame is received because of an address recognition hit.
1 = The frame is received because of promiscuous mode.
The Ethernet controller sets M for frames that are accepted in promiscuous mode but are tagged as a miss by internal address recognition. Thus, in promiscuous mode, M determines whether a frame is destined for this station.6RWOR  Overrun
This bit is set when a receiver overrun occurs during frame reception.5RWIS  Invalid Symbol
This bit is set when the reception of an invalid symbol is detected by the PHY.4RWDN  Dribble Nibble
This bit is set when a received frame cannot de divided by 8 (one extra nibble has been received).3RWTL  Too Long
This bit is set when a received frame is too long (bigger than the value set in the PACKETLEN register (page  PAGEREF _Ref1714173 \h 14). 2RWSF  Short Frame
This bit is set when a frame that is smaller than the minimum length is received (minimum length is set in the PACKETLEN register (page  PAGEREF _Ref1714173 \h 14)).1RWCRC  Rx CRC Error
This bit is set when a received frame contains a CRC error.0RWLC  Late Collision
This bit is set when a late collision occurred while receiving a frame.Table  SEQ Table \* ARABIC 28: Rx Buffer Descriptor

Bit #AccessDescription31-0RWRXPNT  Receive Pointer
This is the pointer to the buffer storing the associated frame. Table  SEQ Table \* ARABIC 29: Rx Buffer pointer when internal DMA is used

4.1.4 Frame Transmission
There are a few differences in the frame transmission regarding the use of external or internal DMA.

4.1.4.1 Frame Transmission with Internal DMA
To transmit the first frame, the RISC must do several things, namely:
Store the frame to the memory. 
Associate the Tx BD in the Ethernet MAC core with the packet written to the memory (length, pad, crc, etc.). See section  REF _Ref1717891 \h  \* MERGEFORMAT 4.1.3 Buffer Descriptors (BD) for more information.
Enable the TX part of the Ethernet Core by setting the TXEN bit to 1. 
As soon as the Ethernet IP Core is enabled, it continuously reads the first BD. Immediately when the descriptor is marked as ready, the core reads the pointer to the memory storing the associated data and starts then reading data to the internal FIFO. At the moment the FIFO is full, transmission begins. 
At the end of the transmission, the transmit status is written to the buffer descriptor and an interrupt might be generated (when enabled). Next, two events might occur (according to the WR bit (wrap) in the descriptor):
If the WR bit has not been set, the BD address is incremented, the next descriptor is loaded, and the process starts all over again (if next BD is marked as ready). 
If the WR bit has been set, the first BD address (base) is loaded again. As soon as the BD is marked as ready, transmission will start.

4.1.4.1 Frame Transmission with External DMA
To transmit the first frame, the RISC must do several things, namely:
Store the frame to the memory 
Associate the first DMA descriptor with the stored frame:
The source address field points to the frame in the memory.
The destination field points to the Ethernet Host Interface.
The next pointer field points to the next descriptor in the memory (this descriptor has not been stored yet).
The total transfer size equals the stored frame size.
The incremented source and destination address fields must be set to zero. You should always use the source and destination address of the descriptor written in the next descriptor field. 
Set the EOL bit to zero, indicating that this descriptor is the last descriptor in the list (and the frame is the last frame).
Set the channel 0 registers (channel 0 is used for transmitting).
Enable the channel by setting the CH_EN bit to 1. The channel is now enabled and will start operating as soon as the REQ0 signal is asserted.
Associate the transmit buffer descriptor in the Ethernet MAC core with the packet written to the memory. Enable the TX part of the Ethernet IP Core by setting the TXEN bit and the DMAEN bit to 1. 
As soon as the Ethernet IP Core is enabled and the transmit descriptor is ready, the Core will assert the DMA request signal (REQ0). Upon noticing the request, the DMA will start transmitting the first word (32-bits) of the pointed frame. The REQ0 will be asserted each time 32 bits of the data are needed. When the last 32 bits are needed, the request for the next descriptor  the ND0 signal  is asserted. The ND0 instructs the DMA to load the next descriptor after the last word has been transmitted. 
At the end of the transmission, the transmit status is written to the buffer descriptor and an interrupt might be generated. Next, two events might occur (according to the EOL bit in the descriptor):
If the EOL bit has not been set, more frames stored in the memory are still waiting to be sent. A new descriptor is loaded, and the whole process starts all over again. The DMA has been set already 
If the EOL bit has been set, the DMA channel stops and clears the CH_EN bit in the channel CSR register. To start the transmission, restore the settings required for the beginning of the first packet transmission. 

4.1.5 Frame Reception
There are a few differences in the frame reception regarding the use of external or internal DMA.

4.1.5.1 Frame Reception when Internal DMA is used
To receive the first frame, the RISC must do several things, namely:
Set the receive buffer descriptor to be associated with the received packet and mark it as empty.
Enable the Ethernet receive function by setting the RECEN bit to 1. 
The Ethernet IP Core reads the Rx BD. If it is marked as empty, it starts receiving frames. The Ethernet receive function receives an incoming frame nibble per nibble. After the whole frame has been received and stored to the memory, the receive status and the pointer to the memory storing the data are written to the BD. An interrupt might be generated (if enabled). Then the BD address is incremented and the next BD loaded. If the new BD is marked as empty, another frame can be received; otherwise the operation stops.

4.1.5.2 Frame Reception with External DMA
When the RISC wants to receive the first frame, it must do several things, namely:
Set the descriptors to be used with the DMA channel 1 to appropriate values (to store the incoming data). 
Set and enable channel 1 to use the descriptors.
Set the receive buffer descriptor to be associated with the received packet.
Enable the Ethernet receive function by setting the RECEN and DMAEN bits to 1. 
The Ethernet receive function receives an incoming frame nibble per nibble. After it has received a whole word, it is written to the memory via the WISHBONE by asserting the REQ1 signal (requesting the DMA write to the memory on channel 1). After the whole frame has been received, the ND1 signal is asserted to force usage of the next descriptor with the next frame. The receive status is written to the receive buffer descriptor. 

4.2. DMA Operation
The DMA operation allows for completely transparent data movement between the Ethernet IP Core and the function attached to the WISHBONE bus. Once set up, no function micro controller intervention is needed for normal operations. The Ethernet IP Core has two associated pairs of REQn and ACKn signals. 
When the DMAEN bit in the MODER register is set, the Ethernet IP Core will use the DMA_REQ and DMA_ACK signals for the DMA flow control. The DMA_REQ signal is asserted when data is in the buffer (receiving frames) or when the buffer is empty and needs to be filled (transmitting frames). The DMA must reply with a DMA_ACK for each word (4 bytes) transferred. The buffer holds one MAX_PL_SZ packet (one word). Depending on the DMA and external bus latency, it might be set up to hold more than that. In this case, additional action needs to be performed in the core (but is not yet supported).
More information about Ethernet-DMA functionality can be found in the section  REF _Ref4152520 \h 4.1.2 External/Internal DMA Operation. 
For more general information about the DMA and descriptors, read the WISHBONE DMA/Bridge Core Specification available at www.opencores.org/projects/wb_dma/.

4.3 TX Ethernet MAC
The TX Ethernet MAC generates 10BASE-T/100BASE-TX transmit MII nibble data streams in response to the byte streams the transmit logic (host) supplies. It performs the required deferral and back-off algorithms, takes care of the inter-packet gap (IPG), computes the checksum (FCS), and monitors the physical media (by monitoring Carrier Sense and collision signals). The TX Ethernet MAC is divided into several modules that provide the following functionality:
Generation of the signals connected to the Ethernet PHY during the transmission process
Generation of the status signals the host uses to track the transmission process
Random time generation used in the back-off process after a collision has been detected
CRC generation and checking
Pad generation
Data nibble generation

4.4 RX Ethernet MAC
The RX Ethernet MAC transmits the data streams to the host in response to the 10BASE-T or 100BASE-TX received MII nibbles. The module is divided into several sub-modules providing the following functionality: 
Preamble removal
Data assembly (from input nibble to output byte)
CRC checking for all incoming packets 
Generation of the signal that can be used for address recognition (in the hash table)
Generation of the status signals the host uses to track the reception process 

4.5 MAC Control Module
The MAC Control Module performs a real-time flow control function for the full-duplex operation. The control opcode PAUSE is used for stopping the station transmitting the packets. The receive buffer (FIFO) starts filling up when the upper layer cannot continue accepting the incoming packets. Before an overflow happens, the upper layer sends a PAUSE control frame to the transmitting station. This control frame inhibits the transmission of the data frames for a specified period of time. 
When the MAC Control module receives a PAUSE control frame, it loads the pause timer with the received value into the pause timer value field. The Tx MAC is stopped (paused) from transmitting the data frames for the pause timer value slot times. The pause timer decrements by one each time a slot time passes by. When the pause time number equals zero, the MAC transmitter resumes the transmit operation. 
The MAC Control Module has the following functionality:
Control frame detection 
Control frame generation 
TX/RX MAC Interface 
PAUSE Timer
Slot Timer

4.5.1 Control Frame Detection 
The incoming data packets are passed from the receiver via the MAC Control Module to the upper layers while the control frames are usually dropped. The PASSALL bit in the CTRLMODER register defines whether the control frames are passed or dropped. 
A valid PAUSE control frame has the frame structure described in  REF _Ref4736169 \h Figure 3Figure 3:

Figure  SEQ Figure \* ARABIC 3: Structure of the PAUSE control frame

The destination address must be a reserved multicast address (01-80-c2-00-00-01) or a destination address equal to the Ethernet IP Core MAC address. The Length/Type field must be equal to 8808 and the opcode to 0001 for a PAUSE control frame. 
When the receive flow control and the MAC Control Module are enabled (RXFLOW asserted and PASSALL deasserted), a PAUSE Timer Value from the PAUSE control frame is passed to the PAUSE timer.

4.5.2 Control Frame Generation
When the host wants to send a PAUSE control frame, it asserts the Transmit Pause Request (TPAUSERQ). When a request is detected, the control module waits for the current transmission to end. It then starts transmitting the PAUSE control frame by asserting the Transmit Packet Start Frame (TxStartFrm) and providing the appropriate control data. Sending CtrlFrm is used to instruct the Transmit function (TX Ethernet MAC) to pad and append the FCS. The transmit Pause Frame End (TxEndFrm) is asserted at the end to inform the host that a Pause request was sent. 
Asserting the TXFLOW bit in the MODER register enables the transmission of the PAUSE control frame.  
The TPAUSERQ signal (request) is latched in the MAC Control Generator and reset after the PAUSE control frame has been transmitted. This prevents issuing a new PAUSE request until the current request is sent. The Transmit Pause Timer Value TPAUSETV[15:0] is set prior to the transmit pause request. The TPAUSETV contains the value to be sent as a Pause Timer Value in the pause control frame ( REF _Ref4736169 \h Figure 3Figure 3).

4.5.3 TX/RX MAC Interface
The MAC Control Module is connected between the host and the Tx and Rx modules. When enabled, the its logic takes over the control of the following signals: TxData[7:0], TxStartFrm, TxEndFrm, TxUsedData, TxDone, and TxAbort. These signals are connected directly between the host and the MAC transmit and receive functions when data frames (not control frames) are transmitted or received. 
On the other hand, when a host wants to send a PAUSE control frame, it asserts a TPauseRQ request signal . It is then up to the MAC Control Module to initiate the transmission. In this case, the above signals are not connected to the host any more. The MAC Control Module drives the appropriate control data signals and instructs the Tx module to transmit. 
When a PAUSE control frame is received, the frame can be dropped or passed to the host, depending on the state of the PASSALL signal. Again TxData[7:0], TxStartFrm, TxEndFrm, TxUsedData, TxDone, and TxAbort are not connected directly.

4.5.4 PAUSE Timer
The 16bit PAUSE timer is loaded with a pause timer value when a PAUSE control frame is received. The timer inhibits the data frame transmissions for the timer value time slots. This is done by:  
Preventing the Tx MAC module from seeing the signal TxStartFrm from the host
Preventing the host from seeing the signal TxUsedData from the Tx module
The timer decrements by one each time a time slot passes by. A Slot Timer is used for counting the slot time.  

4.5.5 Slot Timer
The Slot Timer is activated when a PAUSE Timer is preloaded. It counts slot times and generates pulses to the PAUSE Timer for every slot time passed. 

4.6 MII Management Module
The MII Management Module is a simple two-wire interface between the host and an external PHY device. It is used for configuration and status read of the physical device. The physical interface consists of a management data line MDIO (Management Data Input/Output) and a clock line MDC (Management Data Clock). During the read/write operation, the most significant bit is shifted in/out first from/to the MDIO data signal. On each rising edge of the MDC, a Shift register is shifted to the left and a new value appears on the MDIO. 
Internally the interface consists of four signals: 
MDC
MDI
MDO
MDOEN (Management Data Output Enable)
The unidirectional lines MDI, MDO, and MDOEN are combined to make a bi-directional signal MDIO that is connected to the PHY. 
The configuration and status data is written/read to/from the PHY via the MDIO signal. 
The MDC is a low frequency clock derived from dividing the host clock. 
Three commands are supported for controlling the PHY:
Write Control Data (writes the control data to the PHY Configuration registers)
Read Status (reads the PHY Control and Status register)
Scan Status (continuously reads the PHY Status register of one or more PHYs [link fail status]).
The MII Management Module consists of four sub modules:
Operation Controller
Shift Registers
Output Control Module
Clock Generator 

4.6.1 Operation Controller
The Operation Controllers task is to perform all supported commands: Write Control Data, Read Status, and Scan Status. 

4.6.1.1 Write Control Data
A host initiates a write operation by asserting the WCTRLDATA signal. This signal also indicates that the host data CTLD[15:0], the PHY address FIAD[4:0], and the PHY register address RGAD[4:0] are valid. As soon as the host asserts the WCTRLDATA signal, the MIIM module asserts the BUSY signal to inform the host that the write operation is in process. MDOEN is asserted to enable the output line MDO (MDIO) to the PHY. The MIIM module then clocks out the MIIM frame to the PHY on each rising edge of the MDC. The MIIM frame write format conforms to the IEEE 803.2u Specification:
32-bit long preamble (all ones) if the MIINOPRE bit is not asserted
2-bit long Start of frame pattern ST (zero followed by one)
2-bit Operation definition (zero-one for write or one-zero for read)
5-bit PHY address (FIAD[4:0])
5-bit PHY register address RGAD[4:0]
2-bit turnaround field TA (one-zero)
16-bit data
At the end of the write operation, the BUSY signal is deasserted.

4.6.1.2 Read Status
A host initiates a write operation by asserting the RSTAT signal. This signal also indicates that the PHY address FIAD[4:0] and the PHY register address RGAD[4:0] are valid. As soon as the host asserts the RSTAT signal, the MIIM module asserts the BUSY signal to inform the host that the read operation is in process. MDOEN is asserted to enable the output line MDO (MDIO) to the PHY. The MIIM module then clocks out the MIIM frame to the PHY on each rising edge of the MDC and afterwards clocks in the requested data (status). The MIIM read frame format conforms to the IEEE 803.2u Specification:
32-bit long preamble (all ones) if the MIINOPRE bit is not asserted
2-bit long Start of frame pattern ST (zero followed by one)
2-bit Operation definition (zero-one for write or one-zero for read)
5-bit PHY address (FIAD[4:0])
5-bit PHY register address RGAD[4:0]
2-bit turnaround field TA (one-bit period in which the PHY stays in the high-Z state followed by a one-bit period during which the PHY drives a zero on the MDO)
MIIM deasserts the MDOEN signal that enables the MDI (MDIO works as an input) 
PHY sends the data (status) back to the MIIM Module on the data lines PRSD[15:0]
At the end of the read operation, the MIIM deasserts the BUSY signal to indicate to the host that valid data is on the PRSD[15:0] lines. 

4.6.1.3 Scan Status
A host initiates the Scan Status Operation by asserting the SCANSTAT signal. The MIIM performs a continuous read operation of the PHY Status register. The PHY is selected by the FIAD[4:0] signals. The link status LinkFail signal is asserted/deasserted by the MIIM module and reflects the link status bit of the PHY Status register. The signal NVALID is used for qualifying the validity of the LinkFail signals and the status data PRSD[15:0]. These signals are invalid until the first scan status operation ends. 
During the scan status operation, the BUSY signal is asserted until the last read is performed (the scan status operation is stopped). 

4.6.2 Shift Registers Operation
There are two shift registers in the MII Management Module. The Data Shift register is used for:
Shifting out the data to the PHY during the Write Data Control operation
Shifting in the data during the Read Status operation 
Shifting out the FIAD[4:0] and RGAD[4:0] addresses during all operations
The Status Shift register contains the data latched during the last Read Status Operation. Two additional status signals (LinkFail Status and Status Invalid NVALID) are latched separately from the Status Shift register. 
When a Scan Operation is requested, the state of the PRSD[15:0] and a MIILF is constantly updated from the selected PHY register. NVALID is used to qualify the validity of the PRSD[15:0] and MIILS signals. These signals are invalid until the first Scan Status Operation ends.

4.6.3 Output Control Module Operation
The Output Control Module combines the MDI, MDO, and MDOEN signals into a bi-directional MDIO signal that is connected to the external MII PHY. During the Write Control Data Operation, the MDIO operates as an output from the MIIM module. The signal is used for transferring data from the MIIM Module to the PHY. During the Read Status Operation, the MDIO first operates as an output (addressing the PHY and the PHY Internal register) and then as an input to the MIIM Module (reading the status data). In both cases the most significant bit of the data is shifted first. When no operation is performed, the MDIO is tri-stated. 

4.6.4 Clock Generator Operation
The Management Data Clock MDC is a divided host clock. The division factor is set in the MIIMODER register by setting the CLKDIV[7:0] field (MDC depends on the PHY and can be 2.5 MHz or 12.5 MHz.

Architecture
The Ethernet IP Core consists of 5 modules: 
Host Interface and the BD structure
TX Ethernet MAC (transmit function)
RX Ethernet MAC (receive function)
MAC Control Module
MII Management Module
Figure  SEQ Figure \* ARABIC 5: Architecture Overview

5.1 Host Interface
The host interface is connected to the RISC and the memory through the Wishbone. The RISC writes the data for the configuration registers directly while the data frames are written to the memory. Frames are accessed through the DMA. 

5.2 TX Ethernet MAC
The TX Ethernet MAC generates 10BASE-T/100BASE-TX transmit MII nibble data streams in response to the byte streams supplied by the transmit logic (host). It performs the required deferral and back-off algorithms, takes care of the IPG, computes the checksum (FCS) and monitors the physical media (by monitoring Carrier Sense and collision signals). 

5.3 RX Ethernet MAC
The RX Ethernet MAC interprets 10BASE-T/100BASE-TX MII receive data nibble streams and supplies correctly formed packet-byte streams to the host. It searches for the SFD (start frame delimiter) at the beginning of the packet, verifies the FCS, and detects any dribble nibbles or receive code violations.

5.4 MAC Control Module
The function of this module is to implement the full-duplex flow control.
The MAC Control Module consists of three sub-modules that provide the following functionality:
Control frame detection 
Control frame generation 
TX/RX Ethernet MAC Interface 
PAUSE Timer
Slot Timer

5.4.1 Control Frame Detector
The control frame detector checks the incoming frames for the control frames. Control frames can be discarded or passed to the host. When a PAUSE control frame is detected, it can stop the Tx module from transmitting for a certain period of time. 

5.4.2 Control Frame Generator
If the need arises to stop the transmitting station from transmitting (flow control in full-duplex mode), a PAUSE control frame can be sent. 

5.4.3 TX/RX Ethernet MAC Interface
The MAC Control Module is connected between the host interface, the Tx, and the Rx MAC modules. Signals from the host are passed to the Tx MAC in certain occasions and vice versa. 

5.4.4 PAUSE Timer
When a PAUSE control frame is received, the pause timer value is written to the PAUSE timer. This prevents the Tx module from transmitting for a pause timer value period of slot time. 

5.4.5 Slot Timer
The slot timer measures time slots and generate a pulse to the PAUSE timer for every slot time passed by. 

5.5 MII Management Module
The function of the MII Management Module is to control the PHY and to gather information from it (status). 
It consists of four sub modules:
Operation Control Module
Output Control Module
Shift Register
Clock Generator 

5.5.1 Operation Control Module
The function of the Operation Control Module is to perform the following commands:
Write control data 
Read status
Scan status

5.5.2 Output Control Module
The Output Control Module controls the signal appearance on the MDO, MCK, and MDOEN pins.

5.5.3 Shift Register
The shift registers hold the status read from an external PHY.

5.5.4 Clock Generator
The clock generator generates an appropriate output clock MCK according to the input host clock and the clock divider bits (CLKDIV[7:0] in the MIIMODER register). 

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Ethernet IP CoreSpecification


Author: Igor Mohor
IgorM@opencores.org



Rev. 1.13
 DATE \@ "MMMM d, yyyy" \* MERGEFORMAT April 15, 2002














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Revision History
Rev.DateAuthorDescription0.113/03/01Igor MohorFirst Draft0.217/03/01Igor MohorMDC clock divider changed. Instead of the clock select bits CLKS[2:0] the clock divider bits CLKDIV[7:0] are used. 1.021/03/01Igor MohorMII module completed. Revision changed to 1.0 due to cvs demands. 1.116/04/01IMDMA support and buffer descriptors added. 1.224/05/01IMRegisters revised.1.305/06/01IMStatus is written to the status registers. DMA channels 2 and 3 are not used any more. Figures that are implementation specific removed from the document.1.403/07/01IMCOLLCONF register changed bit width. BCKPRESS and BCKPNBEN bit removed from MODER. LOOPBCK added. 1.521/07/01IMSignal RD0_O (Restart Descriptor for channel 0) added. Per packet CRC, BD changed.1.603/12/01IMBD section rewritten. 1.705/12/01IMTX_BD_NUM register used instead of RX_BD_BASE_ADDR register. 1.807/01/02IMMinor typos fixed1.930/01/02IMRST bit in MODER register is 1 after reset, initial collision window changed.1.1018/02/02IMAddress recognition system added. Buffer Descriptors changed. DMA section changed. Ports changed. 1.1102/03/02IMTypos fixed, INT_SOURCE and INT_MASK registers changed. 1.1215/03/02IMTX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description changed. 1.1315/04/02Jeanne WiegelmannDocument revised.
List of Contents
 TOC \o "1-3" \h \z  HYPERLINK \l "_Toc6650098" Introduction      PAGEREF _Toc6650098 \h 1
 HYPERLINK \l "_Toc6650100" IO Ports   PAGEREF _Toc6650100 \h 2
 HYPERLINK \l "_Toc6650101" 2.1 Ethernet Core IO ports         PAGEREF _Toc6650101 \h 2
 HYPERLINK \l "_Toc6650102" 2.1.1 Host Interface Ports (common ports)  PAGEREF _Toc6650102 \h 2
 HYPERLINK \l "_Toc6650103" 2.1.2 Host Interface Ports (internal DMA ports)    PAGEREF _Toc6650103 \h 3
 HYPERLINK \l "_Toc6650104" 2.1.3 Host Interface ports (external DMA ports)    PAGEREF _Toc6650104 \h 4
 HYPERLINK \l "_Toc6650105" 2.1.4 PHY Interface ports  PAGEREF _Toc6650105 \h 5
 HYPERLINK \l "_Toc6650106" 2.1.5 Reset Signals        PAGEREF _Toc6650106 \h 7
 HYPERLINK \l "_Toc6650108" Registers  PAGEREF _Toc6650108 \h 8
 HYPERLINK \l "_Toc6650109" 3.1 MODER (Mode Register)  PAGEREF _Toc6650109 \h 9
 HYPERLINK \l "_Toc6650110" 3.2 INT_SOURCE (Interrupt Source Register)         PAGEREF _Toc6650110 \h 11
 HYPERLINK \l "_Toc6650111" 3.3 INT_MASK (Interrupt Mask Register)    PAGEREF _Toc6650111 \h 12
 HYPERLINK \l "_Toc6650112" 3.4 IPGT (Back to Back Inter Packet Gap Register)         PAGEREF _Toc6650112 \h 13
 HYPERLINK \l "_Toc6650113" 3.5 IPGR1 (Non Back to Back Inter Packet Gap Register 1)  PAGEREF _Toc6650113 \h 13
 HYPERLINK \l "_Toc6650114" 3.6 IPGR2 (Non Back to Back Inter Packet Gap Register 2)  PAGEREF _Toc6650114 \h 14
 HYPERLINK \l "_Toc6650115" 3.7 PACKETLEN (Packet Length Register)    PAGEREF _Toc6650115 \h 14
 HYPERLINK \l "_Toc6650116" 3.8 COLLCONF (Collision and Retry Configuration Register)         PAGEREF _Toc6650116 \h 15
 HYPERLINK \l "_Toc6650117" 3.9 TX_BD_NUM (Transmit BD Number Reg.)   PAGEREF _Toc6650117 \h 15
 HYPERLINK \l "_Toc6650118" 3.10 CTRLMODER (Control Module Mode Register)     PAGEREF _Toc6650118 \h 16
 HYPERLINK \l "_Toc6650119" 3.11 MIIMODER (MII Mode Register)         PAGEREF _Toc6650119 \h 16
 HYPERLINK \l "_Toc6650120" 3.12 MIICOMMAND (MII Command Register)    PAGEREF _Toc6650120 \h 17
 HYPERLINK \l "_Toc6650121" 3.13 MIIADDRESS (MII Address Register)    PAGEREF _Toc6650121 \h 17
 HYPERLINK \l "_Toc6650122" 3.14 MIITX_DATA (MII Transmit Data)       PAGEREF _Toc6650122 \h 17
 HYPERLINK \l "_Toc6650123" 3.15 MIIRX_DATA (MII Receive Data)        PAGEREF _Toc6650123 \h 18
 HYPERLINK \l "_Toc6650124" 3.16 MIISTATUS (MII Status Register)      PAGEREF _Toc6650124 \h 18
 HYPERLINK \l "_Toc6650125" 3.17 MAC_ADDR0 (MAC Address Register 0)   PAGEREF _Toc6650125 \h 19
 HYPERLINK \l "_Toc6650126" 3.18 MAC_ADDR1 (MAC Address Register 1)   PAGEREF _Toc6650126 \h 19
 HYPERLINK \l "_Toc6650127" 3.19 HASH0 (HASH Register 0)      PAGEREF _Toc6650127 \h 20
 HYPERLINK \l "_Toc6650128" 3.20 HASH1 (HASH Register 1)      PAGEREF _Toc6650128 \h 20
 HYPERLINK \l "_Toc6650130" Operation         PAGEREF _Toc6650130 \h 21
 HYPERLINK \l "_Toc6650131" 4.1 Host Interface Operation      PAGEREF _Toc6650131 \h 22
 HYPERLINK \l "_Toc6650132" 4.1.1 Configuration Registers     PAGEREF _Toc6650132 \h 22
 HYPERLINK \l "_Toc6650133" 4.1.2 External/Internal DMA Operation     PAGEREF _Toc6650133 \h 22
 HYPERLINK \l "_Toc6650134" 4.1.3 Buffer Descriptors (BD)     PAGEREF _Toc6650134 \h 22
 HYPERLINK \l "_Toc6650135" 4.1.4 Frame Transmission  PAGEREF _Toc6650135 \h 27
 HYPERLINK \l "_Toc6650136" 4.1.5 Frame Reception     PAGEREF _Toc6650136 \h 29
 HYPERLINK \l "_Toc6650137" 4.2. DMA Operation        PAGEREF _Toc6650137 \h 30
 HYPERLINK \l "_Toc6650138" 4.3 TX Ethernet MAC       PAGEREF _Toc6650138 \h 30
 HYPERLINK \l "_Toc6650139" 4.4 RX Ethernet MAC       PAGEREF _Toc6650139 \h 31
 HYPERLINK \l "_Toc6650140" 4.5 MAC Control Module    PAGEREF _Toc6650140 \h 31
 HYPERLINK \l "_Toc6650141" 4.5.1 Control Frame Detection     PAGEREF _Toc6650141 \h 32
 HYPERLINK \l "_Toc6650142" 4.5.2 Control Frame Generation    PAGEREF _Toc6650142 \h 32
 HYPERLINK \l "_Toc6650143" 4.5.3 TX/RX MAC Interface         PAGEREF _Toc6650143 \h 33
 HYPERLINK \l "_Toc6650144" 4.5.4 PAUSE Timer         PAGEREF _Toc6650144 \h 33
 HYPERLINK \l "_Toc6650145" 4.5.5 Slot Timer  PAGEREF _Toc6650145 \h 34
 HYPERLINK \l "_Toc6650146" 4.6 MII Management Module         PAGEREF _Toc6650146 \h 34
 HYPERLINK \l "_Toc6650147" 4.6.1 Operation Controller        PAGEREF _Toc6650147 \h 35
 HYPERLINK \l "_Toc6650148" 4.6.2 Shift Registers Operation   PAGEREF _Toc6650148 \h 36
 HYPERLINK \l "_Toc6650149" 4.6.3 Output Control Module Operation     PAGEREF _Toc6650149 \h 37
 HYPERLINK \l "_Toc6650150" 4.6.4 Clock Generator Operation   PAGEREF _Toc6650150 \h 37
 HYPERLINK \l "_Toc6650152" Architecture      PAGEREF _Toc6650152 \h 38
 HYPERLINK \l "_Toc6650153" 5.1 Host Interface        PAGEREF _Toc6650153 \h 40
 HYPERLINK \l "_Toc6650154" 5.2 TX Ethernet MAC       PAGEREF _Toc6650154 \h 40
 HYPERLINK \l "_Toc6650155" 5.3 RX Ethernet MAC       PAGEREF _Toc6650155 \h 40
 HYPERLINK \l "_Toc6650156" 5.4 MAC Control Module    PAGEREF _Toc6650156 \h 40
 HYPERLINK \l "_Toc6650157" 5.4.1 Control Frame Detector      PAGEREF _Toc6650157 \h 41
 HYPERLINK \l "_Toc6650158" 5.4.2 Control Frame Generator     PAGEREF _Toc6650158 \h 41
 HYPERLINK \l "_Toc6650159" 5.4.3 TX/RX Ethernet MAC Interface        PAGEREF _Toc6650159 \h 41
 HYPERLINK \l "_Toc6650160" 5.4.4 PAUSE Timer         PAGEREF _Toc6650160 \h 41
 HYPERLINK \l "_Toc6650161" 5.4.5 Slot Timer  PAGEREF _Toc6650161 \h 41
 HYPERLINK \l "_Toc6650162" 5.5 MII Management Module         PAGEREF _Toc6650162 \h 42
 HYPERLINK \l "_Toc6650163" 5.5.1 Operation Control Module    PAGEREF _Toc6650163 \h 42
 HYPERLINK \l "_Toc6650164" 5.5.2 Output Control Module       PAGEREF _Toc6650164 \h 42
 HYPERLINK \l "_Toc6650165" 5.5.3 Shift Register      PAGEREF _Toc6650165 \h 42
 HYPERLINK \l "_Toc6650166" 5.5.4 Clock Generator     PAGEREF _Toc6650166 \h 42

List of Tables
 TOC \h \z \t "Caption,1"  HYPERLINK \l "_Toc4153344" Table 1: Host Interface Ports (common ports)        PAGEREF _Toc4153344 \h 3
 HYPERLINK \l "_Toc4153345" Table 2: Host Interface Ports (internal DMA used)  PAGEREF _Toc4153345 \h 4
 HYPERLINK \l "_Toc4153346" Table 3: Host Interface Ports (external DMA is used)       PAGEREF _Toc4153346 \h 5
 HYPERLINK \l "_Toc4153347" Table 4: PHY Interface Ports       PAGEREF _Toc4153347 \h 7
 HYPERLINK \l "_Toc4153348" Table 5: Register List     PAGEREF _Toc4153348 \h 9
 HYPERLINK \l "_Toc4153349" Table 6: MODER Register    PAGEREF _Toc4153349 \h 11
 HYPERLINK \l "_Toc4153350" Table 7: INT_SOURCE Register      PAGEREF _Toc4153350 \h 11
 HYPERLINK \l "_Toc4153351" Table 8: INT_MASK Register        PAGEREF _Toc4153351 \h 12
 HYPERLINK \l "_Toc4153352" Table 9: IPGT Register    PAGEREF _Toc4153352 \h 13
 HYPERLINK \l "_Toc4153353" Table 10: IPGR1 Register  PAGEREF _Toc4153353 \h 13
 HYPERLINK \l "_Toc4153354" Table 11: IPGR2 Register  PAGEREF _Toc4153354 \h 14
 HYPERLINK \l "_Toc4153355" Table 12: PACKETLEN Register      PAGEREF _Toc4153355 \h 14
 HYPERLINK \l "_Toc4153356" Table 13: COLLCONF Register       PAGEREF _Toc4153356 \h 15
 HYPERLINK \l "_Toc4153357" Table 14: TX_BD_NUM Register      PAGEREF _Toc4153357 \h 15
 HYPERLINK \l "_Toc4153358" Table 15: CTRLMODER Register      PAGEREF _Toc4153358 \h 16
 HYPERLINK \l "_Toc4153359" Table 16: MIIMODER Register       PAGEREF _Toc4153359 \h 16
 HYPERLINK \l "_Toc4153360" Table 17: MIICOMMAND Register     PAGEREF _Toc4153360 \h 17
 HYPERLINK \l "_Toc4153361" Table 18: MIIADDRESS Register     PAGEREF _Toc4153361 \h 17
 HYPERLINK \l "_Toc4153362" Table 19: MIITX_DATA Register     PAGEREF _Toc4153362 \h 18
 HYPERLINK \l "_Toc4153363" Table 20: MIIRX_DATA Register     PAGEREF _Toc4153363 \h 18
 HYPERLINK \l "_Toc4153364" Table 21: MIISTATUS Register      PAGEREF _Toc4153364 \h 18
 HYPERLINK \l "_Toc4153365" Table 22: MAC_ADDR0 Register      PAGEREF _Toc4153365 \h 19
 HYPERLINK \l "_Toc4153366" Table 23: MAC_ADDR1 Register      PAGEREF _Toc4153366 \h 19
 HYPERLINK \l "_Toc4153367" Table 24: HASH0 Register  PAGEREF _Toc4153367 \h 20
 HYPERLINK \l "_Toc4153368" Table 25: HASH1 Register  PAGEREF _Toc4153368 \h 20
 HYPERLINK \l "_Toc4153369" Table 26: Tx Buffer Descriptor    PAGEREF _Toc4153369 \h 25
 HYPERLINK \l "_Toc4153370" Table 27: Tx Buffer pointer when internal DMA is used     PAGEREF _Toc4153370 \h 25
 HYPERLINK \l "_Toc4153371" Table 28: Rx Buffer Descriptor    PAGEREF _Toc4153371 \h 27
 HYPERLINK \l "_Toc4153372" Table 29: Rx Buffer pointer when internal DMA is used     PAGEREF _Toc4153372 \h 27

List of Figures
 TOC \h \z \t "Caption 1,1"  HYPERLINK \l "_Toc4750722" Figure 1: Tx Buffer Descriptor   PAGEREF _Toc4750722 \h 23
 HYPERLINK \l "_Toc4750723" Figure 2: Rx Buffer Descriptor    PAGEREF _Toc4750723 \h 25
 HYPERLINK \l "_Toc4750724" Figure 3: Structure of the PAUSE control frame    PAGEREF _Toc4750724 \h 32
 HYPERLINK \l "_Toc4750725" Figure 4: Architecture Overview   PAGEREF _Toc4750725 \h 39


Introduction
The Ethernet IP Core consists of five modules:
The MAC (Media Access Control) module, formed by transmit, receive, and control module
The MII (Media Independent Interface) Management module
The Host Interface
The Ethernet IP Core is capable of operating at 10 or 100 Mbps for Ethernet and Fast Ethernet applications. An external PHY is needed for the complete Ethernet solution.

IO Ports
2.1 Ethernet Core IO ports
The Ethernet IP Core uses three types of signals to connect to media: 
WISHBONE signals to connect to the Host Interface.
Common signals
Signals when the Internal DMA is used 
Signals when the External DMA is used
MII Management signals to connect to the PHY
Reset signals (for resetting different parts of the Ethernet IP Core
When internal or external DMA is used, different signals are used for the Host Interface.

2.1.1 Host Interface Ports (common ports)
The table below contains the common ports connecting the Ethernet IP Core to the Host Interface. The Host Interface is WISHBONE Rev. B compliant. 



All signals listed below are active HIGH, unless otherwise noted. Signal direction is with respect to the Ethernet IP Core. 

PortWidthDirectionDescriptionCLK_I1IClock InputRST_I1IReset InputADDR_I32IAddress InputDATA_I32IData InputDATA_O32OData OutputSEL_I4ISelect Input Array
Indicates which bytes are valid on the data bus. Whenever this signal is not 1111b during a valid access, the ERR_O is asserted.WE_I1IWrite Input
Indicates a Write Cycle when asserted high or a Read Cycle when asserted low. STB_I1IStrobe Input
Indicates the beginning of a valid transfer cycle.CYC_I1ICycle Input
Indicates that a valid bus cycle is in progress.ACK_O1OAcknowledgment Output
Indicates a normal Cycle termination.ERR_O1OError Acknowledgment Output
Indicates an abnormal cycle termination.INTA_O1OInterrupt Output A. Table  SEQ Table \* ARABIC 1: Host Interface Ports (common ports)

2.1.2 Host Interface Ports (internal DMA ports)
The table below contains the ports connecting the Ethernet IP Core to the Host Interface when the internal DMA is selected. The Host Interface is WISHBONE Rev. B compliant. 



All signals listed below are active HIGH, unless otherwise noted. Signal direction is with respect to the Ethernet IP Core. 

PortWidthDirectionDescriptionM_ADDR_O32OAddress OutputM_DATA_I32IData InputM_DATA_O32OData OutputM_SEL_O4ISelect Output Array
Indicates which bytes are valid on the data bus. Whenever this signal is not 1111b during a valid access, the ERR_I is asserted.M_WE_O1OWrite Output
Indicates a Write Cycle when asserted high or a Read Cycle when asserted low. M_STB_O1OStrobe Output
Indicates the beginning of a valid transfer cycle.M_CYC_O1OCycle Output
Indicates that a valid bus cycle is in progress.M_ACK_I1IAcknowledgment Input
Indicates a normal cycle termination.M_ERR_I1IError Acknowledgment Input
Indicates an abnormal cycle termination.Table  SEQ Table \* ARABIC 2: Host Interface Ports (internal DMA used)

2.1.3 Host Interface ports (external DMA ports)
The below table contains the ports connecting the Ethernet IP Core to the Host Interface when external DMA is used. The host interface is WISHBONE Rev. B compliant. 



All signals listed below are active HIGH, unless otherwise noted. Signal direction is with respect to the Ethernet IP Core. 

PortWidthDirectionDescriptionREQ0_O1OExternal DMA request to channel 0REQ1_O1OExternal DMA request to channel 1ACK0_I1IExternal DMA acknowledgment channel 0ACK1_I1IExternal DMA acknowledgment channel 1ND0_O1OForce Next Descriptor advancing for channel 0ND1_O1OForce Next Descriptor advancing for channel 1RD0_O1ORestart Descriptor for channel 0Table  SEQ Table \* ARABIC 3: Host Interface Ports (external DMA is used)

2.1.4 PHY Interface ports
The table below contains the ports connecting the Ethernet IP Core to the PHY Interface. All signals listed below are active HIGH, unless otherwise noted. Signal direction is with respect to the Ethernet IP Core. 

PortWidthDirectionDescriptionMTxClk1ITransmit Nibble or Symbol Clock. The PHY provides the MTxClk signal. It operates at a frequency of 25 MHz (100 Mbps) or 2.5 MHz (10 Mbps). The clock is used as a timing reference for the transfer of MTxD[3:0], MtxEn, and MTxErr. MTxD[3:0]4OTransmit Data Nibble. Signals are the transmit data nibbles. They are synchronized to the rising edge of MTxClk. When MTxEn is asserted, PHY accepts the MTxD. MTxEn1OTransmit Enable. When asserted, this signal indicates to the PHY that the data MTxD[3:0] is valid and the transmission can start. The transmission starts with the first nibble of the preamble. The signal remains asserted until all nibbles to be transmitted are presented to the PHY. It is deasserted prior to the first MTxClk, following the final nibble of a frame. MTxErr1OTransmit Coding Error. When asserted for one MTxClk clock period while MTxEn is also asserted, this signal causes the PHY to transmit one or more symbols that are not part of the valid data or delimiter set somewhere in the frame being transmitted to indicate that there has been a transmit coding error. MRxClk1IReceive Nibble or Symbol Clock. The PHY provides the MRxClk signal. It operates at a frequency of 25 MHz (100 Mbps) or 2.5 MHz (10 Mbps). The clock is used as a timing reference for the reception of MRxD[3:0], MRxDV, and MRxErr. MRxDV1IReceive Data Valid. The PHY asserts this signal to indicate to the Rx MAC that it is presenting the valid nibbles on the MRxD[3:0] signals. The signal is asserted synchronously to the MRxClk. MRxDV is asserted from the first recovered nibble of the frame to the final recovered nibble. It is then deasserted prior to the first MRxClk that follows the final nibble. MRxD
[3:0]4IReceive Data Nibble. These signals are the receive data nibble. They are synchronized to the rising edge of MRxClk. When MRxDV is asserted, the PHY sends a data nibble to the Rx MAC. For a correctly interpreted frame, seven bytes of a preamble and a completely formed SFD must be passed across the interface. MRxErr1IReceive Error. The PHY asserts this signal to indicate to the Rx MAC that a media error was detected during the transmission of the current frame. MRxErr is synchronous to the MRxClk and is asserted for one or more MRxClk clock periods and then deasserted. MColl1ICollision Detected. The PHY asynchronously asserts the collision signal MColl after the collision has been detected on the media. When deasserted, no collision is detected on the media.MCrS1ICarrier Sense. The PHY asynchronously asserts the carrier sense MCrS signal after the medium is detected in a non-idle state. When deasserted, this signal indicates that the media is in an idle state (and the transmission can start).MDC1OManagement Data Clock. This is a clock for the MDIO serial data channel. MDIO1I/OManagement Data Input/Output. Bi-directional serial data channel for PHY/STA communication. Table  SEQ Table \* ARABIC 4: PHY Interface Ports

2.1.5 Reset Signals
You may reset the MAC sub-modules using one or more separate signals. To reset the PHY, assert its RESET signal either through the boars system control register or by writing an appropriate bit in the PHY register.

Registers
This section describes all base, control, and status registers inside the Ethernet IP Core. The Address field indicates a relative address in hexadecimal. Width specifies the number of bits in the register, and Access specifies the valid access types to that register. RW stands for read and write access, RO for read-only access. A C appended to RW or RO indicates that some or all of the bits are cleared after a read. 

NameAddressWidthAccessDescriptionMODER0x0032RWMode RegisterINT_SOURCE0x0432RWInterrupt Source RegisterINT_MASK0x0832RWInterrupt Mask RegisterIPGT0x0C32RWBack to Back Inter Packet Gap RegisterIPGR10x1032RWNon Back to Back Inter Packet Gap Register 1IPGR20x1432RWNon Back to Back Inter Packet Gap Register 2PACKETLEN0x1832RWPacket Length (minimum and maximum) RegisterCOLLCONF0x1C32RWCollision and Retry ConfigurationRX_BD_NUM0x208RWReceive Buffer Descriptor NumberCTRLMODER0x2432RWControl Module Mode RegisterMIIMODER0x2832RWMII Mode RegisterMIICOMMAND0x2C32RWMII Commend RegisterMIIADDRESS0x3032RWMII Address Register
Contains the PHY address and the register within the PHY addressMIITX_DATA0x3432RWMII Transmit Data
The data to be transmitted to the PHYMIIRX_DATA0x3832RWMII Receive Data
The data received from the PHYMIISTATUS0x3C32RWMII Status RegisterMAC_ADDR00x4032RWMAC Individual Address0
The LSB four bytes of the individual address are written to this register.MAC_ADDR10x4432RWMAC Individual Address1
The MSB two bytes of the individual address are written to this register.ETH_HASH0_ADR0x4832RWHASH0 RegisterETH_HASH1_ADR0x4C32RWHASH1 RegisterTable  SEQ Table \* ARABIC 5: Register List

3.1 MODER (Mode Register)
Bit #AccessDescription31-17Reserved16RWRECSMALL  Receive Small Packets
0 = Packets smaller than MINFL are ignored.
1 = Packets smaller than MINFL are accepted.15RWPAD  Padding enabled
0 = Do not add pads to short frames. 
1 = Add pads to short frames (until the minimum frame length is equal to MINFL). 14RWHUGEN  Huge Packets Enable
0 = The maximum frame length is MAXFL. All additional bytes are discarded. 
1 = Frames up 64 KB are transmitted. 13RWCRCEN  CRC Enable
0 = Tx MAC does not append the CRC (passed frames already contain the CRC.
1 = Tx MAC appends the CRC to every frame.12RWDLYCRCEN  Delayed CRC Enabled
0 = Normal operation (CRC calculation starts immediately after the SFD).
1 = CRC calculation starts 4 bytes after the SFD.11RWRST  Reset MAC
0 = Normal operation.
1 = MAC is reset.10RWFULLD  Full Duplex
0 = Half duplex mode. 
1 = Full duplex mode. 9RWEXDFREN  Excess Defer Enabled 
0 = When the excessive deferral limit is reached, a packet is aborted.
1 = MAC waits for the carrier indefinitely.8RWNOBCKOF  No Backoff
0 = Normal operation (a binary exponential backoff algorithm is used).
1 = Tx MAC starts retransmitting immediately after the collision. 7RWLOOPBCK  Loop Back
0 = Normal operation. 
1 = TX is looped back to the RX. 6RWIFG  Interframe Gap for Incoming frames
0 = Normal operation (minimum IFG is required for a frame to be accepted).
1 = All frames are accepted regardless to the IFG.5RWPRO  Promiscuous
0 = Check the destination address of the incoming frames.
1 = Receive the frame regardless of its address.4RWIAM  Individual Address Mode
0 = Normal operation (physical address is checked when the frame is received.
1 = The individual hash table is used to check all individual addresses received.3RWBRO  Broadcast Address
0 = Receive all frames containing the broadcast address.
1 = Reject all frames containing the broadcast address unless the PRO bit = 1.2RWNOPRE  No Preamble
0 = Normal operation (7-byte preamble).
1 = No preamble is sent.1RWTXEN  Transmit Enable
0 = Transmit is disabled.
1 = Transmit is enabled.0RWRXEN  Receive Enable
0 = Receive is disabled.
1 = Receive is enabled.Table  SEQ Table \* ARABIC 6: MODER Register
Reset Value:
   MODER: 0000A800h

3.2 INT_SOURCE (Interrupt Source Register)
Bit #AccessDescription31-7Reserved6RWRXC  Receive Control Frame 
This bit indicates that the control frame was received. It is cleared by writing 1 to it.5RWTXC  Transmit Control Frame 
This bit indicates that a control frame was transmitted. It is cleared by writing 1 to it.4RWBUSY  Busy 
This bit indicates that a buffer was received and discarded due to a lack of buffers. It is cleared by writing 1 to it.3RWRXE - Receive Error
This bit indicates that an error occurred while receiving data. It is cleared by writing 1 to it.2RWRXB - Receive Frame
This bit indicates that a frame was received. It is cleared by writing 1 to it.1RWTXE - Transmit Error
This bit indicates that a buffer was not transmitted due to a transmit error.  It is cleared by writing 1 to it.0RWTXB  Transmit Buffer
This bit indicates that a buffer has been transmitted. It is cleared by writing 1 to it.Table  SEQ Table \* ARABIC 7: INT_SOURCE Register
Reset Value:
 INT_SOURCE: 00000000h

3.3 INT_MASK (Interrupt Mask Register)
Bit #AccessDescription31-7Reserved6RWRXC_M  Receive Control Frame Mask
0 = Event masked
1 = Event causes an interrupt5RWTXC_M  Transmit Control Frame Mask
0 = Event masked
1 = Event causes an interrupt4RWBUSY_M  Busy Mask
0 = Event masked
1 = Event causes an interrupt3RWRXE_M  Receive Error Mask
0 = Event masked
1 = Event causes an interrupt2RWRXF_M  Receive Frame Mask
0 = Event masked
1 = Event causes an interrupt1RWTXE_M  Transmit Error Mask
0 = Event masked
1 = Event causes an interrupt0RWTXB_M  Transmit Buffer Mask
0 = Event masked
1 = Event causes an interruptTable  SEQ Table \* ARABIC 8: INT_MASK Register
Reset Value:
    INT_MASK: 00000000h

3.4 IPGT (Back to Back Inter Packet Gap Register)
Bit #AccessDescription31-7Reserved6-0RWIPGT  Back to Back Inter Packet Gap
Full Duplex: The recommended value is 0x15, which equals 0.96 (s IPG (100 Mbps) or 9.6 (s (10 Mbps). The desired period in nibble times minus 6 should be written to the register.
Half Duplex: The recommended value and default is 0x12, which equals 0.96 (s IPG (100 Mbps) or 9.6 (s (10 Mbps). The desired period in nibble times minus 3 should be written to the register.Table  SEQ Table \* ARABIC 9: IPGT Register
Reset Value:
    IPGT: 00000012h

3.5 IPGR1 (Non Back to Back Inter Packet Gap Register 1)
Bit #AccessDescription31-7Reserved6-0RWIPGR1  Non Back to Back Inter Packet Gap 1
When a carrier sense appears within the IPGR1 window, Tx MAC defers and the IPGR counter is reset.
When a carrier sense appears later than the IPGR1 window, the IPGR counter continues counting. The recommended and default value for this register is 0xC. It must be within the range [0,IPGR2].Table  SEQ Table \* ARABIC 10: IPGR1 Register
Reset Value:
     IPGR1: 0000000Ch

3.6 IPGR2 (Non Back to Back Inter Packet Gap Register 2)
Bit #AccessDescription31-7Reserved6-0RWIPGR2  Non Back to Back Inter Packet Gap 2
The recommended and default value is 0x12, which equals to 0.96 (s IPG (100 Mbit/s) or 9.6 (s (10 Mbit/s).Table  SEQ Table \* ARABIC 11: IPGR2 Register
Reset Value:
      IPGR2: 00000012h

3.7 PACKETLEN (Packet Length Register)
Bit #AccessDescription31-16RWMINFL  Minimum Frame Length
The minimum Ethernet packet is 64 bytes long. If a reception of smaller frames is needed, assert the RECSMALL bit (in the mode register MODER) or change the value of this register. 
To transmit small packets, assert the PAD bit or the MINFL value (see the PAD bit description in the MODER register). 15-0RWMAXFL  Maximum Frame Length
The maximum Ethernet packet is 1518 bytes long. To support this and to leave some additional space for the tags, a default maximum packet length equals 1536 bytes (0x0600). If there is a need to support bigger packets, you can assert the HUGEN bit or increase the value of the MAXFL field (see the HUGEN bit description in the MODER).Table  SEQ Table \* ARABIC 12: PACKETLEN Register
Reset Value:
  PACKETLEN: 00400600h

3.8 COLLCONF (Collision and Retry Configuration Register)
Bit #AccessDescription31-20Reserved19-16RWMAXRET  Maximum Retry
This field specifies the maximum number of consequential retransmission attempts after the collision is detected. When the maximum number has been reached, the Tx MAC reports an error and stops transmitting the current packet. According to the Ethernet standard, the MAXRET default value is set to 0xf (15).15-6Reserved5-0RWCOLLVALID  Collision Valid
This field specifies a collision time window. A collision that occurs later than the time window is reported as a Late Collisions and transmission of the current packet is aborted. The default value equals 0x3f (by default, a late collision is every collision that occurs 64 bytes (63 + 1) from the preamble). Table  SEQ Table \* ARABIC 13: COLLCONF Register
Reset Value:
  COLLCONF: 000F003fh

3.9 TX_BD_NUM (Transmit BD Number Reg.)
Bit #AccessDescription31:8Reserved9:0RWTransmit Buffer Descriptor (Tx BD) Number
Number of the Tx BD (when external DMA is used) 
or
Number of the Tx BD multiplied by 2 (when internal DMA is used) Table  SEQ Table \* ARABIC 14: TX_BD_NUM Register
Reset Value:
        TX_BD_NUM: 00000080h

3.10 CTRLMODER (Control Module Mode Register)
Bit #AccessDescription31-3Reserved2RWTXFLOW  Transmit Flow Control
0 = PAUSE control frames are blocked.
1 = PAUSE control frames are allowed to be sent.1RWRXFLOW  Receive Flow Control
0 = Received PAUSE control frames are ignored.
1 = The transmit function (Tx MAC) is blocked when a PAUSE control frame is received.0RWPASSALL  Pass All Receive Frames
0 = Control frames are not passed to the host. The MAC Control module is enabled.
1 = All received frames are passed to the host. The MAC Control module is disabled.Table  SEQ Table \* ARABIC 15: CTRLMODER Register
Reset Value:
     CTRLMODER: 00000000h

3.11 MIIMODER (MII Mode Register) 
Bit #AccessDescription31-11Reserved10RWMIIMRST  Reset of the MIIM module9Reserved8RWMIINOPRE  No Preamble
0 = 32-bit preamble sent
1 = No preamble send7-0RWCLKDIV  Clock Divider
The field is a host clock divider factor. The host clock can be divided by an even number, greater then 1. The default value is 0x64 (100).Table  SEQ Table \* ARABIC 16: MIIMODER Register
Reset Value:
      MIIMODER: 00000064h

3.12 MIICOMMAND (MII Command Register)
Bit #AccessDescription31-3Reserved2RWWCTRLDATA  Write Control Data1RWRSTAT  Read Status0RWSCANSTAT  Scan StatusTable  SEQ Table \* ARABIC 17: MIICOMMAND Register
Reset Value:
   MIICOMMAND: 00000000h

3.13 MIIADDRESS (MII Address Register)
Bit #AccessDescription31-13Reserved12-8RWRGAD  Register Address (within the PHY selected by the FIAD[4:0])7-5Reserved4-0RWFIAD  PHY AddressTable  SEQ Table \* ARABIC 18: MIIADDRESS Register
Reset Value:
      MIIADDRESS: 00000000h

3.14 MIITX_DATA (MII Transmit Data)
Bit #AccessDescription31-16Reserved15-0RWCTRLDATA  Control Data (data to be written to the PHY)Table  SEQ Table \* ARABIC 19: MIITX_DATA Register
Reset Value:
      MIITX_DATA: 00000000h

3.15 MIIRX_DATA (MII Receive Data)
Bit #AccessDescription31-16Reserved15-0RWPRSD  Received Data (data read from the PHY)Table  SEQ Table \* ARABIC 20: MIIRX_DATA Register
Reset Value:
 MIIRX_DATA: 00000000h

3.16 MIISTATUS (MII Status Register)
Bit #AccessDescription31-3Reserved2RNVALID  Invalid
0 = The data in the MSTATUS register is valid.
1 = The data in the MSTATUS register is invalid.1RBUSY
0 = The MII is ready.
1 = The MII is busy (operation in progress).0RCLINKFAIL:
0 = The link is OK.
1 = The link failed.
The Link fail condition occurred (now the link might be OK). After a read, this bit is cleared. Another status read gets a new status.Table  SEQ Table \* ARABIC 21: MIISTATUS Register
Reset Value:
     MIISTATUS: 00000000h

3.17 MAC_ADDR0 (MAC Address Register 0)
Bit #AccessDescription31-24RWByte 2 of the Ethernet MAC address (individual address)23-16RWByte 3 of the Ethernet MAC address (individual address)15-8RWByte 4 of the Ethernet MAC address (individual address)7-0RWByte 5 of the Ethernet MAC address (individual address)Table  SEQ Table \* ARABIC 22: MAC_ADDR0 Register
Reset Value:
 MAC_ADDR0: 00000000h

Note: When an address is transmitted, byte 0 is sent first and byte 5 last.

3.18 MAC_ADDR1 (MAC Address Register 1)
Bit #AccessDescription31-16Reserved15-8RWByte 0 of the Ethernet MAC address (individual address)7-0RWByte 1 of the Ethernet MAC address (individual address)Table  SEQ Table \* ARABIC 23: MAC_ADDR1 Register
Reset Value:
       MAC_ADDR1: 00000000h

Note: When an address is transmitted, byte 0 is sent first and byte 5 last.

3.19 HASH0 (HASH Register 0)
Bit #AccessDescription31-0RWHash0 valueTable  SEQ Table \* ARABIC 24: HASH0 Register
Reset Value: 
  HASH0: 00000000h

3.20 HASH1 (HASH Register 1)
Bit #AccessDescription31-0RWHash1 valueTable  SEQ Table \* ARABIC 25: HASH1 Register
Reset Value:
    HASH1: 00000000h


Operation
This section describes the Ethernet IP Core operation. 
The core consists of five modules: 
The host interface connects the Ethernet Core to the rest of the system via the WISHBONE (using DMA transfers). Registers are also part of the host interface. 
The TX Ethernet MAC performs transmit functions.
The RX Ethernet MAC performs receive functions.
The MAC Control Module performs full duplex flow control functions.
The MII Management Module performs PHY control and gathers the status information from it.
All modules combined deliver full-function 10/100 Mbps Media Access Control. The Ethernet IP Core can operate in half- or full-duplex mode and is based on the CSMA/CD (Carrier Sense Multiple Access / Collision Detection) protocol.. 
When a station wants to transmit in half-duplex mode, it must observe the activity on the media (Carrier Sense). As soon as the media is idle (no transmission), any station can start transmitting (Multiple Access). If two or more stations are transmitting at the same time, a collision on the media is detected. All stations stop transmitting and back off for some random time. After the back-off time, the station checks the activity on the media again. If the media is idle, it starts transmitting. All other stations wait for the current transmission to end. 
In full-duplex mode, the Carrier Sense and the Collision Detect signals are ignored. The MAC Control module takes care of sending and receiving the PAUSE control frame to achieve Flow control (see the TXFLOW and RXFLOW bit description in the CTRLMODER register for more information). 
The MII Management module provides a media independent interface (MII) to the external PHY. This way, the configuration and status registers of the PHY can be read from/written to. 

4.1 Host Interface Operation
The host interface connects the Ethernet IP Core to the rest of the system (RISC, memory) via the WISHBONE bus. The WISHBONE serves to access the configuration registers and the memory. Currently, only DMA transfers are supported for transferring the data from/to the memory. 

4.1.1 Configuration Registers
The function of the configuration registers is transparent and can be easily understood by reading the Registers section (Chapter  REF _Ref4387033 \r \h 3). 

4.1.2 External/Internal DMA Operation
The Ethernet MAC can use an external or internal DMA engine:
An External DMA core is needed. This mode is not recommended because it will soon be obsolete.
The Ethernet IP core uses Internal DMA resources. 
The selection between external and internal DMA is made in the eth_defines.v file. 

4.1.3 Buffer Descriptors (BD)
The transmission and the reception processes are based on the descriptors. The Transmit Descriptors (TxD) are used for transmission while the Receive Descriptors (RxD) are used for reception. 
When using an internal DMA, the buffer descriptors are 64 bits long. The first 32 bits are reserved for length and status while the last 32 bits contain the pointer to the associated buffer (where data is stored). The Ethernet MAC core has an internal RAM that can store up to 128 BDs (for both Rx and Tx).
When using external DMA, buffer descriptors are 32 bits long. Status and length information is stored to these 32 bits. Pointers to the associated buffers are stored in the external DMA core (additional descriptors that are part of the DMA). The Ethernet MAC core has an internal RAM that can store up to 256 descriptors (for both Rx and Tx).
The first 32 bits are the same for both, internal and external DMA operation. The difference lies in the buffer pointer (read the above section).
The internal memory saves all descriptors at addresses from 0x400 to 0x800 (128 64bit descriptors when the internal DMA is used or 256 32bit descriptors when the external DMA is used). The transmit descriptors are located between the start address (0x400) and the address that equals the value written in the TX_BD_NUM register (page  PAGEREF _Ref532008757 \h 15) multiplied by 4. This register holds the number of the Tx buffer descriptors used multiplied by 2. The receive descriptors are located between the start address (0x400), plus the address number written in the TX_BD_NUM multiplied by 4, and the descriptor end address (0x800). 
The transmit and receive status of the packet is written to the associated buffer descriptor once its transmission/reception is finished. 

4.1.3.1 Tx Buffer Descriptors
The transmit descriptors contain information about associated buffers (length, status). When the internal DMA is selected, they also contain pointers to the buffers holding the relevant data.

ADDR = Offset + 0
31302928272625242322212019181716LEN1514131211109876543210RDIRQWRPADCRCReservedURRTRY[3:0]RLLCDFCS
ADDR = Offset + 4
31302928272625242322212019181716TXPNT1514131211109876543210TXPNTFigure  SEQ Figure \* ARABIC 1: Tx Buffer Descriptor

Bit #AccessDescription31-16RWLEN  Length
Number of bytes associated with the BD to be transmitted. 15RWRD  Tx BD Ready
0 = The buffer associated with this buffer descriptor is not ready, and you are free to manipulate it. After the data from the associated buffer has been transmitted or after an error condition occurred, this bit is cleared to 0. 
1 = The data buffer is ready for transmission or is currently being transmitted. You are not allowed to manipulate this descriptor once this bit is set. 14RWIRQ  Interrupt Request Enable
0 = No interrupt is generated after the transmission. 
1 = When data associated with this buffer descriptor is sent, a TXB or TXE interrupt will be asserted (see  REF _Ref532014672 \h  \* MERGEFORMAT 3.2 INT_SOURCE (Interrupt Source Register) for more details). 13RWWR  Wrap
0 = This buffer descriptor is not the last descriptor in the buffer descriptor table. 
1 = This buffer descriptor is the last descriptor in the buffer descriptor table. After this buffer descriptor was used, the first buffer descriptor in the table will be used again. 12RWPAD  Pad Enable
0 = No pads will be add at the end of short packets. 
1 = Pads will be added to the end of short packets. 11RWCRC  CRC Enable
0 = CRC wont be added at the end of the packet.
1 = CRC will be added at the end of the packet.10:9Reserved8RWUR  Underrun 
Underrun occurred while sending this buffer.7:4RWRTRY  Retry Count 
This bit indicates the number of retries before the frame was successfully sent. 3RWRL  Retransmission Limit 
This bit is set when the transmitter fails. (Retry Limit + 1) attempts to successfully transmit a message due to repeated collisions on the medium. The Retry Limit is set in the COLLCONF register on page  PAGEREF _Ref1709320 \h 15. 2RWLC  Late Collision
Late collision occurred while sending this buffer. The transmission is stopped and this bit is written. Late collision is defined in the COLLCONF register on page  PAGEREF _Ref1709320 \h 15.1RWDF  Defer Indication
The frame was deferred before being sent successfully, i.e. the transmitter had to wait for Carrier Sense before sending because the line was busy. This is not a collision indication. Collisions are indicated in RTRY. 0RWCS  Carrier Sense Lost
This bit is set when Carrier Sense is lost during a frame transmission. The Ethernet controller writes CS after it finishes sending the buffer.Table  SEQ Table \* ARABIC 26: Tx Buffer Descriptor

Bit #AccessDescription31-0RWTXPNT  Transmit Pointer
This is the buffer pointer when the associated frame is stored. Table  SEQ Table \* ARABIC 27: Tx Buffer Pointer When Internal DMA is Used

4.1.3.2 Rx Buffer Descriptors
The receive BDs contain information about the received frames (length, status). When the internal DMA is selected, they also contain pointers to the buffers holding the relevant data.

ADDR = Offset + 0
31302928272625242322212019181716LEN1514131211109876543210EIRQWRReservedMORISDNTLSFCRCLC
ADDR = Offset + 4
31302928272625242322212019181716RXPNT1514131211109876543210RXPNTFigure  SEQ Figure \* ARABIC 2: Rx Buffer Descriptor

Bit #AccessDescription31-16RWLEN  Number of the received bytes associated with this BD. 15RWE  Empty
0 = The data buffer associated with this buffer descriptor has been filled with data or has stopped because an error occurred. The core can read or write this BD. As long as this bit is zero, this buffer descriptor wont be used. 
1 = The data buffer is empty (and ready for receiving data) or currently receiving data. 14RWIRQ  Interrupt Request Enable
0 = No interrupt is generated after the reception. 
1 = When data is received (or error occurs), an RXF interrupt will be asserted (See  REF _Ref532014672 \h  \* MERGEFORMAT 3.2 INT_SOURCE (Interrupt Source Register) for more details).13RWWRAP
0 = This buffer descriptor is not the last descriptor in the buffer descriptor table. 
1 = This buffer descriptor is the last descriptor in the buffer descriptor table. After this buffer descriptor is used, the first Rx buffer descriptor in the table will be used again. 12:8Reserved.7RWM  Miss
0 = The frame is received because of an address recognition hit.
1 = The frame is received because of promiscuous mode.
The Ethernet controller sets M for frames that are accepted in promiscuous mode but are tagged as a miss by internal address recognition. Thus, in promiscuous mode, M determines whether a frame is destined for this station.6RWOR  Overrun
This bit is set when a receiver overrun occurs during frame reception.5RWIS  Invalid Symbol
This bit is set when the reception of an invalid symbol is detected by the PHY.4RWDN  Dribble Nibble
This bit is set when a received frame cannot de divided by 8 (one extra nibble has been received).3RWTL  Too Long
This bit is set when a received frame is too long (bigger than the value set in the PACKETLEN register (page  PAGEREF _Ref1714173 \h 14). 2RWSF  Short Frame
This bit is set when a frame that is smaller than the minimum length is received (minimum length is set in the PACKETLEN register (page  PAGEREF _Ref1714173 \h 14)).1RWCRC  Rx CRC Error
This bit is set when a received frame contains a CRC error.0RWLC  Late Collision
This bit is set when a late collision occurred while receiving a frame.Table  SEQ Table \* ARABIC 28: Rx Buffer Descriptor

Bit #AccessDescription31-0RWRXPNT  Receive Pointer
This is the pointer to the buffer storing the associated frame. Table  SEQ Table \* ARABIC 29: Rx Buffer pointer when internal DMA is used

4.1.4 Frame Transmission
There are a few differences in the frame transmission regarding the use of external or internal DMA.

4.1.4.1 Frame Transmission with Internal DMA
To transmit the first frame, the RISC must do several things, namely:
Store the frame to the memory. 
Associate the Tx BD in the Ethernet MAC core with the packet written to the memory (length, pad, crc, etc.). See section  REF _Ref1717891 \h  \* MERGEFORMAT 4.1.3 Buffer Descriptors (BD) for more information.
Enable the TX part of the Ethernet Core by setting the TXEN bit to 1. 
As soon as the Ethernet IP Core is enabled, it continuously reads the first BD. Immediately when the descriptor is marked as ready, the core reads the pointer to the memory storing the associated data and starts then reading data to the internal FIFO. At the moment the FIFO is full, transmission begins. 
At the end of the transmission, the transmit status is written to the buffer descriptor and an interrupt might be generated (when enabled). Next, two events might occur (according to the WR bit (wrap) in the descriptor):
If the WR bit has not been set, the BD address is incremented, the next descriptor is loaded, and the process starts all over again (if next BD is marked as ready). 
If the WR bit has been set, the first BD address (base) is loaded again. As soon as the BD is marked as ready, transmission will start.

4.1.4.1 Frame Transmission with External DMA
To transmit the first frame, the RISC must do several things, namely:
Store the frame to the memory 
Associate the first DMA descriptor with the stored frame:
The source address field points to the frame in the memory.
The destination field points to the Ethernet Host Interface.
The next pointer field points to the next descriptor in the memory (this descriptor has not been stored yet).
The total transfer size equals the stored frame size.
The incremented source and destination address fields must be set to zero. You should always use the source and destination address of the descriptor written in the next descriptor field. 
Set the EOL bit to zero, indicating that this descriptor is the last descriptor in the list (and the frame is the last frame).
Set the channel 0 registers (channel 0 is used for transmitting).
Enable the channel by setting the CH_EN bit to 1. The channel is now enabled and will start operating as soon as the REQ0 signal is asserted.
Associate the transmit buffer descriptor in the Ethernet MAC core with the packet written to the memory. Enable the TX part of the Ethernet IP Core by setting the TXEN bit and the DMAEN bit to 1. 
As soon as the Ethernet IP Core is enabled and the transmit descriptor is ready, the Core will assert the DMA request signal (REQ0). Upon noticing the request, the DMA will start transmitting the first word (32-bits) of the pointed frame. The REQ0 will be asserted each time 32 bits of the data are needed. When the last 32 bits are needed, the request for the next descriptor  the ND0 signal  is asserted. The ND0 instructs the DMA to load the next descriptor after the last word has been transmitted. 
At the end of the transmission, the transmit status is written to the buffer descriptor and an interrupt might be generated. Next, two events might occur (according to the EOL bit in the descriptor):
If the EOL bit has not been set, more frames stored in the memory are still waiting to be sent. A new descriptor is loaded, and the whole process starts all over again. The DMA has been set already 
If the EOL bit has been set, the DMA channel stops and clears the CH_EN bit in the channel CSR register. To start the transmission, restore the settings required for the beginning of the first packet transmission. 

4.1.5 Frame Reception
There are a few differences in the frame reception regarding the use of external or internal DMA.

4.1.5.1 Frame Reception when Internal DMA is used
To receive the first frame, the RISC must do several things, namely:
Set the receive buffer descriptor to be associated with the received packet and mark it as empty.
Enable the Ethernet receive function by setting the RECEN bit to 1. 
The Ethernet IP Core reads the Rx BD. If it is marked as empty, it starts receiving frames. The Ethernet receive function receives an incoming frame nibble per nibble. After the whole frame has been received and stored to the memory, the receive status and the pointer to the memory storing the data are written to the BD. An interrupt might be generated (if enabled). Then the BD address is incremented and the next BD loaded. If the new BD is marked as empty, another frame can be received; otherwise the operation stops.

4.1.5.2 Frame Reception with External DMA
When the RISC wants to receive the first frame, it must do several things, namely:
Set the descriptors to be used with the DMA channel 1 to appropriate values (to store the incoming data). 
Set and enable channel 1 to use the descriptors.
Set the receive buffer descriptor to be associated with the received packet.
Enable the Ethernet receive function by setting the RECEN and DMAEN bits to 1. 
The Ethernet receive function receives an incoming frame nibble per nibble. After it has received a whole word, it is written to the memory via the WISHBONE by asserting the REQ1 signal (requesting the DMA write to the memory on channel 1). After the whole frame has been received, the ND1 signal is asserted to force usage of the next descriptor with the next frame. The receive status is written to the receive buffer descriptor. 

4.2. DMA Operation
The DMA operation allows for completely transparent data movement between the Ethernet IP Core and the function attached to the WISHBONE bus. Once set up, no function micro controller intervention is needed for normal operations. The Ethernet IP Core has two associated pairs of REQn and ACKn signals. 
When the DMAEN bit in the MODER register is set, the Ethernet IP Core will use the DMA_REQ and DMA_ACK signals for the DMA flow control. The DMA_REQ signal is asserted when data is in the buffer (receiving frames) or when the buffer is empty and needs to be filled (transmitting frames). The DMA must reply with a DMA_ACK for each word (4 bytes) transferred. The buffer holds one MAX_PL_SZ packet (one word). Depending on the DMA and external bus latency, it might be set up to hold more than that. In this case, additional action needs to be performed in the core (but is not yet supported).
More information about Ethernet-DMA functionality can be found in the section  REF _Ref4152520 \h 4.1.2 External/Internal DMA Operation. 
For more general information about the DMA and descriptors, read the WISHBONE DMA/Bridge Core Specification available at www.opencores.org/projects/wb_dma/.

4.3 TX Ethernet MAC
The TX Ethernet MAC generates 10BASE-T/100BASE-TX transmit MII nibble data streams in response to the byte streams the transmit logic (host) supplies. It performs the required deferral and back-off algorithms, takes care of the inter-packet gap (IPG), computes the checksum (FCS), and monitors the physical media (by monitoring Carrier Sense and collision signals). The TX Ethernet MAC is divided into several modules that provide the following functionality:
Generation of the signals connected to the Ethernet PHY during the transmission process
Generation of the status signals the host uses to track the transmission process
Random time generation used in the back-off process after a collision has been detected
CRC generation and checking
Pad generation
Data nibble generation

4.4 RX Ethernet MAC
The RX Ethernet MAC transmits the data streams to the host in response to the 10BASE-T or 100BASE-TX received MII nibbles. The module is divided into several sub-modules providing the following functionality: 
Preamble removal
Data assembly (from input nibble to output byte)
CRC checking for all incoming packets 
Generation of the signal that can be used for address recognition (in the hash table)
Generation of the status signals the host uses to track the reception process 

4.5 MAC Control Module
The MAC Control Module performs a real-time flow control function for the full-duplex operation. The control opcode PAUSE is used for stopping the station transmitting the packets. The receive buffer (FIFO) starts filling up when the upper layer cannot continue accepting the incoming packets. Before an overflow happens, the upper layer sends a PAUSE control frame to the transmitting station. This control frame inhibits the transmission of the data frames for a specified period of time. 
When the MAC Control module receives a PAUSE control frame, it loads the pause timer with the received value into the pause timer value field. The Tx MAC is stopped (paused) from transmitting the data frames for the pause timer value slot times. The pause timer decrements by one each time a slot time passes by. When the pause time number equals zero, the MAC transmitter resumes the transmit operation. 
The MAC Control Module has the following functionality:
Control frame detection 
Control frame generation 
TX/RX MAC Interface 
PAUSE Timer
Slot Timer

4.5.1 Control Frame Detection 
The incoming data packets are passed from the receiver via the MAC Control Module to the upper layers while the control frames are usually dropped. The PASSALL bit in the CTRLMODER register defines whether the control frames are passed or dropped. 
A valid PAUSE control frame has the frame structure described in  REF _Ref4736169 \h Figure 3Figure 3:

Figure  SEQ Figure \* ARABIC 3: Structure of the PAUSE control frame

The destination address must be a reserved multicast address (01-80-c2-00-00-01) or a destination address equal to the Ethernet IP Core MAC address. The Length/Type field must be equal to 8808 and the opcode to 0001 for a PAUSE control frame. 
When the receive flow control and the MAC Control Module are enabled (RXFLOW asserted and PASSALL deasserted), a PAUSE Timer Value from the PAUSE control frame is passed to the PAUSE timer.

4.5.2 Control Frame Generation
When the host wants to send a PAUSE control frame, it asserts the Transmit Pause Request (TPAUSERQ). When a request is detected, the control module waits for the current transmission to end. It then starts transmitting the PAUSE control frame by asserting the Transmit Packet Start Frame (TxStartFrm) and providing the appropriate control data. Sending CtrlFrm is used to instruct the Transmit function (TX Ethernet MAC) to pad and append the FCS. The transmit Pause Frame End (TxEndFrm) is asserted at the end to inform the host that a Pause request was sent. 
Asserting the TXFLOW bit in the MODER register enables the transmission of the PAUSE control frame.  
The TPAUSERQ signal (request) is latched in the MAC Control Generator and reset after the PAUSE control frame has been transmitted. This prevents issuing a new PAUSE request until the current request is sent. The Transmit Pause Timer Value TPAUSETV[15:0] is set prior to the transmit pause request. The TPAUSETV contains the value to be sent as a Pause Timer Value in the pause control frame ( REF _Ref4736169 \h Figure 3Figure 3).

4.5.3 TX/RX MAC Interface
The MAC Control Module is connected between the host and the Tx and Rx modules. When enabled, the its logic takes over the control of the following signals: TxData[7:0], TxStartFrm, TxEndFrm, TxUsedData, TxDone, and TxAbort. These signals are connected directly between the host and the MAC transmit and receive functions when data frames (not control frames) are transmitted or received. 
On the other hand, when a host wants to send a PAUSE control frame, it asserts a TPauseRQ request signal . It is then up to the MAC Control Module to initiate the transmission. In this case, the above signals are not connected to the host any more. The MAC Control Module drives the appropriate control data signals and instructs the Tx module to transmit. 
When a PAUSE control frame is received, the frame can be dropped or passed to the host, depending on the state of the PASSALL signal. Again TxData[7:0], TxStartFrm, TxEndFrm, TxUsedData, TxDone, and TxAbort are not connected directly.

4.5.4 PAUSE Timer
The 16bit PAUSE timer is loaded with a pause timer value when a PAUSE control frame is received. The timer inhibits the data frame transmissions for the timer value time slots. This is done by:  
Preventing the Tx MAC module from seeing the signal TxStartFrm from the host
Preventing the host from seeing the signal TxUsedData from the Tx module
The timer decrements by one each time a time slot passes by. A Slot Timer is used for counting the slot time.  

4.5.5 Slot Timer
The Slot Timer is activated when a PAUSE Timer is preloaded. It counts slot times and generates pulses to the PAUSE Timer for every slot time passed. 

4.6 MII Management Module
The MII Management Module is a simple two-wire interface between the host and an external PHY device. It is used for configuration and status read of the physical device. The physical interface consists of a management data line MDIO (Management Data Input/Output) and a clock line MDC (Management Data Clock). During the read/write operation, the most significant bit is shifted in/out first from/to the MDIO data signal. On each rising edge of the MDC, a Shift register is shifted to the left and a new value appears on the MDIO. 
Internally the interface consists of four signals: 
MDC
MDI
MDO
MDOEN (Management Data Output Enable)
The unidirectional lines MDI, MDO, and MDOEN are combined to make a bi-directional signal MDIO that is connected to the PHY. 
The configuration and status data is written/read to/from the PHY via the MDIO signal. 
The MDC is a low frequency clock derived from dividing the host clock. 
Three commands are supported for controlling the PHY:
Write Control Data (writes the control data to the PHY Configuration registers)
Read Status (reads the PHY Control and Status register)
Scan Status (continuously reads the PHY Status register of one or more PHYs [link fail status]).
The MII Management Module consists of four sub modules:
Operation Controller
Shift Registers
Output Control Module
Clock Generator 

4.6.1 Operation Controller
The Operation Controllers task is to perform all supported commands: Write Control Data, Read Status, and Scan Status. 

4.6.1.1 Write Control Data
A host initiates a write operation by asserting the WCTRLDATA signal. This signal also indicates that the host data CTLD[15:0], the PHY address FIAD[4:0], and the PHY register address RGAD[4:0] are valid. As soon as the host asserts the WCTRLDATA signal, the MIIM module asserts the BUSY signal to inform the host that the write operation is in process. MDOEN is asserted to enable the output line MDO (MDIO) to the PHY. The MIIM module then clocks out the MIIM frame to the PHY on each rising edge of the MDC. The MIIM frame write format conforms to the IEEE 803.2u Specification:
32-bit long preamble (all ones) if the MIINOPRE bit is not asserted
2-bit long Start of frame pattern ST (zero followed by one)
2-bit Operation definition (zero-one for write or one-zero for read)
5-bit PHY address (FIAD[4:0])
5-bit PHY register address RGAD[4:0]
2-bit turnaround field TA (one-zero)
16-bit data
At the end of the write operation, the BUSY signal is deasserted.

4.6.1.2 Read Status
A host initiates a write operation by asserting the RSTAT signal. This signal also indicates that the PHY address FIAD[4:0] and the PHY register address RGAD[4:0] are valid. As soon as the host asserts the RSTAT signal, the MIIM module asserts the BUSY signal to inform the host that the read operation is in process. MDOEN is asserted to enable the output line MDO (MDIO) to the PHY. The MIIM module then clocks out the MIIM frame to the PHY on each rising edge of the MDC and afterwards clocks in the requested data (status). The MIIM read frame format conforms to the IEEE 803.2u Specification:
32-bit long preamble (all ones) if the MIINOPRE bit is not asserted
2-bit long Start of frame pattern ST (zero followed by one)
2-bit Operation definition (zero-one for write or one-zero for read)
5-bit PHY address (FIAD[4:0])
5-bit PHY register address RGAD[4:0]
2-bit turnaround field TA (one-bit period in which the PHY stays in the high-Z state followed by a one-bit period during which the PHY drives a zero on the MDO)
MIIM deasserts the MDOEN signal that enables the MDI (MDIO works as an input) 
PHY sends the data (status) back to the MIIM Module on the data lines PRSD[15:0]
At the end of the read operation, the MIIM deasserts the BUSY signal to indicate to the host that valid data is on the PRSD[15:0] lines. 

4.6.1.3 Scan Status
A host initiates the Scan Status Operation by asserting the SCANSTAT signal. The MIIM performs a continuous read operation of the PHY Status register. The PHY is selected by the FIAD[4:0] signals. The link status LinkFail signal is asserted/deasserted by the MIIM module and reflects the link status bit of the PHY Status register. The signal NVALID is used for qualifying the validity of the LinkFail signals and the status data PRSD[15:0]. These signals are invalid until the first scan status operation ends. 
During the scan status operation, the BUSY signal is asserted until the last read is performed (the scan status operation is stopped). 

4.6.2 Shift Registers Operation
There are two shift registers in the MII Management Module. The Data Shift register is used for:
Shifting out the data to the PHY during the Write Data Control operation
Shifting in the data during the Read Status operation 
Shifting out the FIAD[4:0] and RGAD[4:0] addresses during all operations
The Status Shift register contains the data latched during the last Read Status Operation. Two additional status signals (LinkFail Status and Status Invalid NVALID) are latched separately from the Status Shift register. 
When a Scan Operation is requested, the state of the PRSD[15:0] and a MIILF is constantly updated from the selected PHY register. NVALID is used to qualify the validity of the PRSD[15:0] and MIILS signals. These signals are invalid until the first Scan Status Operation ends.

4.6.3 Output Control Module Operation
The Output Control Module combines the MDI, MDO, and MDOEN signals into a bi-directional MDIO signal that is connected to the external MII PHY. During the Write Control Data Operation, the MDIO operates as an output from the MIIM module. The signal is used for transferring data from the MIIM Module to the PHY. During the Read Status Operation, the MDIO first operates as an output (addressing the PHY and the PHY Internal register) and then as an input to the MIIM Module (reading the status data). In both cases the most significant bit of the data is shifted first. When no operation is performed, the MDIO is tri-stated. 

4.6.4 Clock Generator Operation
The Management Data Clock MDC is a divided host clock. The division factor is set in the MIIMODER register by setting the CLKDIV[7:0] field (MDC depends on the PHY and can be 2.5 MHz or 12.5 MHz.

Architecture
The Ethernet IP Core consists of 5 modules: 
Host Interface and the BD structure
TX Ethernet MAC (transmit function)
RX Ethernet MAC (receive function)
MAC Control Module
MII Management Module
Figure  SEQ Figure \* ARABIC 5: Architecture Overview

5.1 Host Interface
The host interface is connected to the RISC and the memory through the Wishbone. The RISC writes the data for the configuration registers directly while the data frames are written to the memory. Frames are accessed through the DMA. 

5.2 TX Ethernet MAC
The TX Ethernet MAC generates 10BASE-T/100BASE-TX transmit MII nibble data streams in response to the byte streams supplied by the transmit logic (host). It performs the required deferral and back-off algorithms, takes care of the IPG, computes the checksum (FCS) and monitors the physical media (by monitoring Carrier Sense and collision signals). 

5.3 RX Ethernet MAC
The RX Ethernet MAC interprets 10BASE-T/100BASE-TX MII receive data nibble streams and supplies correctly formed packet-byte streams to the host. It searches for the SFD (start frame delimiter) at the beginning of the packet, verifies the FCS, and detects any dribble nibbles or receive code violations.

5.4 MAC Control Module
The function of this module is to implement the full-duplex flow control.
The MAC Control Module consists of three sub-modules that provide the following functionality:
Control frame detection 
Control frame generation 
TX/RX Ethernet MAC Interface 
PAUSE Timer
Slot Timer

5.4.1 Control Frame Detector
The control frame detector checks the incoming frames for the control frames. Control frames can be discarded or passed to the host. When a PAUSE control frame is detected, it can stop the Tx module from transmitting for a certain period of time. 

5.4.2 Control Frame Generator
If the need arises to stop the transmitting station from transmitting (flow control in full-duplex mode), a PAUSE control frame can be sent. 

5.4.3 TX/RX Ethernet MAC Interface
The MAC Control Module is connected between the host interface, the Tx, and the Rx MAC modules. Signals from the host are passed to the Tx MAC in certain occasions and vice versa. 

5.4.4 PAUSE Timer
When a PAUSE control frame is received, the pause timer value is written to the PAUSE timer. This prevents the Tx module from transmitting for a pause timer value period of slot time. 

5.4.5 Slot Timer
The slot timer measures time slots and generate a pulse to the PAUSE timer for every slot time passed by. 

5.5 MII Management Module
The function of the MII Management Module is to control the PHY and to gather information from it (status). 
It consists of four sub modules:
Operation Control Module
Output Control Module
Shift Register
Clock Generator 

5.5.1 Operation Control Module
The function of the Operation Control Module is to perform the following commands:
Write control data 
Read status
Scan status

5.5.2 Output Control Module
The Output Control Module controls the signal appearance on the MDO, MCK, and MDOEN pins.

5.5.3 Shift Register
The shift registers hold the status read from an external PHY.

5.5.4 Clock Generator
The clock generator generates an appropriate output clock MCK according to the input host clock and the clock divider bits (CLKDIV[7:0] in the MIIMODER register). 

 TIME \@ "MMMM d, yyyy" April 15, 2002    Ethernet IP Core Specification





http://www.opencores.org        Rev 1.3 Preliminary      PAGE ii


 HYPERLINK "http://www.opencores.org" http://www.opencores.org        Rev 1.13 Preliminary     PAGE vii 




 HYPERLINK "http://www.opencores.org" http://www.opencores.org    Rev 1.13 Preliminary     PAGE 30 of  SECTIONPAGES42


Length/
Type

8808

Dest. Address or
reserved Multicast  address
01-80-c2-00-00-01

Source Address


xx-xx-xx-xx-xx-xx

Opcode


0001

Pause Timer Value
xxxx

CRC


xxxxxxxx

Reserved


xxxxxxxxxx

6

6

2

2

2

42

4

64 Bytes

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