ĐĎॹá > ţ˙ , . ţ˙˙˙ + e ű ˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙ěĽÁ 7 $ řż s bjbjUU gE 7| 7| Š u T ˙˙ ˙˙ ˙˙ l # # # 4 # ž0 ž0 ž0 h &1 :1 D # f . 1 1 " Ź1 Ź1 Ô1 f5 f5 f5 f f f f f f f $ śh Öj Ü -f # f5 5 ^ f5 f5 f5 -f 47 Ź1 Ô1 4 Bf 47 47 47 f5 Ę & Ź1 ( # Ô1 f 47 f5 f 47 â 47 > Ę [ Ř *" Ö # ke Ô1 ~1 dţĄĄ`Â# *
ž0 06 gd ke Xf 0 f éd ˛k ž6 v ˛k ke 47 4# T# @ Ů
Ethernet IP Core Product Brief
Introduction
The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 and 802.3u specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively.
Features
The core provides the following features:
Flow control and automatic generation of control frames in full duplex mode (IEEE 802.3x)
Collision detection and auto re-transmission on collisions in half duplex mode (CSMA/CD protocol)
Automatic 32-bit CRC generation and checking
Preamble generation and removal
Complete status for TX/RX packets
IEEE 802.3 Media Independent Interface (MII)
WISHBONE SoC Interconnection Rev. B compliant interface
Figure 1: Core Architecture Overview
General Description
Architecture
Adjoining figure shows the general architecture of the Ethernet IP core. It consists of several building blocks:
TX Ethernet MAC (transmit function) block with the CRC generator
RX Ethernet MAC (receive function) block with the CRC generator
MAC control block
Management block (MIIM)
Host interface
TX and RX Modules
The TX and RX modules provide full transmit and receive functionality. CRC generators are incorporated in both modules for error detection purposes. The modules also handle preamble generation and removal. Padding occurs automatically (when enabled) in compliance with the IEEE 802.3 standard. When enabled, packets greater than the standard can be transmitted.
Control Module
The control module provides full duplex flow control, according to the IEEE 802.3u standard. Flow control is achieved by transfering the PAUSE control frames between the communicating stations.
Management Module (MIIM)
The management module provides the standard IEEE 802.3 Media Independent Interface (MII) that defines the connection between the PHY and link layers. Using this interface, the device (RISC) connected to the host interface can force PHY to run at 10 Mbps versus 100 Mbps or to configure it to run at full versus half duplex mode.
WISHBONE Interface
The WISHBONE interface connects the Ethernet core to the RISC and to external memory. The core is WISHBONE SoC Interconnection specification Rev. B compliant. The implementation realizes a 32-bit bus width and does not support other bus widths.
Utilization
The table in this section lists the intended applications of the different cores.
TechnologyAreaSilicon AreaSpeedPower ConsumptionXilinx Virtex2600 slices100000 gates60 MHz (25 needed)TBD
OpenCores reserves the right to make changes in specifications at any time and without notice. The information furnished by OpenCores in this publication is believed to be accurate and reliable. No responsibility, however, is assumed by OpenCores for its use, nor for any infringements of patents or other rights of third parties resulting from its use. This product is intended for use in normal commercial applications. Use of this product in applications such as life-support or life-sustaining equipment is at your own risc.
(footnote continued)
OpenCores
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Ethernet IP Core
OpenCores
Ethernet IP Core
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ĐĎॹá > ţ˙ , . ţ˙˙˙ + e ű ˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙ěĽÁ 7 $ řż s bjbjUU gE 7| 7| Š u T ˙˙ ˙˙ ˙˙ l # # # 4 # ž0 ž0 ž0 h &1 :1 D # f . 1 1 " Ź1 Ź1 Ô1 f5 f5 f5 f f f f f f f $ śh Öj Ü -f # f5 5 ^ f5 f5 f5 -f 47 Ź1 Ô1 4 Bf 47 47 47 f5 Ę & Ź1 ( # Ô1 f 47 f5 f 47 â 47 > Ę [ Ř *" Ö # ke Ô1 ~1 dţĄĄ`Â# *
ž0 06 gd ke Xf 0 f éd ˛k ž6 v ˛k ke 47 4# T# @ Ů
Ethernet IP Core Product Brief
Introduction
The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 and 802.3u specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively.
Features
The core provides the following features:
Flow control and automatic generation of control frames in full duplex mode (IEEE 802.3x)
Collision detection and auto re-transmission on collisions in half duplex mode (CSMA/CD protocol)
Automatic 32-bit CRC generation and checking
Preamble generation and removal
Complete status for TX/RX packets
IEEE 802.3 Media Independent Interface (MII)
WISHBONE SoC Interconnection Rev. B compliant interface
Figure 1: Core Architecture Overview
General Description
Architecture
Adjoining figure shows the general architecture of the Ethernet IP core. It consists of several building blocks:
TX Ethernet MAC (transmit function) block with the CRC generator
RX Ethernet MAC (receive function) block with the CRC generator
MAC control block
Management block (MIIM)
Host interface
TX and RX Modules
The TX and RX modules provide full transmit and receive functionality. CRC generators are incorporated in both modules for error detection purposes. The modules also handle preamble generation and removal. Padding occurs automatically (when enabled) in compliance with the IEEE 802.3 standard. When enabled, packets greater than the standard can be transmitted.
Control Module
The control module provides full duplex flow control, according to the IEEE 802.3u standard. Flow control is achieved by transfering the PAUSE control frames between the communicating stations.
Management Module (MIIM)
The management module provides the standard IEEE 802.3 Media Independent Interface (MII) that defines the connection between the PHY and link layers. Using this interface, the device (RISC) connected to the host interface can force PHY to run at 10 Mbps versus 100 Mbps or to configure it to run at full versus half duplex mode.
WISHBONE Interface
The WISHBONE interface connects the Ethernet core to the RISC and to external memory. The core is WISHBONE SoC Interconnection specification Rev. B compliant. The implementation realizes a 32-bit bus width and does not support other bus widths.
Utilization
The table in this section lists the intended applications of the different cores.
TechnologyAreaSilicon AreaSpeedPower ConsumptionXilinx Virtex2600 slices100000 gates60 MHz (25 needed)TBD
OpenCores reserves the right to make changes in specifications at any time and without notice. The information furnished by OpenCores in this publication is believed to be accurate and reliable. No responsibility, however, is assumed by OpenCores for its use, nor for any infringements of patents or other rights of third parties resulting from its use. This product is intended for use in normal commercial applications. Use of this product in applications such as life-support or life-sustaining equipment is at your own risc.
(footnote continued)
OpenCores
PAGE
PAGE 2
Ethernet IP Core
OpenCores
Ethernet IP Core
EMBED Visio.Drawing.6
EMBED CorelDraw.Graphic.7
# $ 2 L $ % ¤ Ń ă O
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