//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth_registers.v ////
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//// eth_registers.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// Copyright (C) 2001, 2002 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.24 2002/11/22 01:57:06 mohor
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// Revision 1.24 2002/11/22 01:57:06 mohor
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
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// synchronized.
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// synchronized.
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//
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//
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// Revision 1.23 2002/11/19 18:13:49 mohor
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// Revision 1.23 2002/11/19 18:13:49 mohor
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// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
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// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
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//
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//
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// Revision 1.22 2002/11/14 18:37:20 mohor
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// Revision 1.22 2002/11/14 18:37:20 mohor
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// r_Rst signal does not reset any module any more and is removed from the design.
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// r_Rst signal does not reset any module any more and is removed from the design.
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//
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//
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// Revision 1.21 2002/09/10 10:35:23 mohor
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// Revision 1.21 2002/09/10 10:35:23 mohor
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// Ethernet debug registers removed.
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// Ethernet debug registers removed.
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//
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//
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// Revision 1.20 2002/09/04 18:40:25 mohor
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// Revision 1.20 2002/09/04 18:40:25 mohor
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// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
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// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
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// the control frames connected.
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// the control frames connected.
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//
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//
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// Revision 1.19 2002/08/19 16:01:40 mohor
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// Revision 1.19 2002/08/19 16:01:40 mohor
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// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
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// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
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// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
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// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
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//
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//
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// Revision 1.18 2002/08/16 22:28:23 mohor
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// Revision 1.18 2002/08/16 22:28:23 mohor
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// Syntax error fixed.
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// Syntax error fixed.
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//
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//
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// Revision 1.17 2002/08/16 22:23:03 mohor
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// Revision 1.17 2002/08/16 22:23:03 mohor
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// Syntax error fixed.
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// Syntax error fixed.
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//
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//
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// Revision 1.16 2002/08/16 22:14:22 mohor
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// Revision 1.16 2002/08/16 22:14:22 mohor
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// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
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// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
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// changed from bit position 10 to 9.
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// changed from bit position 10 to 9.
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//
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//
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// Revision 1.15 2002/08/14 18:26:37 mohor
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// Revision 1.15 2002/08/14 18:26:37 mohor
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// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
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// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
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//
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//
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// Revision 1.14 2002/04/22 14:03:44 mohor
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// Revision 1.14 2002/04/22 14:03:44 mohor
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// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
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// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
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// or not.
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// or not.
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//
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//
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// Revision 1.13 2002/02/26 16:18:09 mohor
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// Revision 1.13 2002/02/26 16:18:09 mohor
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// Reset values are passed to registers through parameters
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// Reset values are passed to registers through parameters
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//
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//
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// Revision 1.12 2002/02/17 13:23:42 mohor
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// Revision 1.12 2002/02/17 13:23:42 mohor
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// Define missmatch fixed.
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// Define missmatch fixed.
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//
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//
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// Revision 1.11 2002/02/16 14:03:44 mohor
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// Revision 1.11 2002/02/16 14:03:44 mohor
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// Registered trimmed. Unused registers removed.
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// Registered trimmed. Unused registers removed.
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//
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//
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// Revision 1.10 2002/02/15 11:08:25 mohor
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// Revision 1.10 2002/02/15 11:08:25 mohor
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// File format fixed a bit.
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// File format fixed a bit.
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//
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//
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// Revision 1.9 2002/02/14 20:19:41 billditt
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// Revision 1.9 2002/02/14 20:19:41 billditt
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// Modified for Address Checking,
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// Modified for Address Checking,
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// addition of eth_addrcheck.v
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// addition of eth_addrcheck.v
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//
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//
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// Revision 1.8 2002/02/12 17:01:19 mohor
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// Revision 1.8 2002/02/12 17:01:19 mohor
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// HASH0 and HASH1 registers added.
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// HASH0 and HASH1 registers added.
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|
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// Revision 1.7 2002/01/23 10:28:16 mohor
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// Revision 1.7 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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// Link in the header changed.
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//
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//
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// Revision 1.6 2001/12/05 15:00:16 mohor
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// Revision 1.6 2001/12/05 15:00:16 mohor
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// instead of the number of RX descriptors).
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// instead of the number of RX descriptors).
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//
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//
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// Revision 1.5 2001/12/05 10:22:19 mohor
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// Revision 1.5 2001/12/05 10:22:19 mohor
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// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
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// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
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//
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//
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// Revision 1.4 2001/10/19 08:43:51 mohor
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// Revision 1.4 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Status signals changed, Adress decoding changed, interrupt controller
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// Status signals changed, Adress decoding changed, interrupt controller
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// added.
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// added.
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//
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//
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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// demands).
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//
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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// is done due to the ASIC tools.
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//
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//
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Unconnected signals are now connected.
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// Unconnected signals are now connected.
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//
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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|
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`include "eth_defines.v"
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
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r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
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r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
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StartTxDone, TxClk, RxClk, SetPauseTimer
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StartTxDone, TxClk, RxClk, SetPauseTimer
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input [31:0] DataIn;
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input [31:0] DataIn;
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input [7:0] Address;
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input [7:0] Address;
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input Rw;
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input Rw;
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input Cs;
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input Cs;
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input Clk;
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input Clk;
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input Reset;
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input Reset;
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input WCtrlDataStart;
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input WCtrlDataStart;
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input RStatStart;
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input RStatStart;
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input UpdateMIIRX_DATAReg;
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input UpdateMIIRX_DATAReg;
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input [15:0] Prsd;
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input [15:0] Prsd;
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output [31:0] DataOut;
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output [31:0] DataOut;
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reg [31:0] DataOut;
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reg [31:0] DataOut;
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output r_RecSmall;
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output r_RecSmall;
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output r_Pad;
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output r_Pad;
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output r_HugEn;
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output r_HugEn;
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output r_CrcEn;
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output r_CrcEn;
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output r_DlyCrcEn;
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output r_DlyCrcEn;
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output r_FullD;
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output r_FullD;
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output r_ExDfrEn;
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output r_ExDfrEn;
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output r_NoBckof;
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output r_NoBckof;
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output r_LoopBck;
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output r_LoopBck;
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output r_IFG;
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output r_IFG;
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output r_Pro;
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output r_Pro;
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output r_Iam;
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output r_Iam;
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output r_Bro;
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output r_Bro;
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output r_NoPre;
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output r_NoPre;
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output r_TxEn;
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output r_TxEn;
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output r_RxEn;
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output r_RxEn;
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output [31:0] r_HASH0;
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output [31:0] r_HASH0;
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output [31:0] r_HASH1;
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output [31:0] r_HASH1;
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input TxB_IRQ;
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input TxB_IRQ;
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input TxE_IRQ;
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input TxE_IRQ;
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input RxB_IRQ;
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input RxB_IRQ;
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input RxE_IRQ;
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input RxE_IRQ;
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input Busy_IRQ;
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input Busy_IRQ;
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output [6:0] r_IPGT;
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output [6:0] r_IPGT;
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output [6:0] r_IPGR1;
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output [6:0] r_IPGR1;
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output [6:0] r_IPGR2;
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output [6:0] r_IPGR2;
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output [15:0] r_MinFL;
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output [15:0] r_MinFL;
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output [15:0] r_MaxFL;
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output [15:0] r_MaxFL;
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output [3:0] r_MaxRet;
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output [3:0] r_MaxRet;
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output [5:0] r_CollValid;
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output [5:0] r_CollValid;
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output r_TxFlow;
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output r_TxFlow;
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output r_RxFlow;
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output r_RxFlow;
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output r_PassAll;
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output r_PassAll;
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|
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output r_MiiNoPre;
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output r_MiiNoPre;
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output [7:0] r_ClkDiv;
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output [7:0] r_ClkDiv;
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|
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output r_WCtrlData;
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output r_WCtrlData;
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output r_RStat;
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output r_RStat;
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output r_ScanStat;
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output r_ScanStat;
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|
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output [4:0] r_RGAD;
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output [4:0] r_RGAD;
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output [4:0] r_FIAD;
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output [4:0] r_FIAD;
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|
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output [15:0]r_CtrlData;
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output [15:0]r_CtrlData;
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|
|
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input NValid_stat;
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input NValid_stat;
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input Busy_stat;
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input Busy_stat;
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input LinkFail;
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input LinkFail;
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|
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output [47:0]r_MAC;
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output [47:0]r_MAC;
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output [7:0] r_TxBDNum;
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output [7:0] r_TxBDNum;
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output TX_BD_NUM_Wr;
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output TX_BD_NUM_Wr;
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output int_o;
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output int_o;
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output [15:0]r_TxPauseTV;
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output [15:0]r_TxPauseTV;
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output r_TxPauseRq;
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output r_TxPauseRq;
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input RstTxPauseRq;
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input RstTxPauseRq;
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input TxCtrlEndFrm;
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input TxCtrlEndFrm;
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input StartTxDone;
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input StartTxDone;
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input TxClk;
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input TxClk;
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input RxClk;
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input RxClk;
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input SetPauseTimer;
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input SetPauseTimer;
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|
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reg irq_txb;
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reg irq_txb;
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reg irq_txe;
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reg irq_txe;
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reg irq_rxb;
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reg irq_rxb;
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reg irq_rxe;
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reg irq_rxe;
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reg irq_busy;
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reg irq_busy;
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reg irq_txc;
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reg irq_txc;
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reg irq_rxc;
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reg irq_rxc;
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|
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reg SetTxCIrq_txclk;
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reg SetTxCIrq_txclk;
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reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
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reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
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reg SetTxCIrq;
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reg SetTxCIrq;
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reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
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reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
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|
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reg SetRxCIrq_rxclk;
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reg SetRxCIrq_rxclk;
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reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
|
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
|
reg SetRxCIrq;
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reg SetRxCIrq;
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reg ResetRxCIrq_sync1;
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reg ResetRxCIrq_sync1;
|
reg ResetRxCIrq_sync2;
|
reg ResetRxCIrq_sync2;
|
reg ResetRxCIrq_sync3;
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reg ResetRxCIrq_sync3;
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|
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wire Write = Cs & Rw;
|
wire Write = Cs & Rw;
|
wire Read = Cs & ~Rw;
|
wire Read = Cs & ~Rw;
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|
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wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
|
wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
|
wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR ) & Write;
|
wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR ) & Write;
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wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR ) & Write;
|
wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR ) & Write;
|
wire IPGT_Wr = (Address == `ETH_IPGT_ADR ) & Write;
|
wire IPGT_Wr = (Address == `ETH_IPGT_ADR ) & Write;
|
wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR ) & Write;
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wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR ) & Write;
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wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR ) & Write;
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wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR ) & Write;
|
wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR ) & Write;
|
wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR ) & Write;
|
wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR ) & Write;
|
wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR ) & Write;
|
|
|
wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR ) & Write;
|
wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR ) & Write;
|
wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR ) & Write;
|
wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR ) & Write;
|
wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR ) & Write;
|
wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR ) & Write;
|
wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR ) & Write;
|
wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR ) & Write;
|
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
|
wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
|
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
|
wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
|
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
|
wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
|
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
|
wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
|
wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
|
wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
|
wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
|
wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
|
wire TXCTRL_Wr = (Address == `ETH_TX_CTRL_ADR ) & Write;
|
wire TXCTRL_Wr = (Address == `ETH_TX_CTRL_ADR ) & Write;
|
wire RXCTRL_Wr = (Address == `ETH_RX_CTRL_ADR ) & Write;
|
wire RXCTRL_Wr = (Address == `ETH_RX_CTRL_ADR ) & Write;
|
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write & (DataIn<='h80);
|
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write & (DataIn<='h80);
|
|
|
|
|
|
|
wire [31:0] MODEROut;
|
wire [31:0] MODEROut;
|
wire [31:0] INT_SOURCEOut;
|
wire [31:0] INT_SOURCEOut;
|
wire [31:0] INT_MASKOut;
|
wire [31:0] INT_MASKOut;
|
wire [31:0] IPGTOut;
|
wire [31:0] IPGTOut;
|
wire [31:0] IPGR1Out;
|
wire [31:0] IPGR1Out;
|
wire [31:0] IPGR2Out;
|
wire [31:0] IPGR2Out;
|
wire [31:0] PACKETLENOut;
|
wire [31:0] PACKETLENOut;
|
wire [31:0] COLLCONFOut;
|
wire [31:0] COLLCONFOut;
|
wire [31:0] CTRLMODEROut;
|
wire [31:0] CTRLMODEROut;
|
wire [31:0] MIIMODEROut;
|
wire [31:0] MIIMODEROut;
|
wire [31:0] MIICOMMANDOut;
|
wire [31:0] MIICOMMANDOut;
|
wire [31:0] MIIADDRESSOut;
|
wire [31:0] MIIADDRESSOut;
|
wire [31:0] MIITX_DATAOut;
|
wire [31:0] MIITX_DATAOut;
|
wire [31:0] MIIRX_DATAOut;
|
wire [31:0] MIIRX_DATAOut;
|
wire [31:0] MIISTATUSOut;
|
wire [31:0] MIISTATUSOut;
|
wire [31:0] MAC_ADDR0Out;
|
wire [31:0] MAC_ADDR0Out;
|
wire [31:0] MAC_ADDR1Out;
|
wire [31:0] MAC_ADDR1Out;
|
wire [31:0] TX_BD_NUMOut;
|
wire [31:0] TX_BD_NUMOut;
|
wire [31:0] HASH0Out;
|
wire [31:0] HASH0Out;
|
wire [31:0] HASH1Out;
|
wire [31:0] HASH1Out;
|
wire [31:0] TXCTRLOut;
|
wire [31:0] TXCTRLOut;
|
wire [31:0] RXCTRLOut;
|
wire [31:0] RXCTRLOut;
|
|
|
// MODER Register
|
// MODER Register
|
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF) MODER
|
eth_register #(`ETH_MODER_WIDTH, `ETH_MODER_DEF) MODER
|
(
|
(
|
.DataIn (DataIn[`ETH_MODER_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_MODER_WIDTH-1:0]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH-1:0]),
|
.DataOut (MODEROut[`ETH_MODER_WIDTH-1:0]),
|
.Write (MODER_Wr),
|
.Write (MODER_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
|
assign MODEROut[31:`ETH_MODER_WIDTH] = 0;
|
|
|
// INT_MASK Register
|
// INT_MASK Register
|
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF) INT_MASK
|
eth_register #(`ETH_INT_MASK_WIDTH, `ETH_INT_MASK_DEF) INT_MASK
|
(
|
(
|
.DataIn (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_INT_MASK_WIDTH-1:0]),
|
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
|
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH-1:0]),
|
.Write (INT_MASK_Wr),
|
.Write (INT_MASK_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH] = 0;
|
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH] = 0;
|
|
|
// IPGT Register
|
// IPGT Register
|
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF) IPGT
|
eth_register #(`ETH_IPGT_WIDTH, `ETH_IPGT_DEF) IPGT
|
(
|
(
|
.DataIn (DataIn[`ETH_IPGT_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_IPGT_WIDTH-1:0]),
|
.DataOut (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
|
.DataOut (IPGTOut[`ETH_IPGT_WIDTH-1:0]),
|
.Write (IPGT_Wr),
|
.Write (IPGT_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
|
assign IPGTOut[31:`ETH_IPGT_WIDTH] = 0;
|
|
|
// IPGR1 Register
|
// IPGR1 Register
|
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF) IPGR1
|
eth_register #(`ETH_IPGR1_WIDTH, `ETH_IPGR1_DEF) IPGR1
|
(
|
(
|
.DataIn (DataIn[`ETH_IPGR1_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_IPGR1_WIDTH-1:0]),
|
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
|
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH-1:0]),
|
.Write (IPGR1_Wr),
|
.Write (IPGR1_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
|
assign IPGR1Out[31:`ETH_IPGR1_WIDTH] = 0;
|
|
|
// IPGR2 Register
|
// IPGR2 Register
|
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF) IPGR2
|
eth_register #(`ETH_IPGR2_WIDTH, `ETH_IPGR2_DEF) IPGR2
|
(
|
(
|
.DataIn (DataIn[`ETH_IPGR2_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_IPGR2_WIDTH-1:0]),
|
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
|
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH-1:0]),
|
.Write (IPGR2_Wr),
|
.Write (IPGR2_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
|
assign IPGR2Out[31:`ETH_IPGR2_WIDTH] = 0;
|
|
|
// PACKETLEN Register
|
// PACKETLEN Register
|
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
|
eth_register #(`ETH_PACKETLEN_WIDTH, `ETH_PACKETLEN_DEF) PACKETLEN
|
(
|
(
|
.DataIn (DataIn),
|
.DataIn (DataIn),
|
.DataOut (PACKETLENOut),
|
.DataOut (PACKETLENOut),
|
.Write (PACKETLEN_Wr),
|
.Write (PACKETLEN_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// COLLCONF Register
|
// COLLCONF Register
|
eth_register #(6, `ETH_COLLCONF0_DEF) COLLCONF0
|
eth_register #(6, `ETH_COLLCONF0_DEF) COLLCONF0
|
(
|
(
|
.DataIn (DataIn[5:0]),
|
.DataIn (DataIn[5:0]),
|
.DataOut (COLLCONFOut[5:0]),
|
.DataOut (COLLCONFOut[5:0]),
|
.Write (COLLCONF_Wr),
|
.Write (COLLCONF_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign COLLCONFOut[15:6] = 0;
|
assign COLLCONFOut[15:6] = 0;
|
|
|
eth_register #(4, `ETH_COLLCONF1_DEF) COLLCONF1
|
eth_register #(4, `ETH_COLLCONF1_DEF) COLLCONF1
|
(
|
(
|
.DataIn (DataIn[19:16]),
|
.DataIn (DataIn[19:16]),
|
.DataOut (COLLCONFOut[19:16]),
|
.DataOut (COLLCONFOut[19:16]),
|
.Write (COLLCONF_Wr),
|
.Write (COLLCONF_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign COLLCONFOut[31:20] = 0;
|
assign COLLCONFOut[31:20] = 0;
|
|
|
// TX_BD_NUM Register
|
// TX_BD_NUM Register
|
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
|
eth_register #(`ETH_TX_BD_NUM_WIDTH, `ETH_TX_BD_NUM_DEF) TX_BD_NUM
|
(
|
(
|
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH-1:0]),
|
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
|
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH-1:0]),
|
.Write (TX_BD_NUM_Wr),
|
.Write (TX_BD_NUM_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
|
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH] = 0;
|
|
|
// CTRLMODER Register
|
// CTRLMODER Register
|
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF) CTRLMODER2
|
eth_register #(`ETH_CTRLMODER_WIDTH, `ETH_CTRLMODER_DEF) CTRLMODER2
|
(
|
(
|
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH-1:0]),
|
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
|
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH-1:0]),
|
.Write (CTRLMODER_Wr),
|
.Write (CTRLMODER_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
|
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH] = 0;
|
|
|
// MIIMODER Register
|
// MIIMODER Register
|
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF) MIIMODER
|
eth_register #(`ETH_MIIMODER_WIDTH, `ETH_MIIMODER_DEF) MIIMODER
|
(
|
(
|
.DataIn (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_MIIMODER_WIDTH-1:0]),
|
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
|
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH-1:0]),
|
.Write (MIIMODER_Wr),
|
.Write (MIIMODER_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
|
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH] = 0;
|
|
|
// MIICOMMAND Register
|
// MIICOMMAND Register
|
eth_register #(1, 0) MIICOMMAND0
|
eth_register #(1, 0) MIICOMMAND0
|
(
|
(
|
.DataIn (DataIn[0]),
|
.DataIn (DataIn[0]),
|
.DataOut (MIICOMMANDOut[0]),
|
.DataOut (MIICOMMANDOut[0]),
|
.Write (MIICOMMAND_Wr),
|
.Write (MIICOMMAND_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
eth_register #(1, 0) MIICOMMAND1
|
eth_register #(1, 0) MIICOMMAND1
|
(
|
(
|
.DataIn (DataIn[1]),
|
.DataIn (DataIn[1]),
|
.DataOut (MIICOMMANDOut[1]),
|
.DataOut (MIICOMMANDOut[1]),
|
.Write (MIICOMMAND_Wr),
|
.Write (MIICOMMAND_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (RStatStart)
|
.SyncReset (RStatStart)
|
);
|
);
|
|
|
eth_register #(1, 0) MIICOMMAND2
|
eth_register #(1, 0) MIICOMMAND2
|
(
|
(
|
.DataIn (DataIn[2]),
|
.DataIn (DataIn[2]),
|
.DataOut (MIICOMMANDOut[2]),
|
.DataOut (MIICOMMANDOut[2]),
|
.Write (MIICOMMAND_Wr),
|
.Write (MIICOMMAND_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (WCtrlDataStart)
|
.SyncReset (WCtrlDataStart)
|
);
|
);
|
assign MIICOMMANDOut[31:3] = 29'h0;
|
assign MIICOMMANDOut[31:3] = 29'h0;
|
|
|
// MIIADDRESSRegister
|
// MIIADDRESSRegister
|
eth_register #(5, `ETH_MIIADDRESS0_DEF) MIIADDRESS0
|
eth_register #(5, `ETH_MIIADDRESS0_DEF) MIIADDRESS0
|
(
|
(
|
.DataIn (DataIn[4:0]),
|
.DataIn (DataIn[4:0]),
|
.DataOut (MIIADDRESSOut[4:0]),
|
.DataOut (MIIADDRESSOut[4:0]),
|
.Write (MIIADDRESS_Wr),
|
.Write (MIIADDRESS_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIADDRESSOut[7:5] = 0;
|
assign MIIADDRESSOut[7:5] = 0;
|
|
|
eth_register #(5, `ETH_MIIADDRESS1_DEF) MIIADDRESS1
|
eth_register #(5, `ETH_MIIADDRESS1_DEF) MIIADDRESS1
|
(
|
(
|
.DataIn (DataIn[12:8]),
|
.DataIn (DataIn[12:8]),
|
.DataOut (MIIADDRESSOut[12:8]),
|
.DataOut (MIIADDRESSOut[12:8]),
|
.Write (MIIADDRESS_Wr),
|
.Write (MIIADDRESS_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIADDRESSOut[31:13] = 0;
|
assign MIIADDRESSOut[31:13] = 0;
|
|
|
// MIITX_DATA Register
|
// MIITX_DATA Register
|
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
|
eth_register #(`ETH_MIITX_DATA_WIDTH, `ETH_MIITX_DATA_DEF) MIITX_DATA
|
(
|
(
|
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH-1:0]),
|
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
|
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH-1:0]),
|
.Write (MIITX_DATA_Wr),
|
.Write (MIITX_DATA_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
|
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH] = 0;
|
|
|
// MIIRX_DATA Register
|
// MIIRX_DATA Register
|
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
|
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
|
(
|
(
|
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
|
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
|
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
|
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
|
.Write (MIIRX_DATA_Wr),
|
.Write (MIIRX_DATA_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
|
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
|
|
|
// MAC_ADDR0 Register
|
// MAC_ADDR0 Register
|
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF) MAC_ADDR0
|
eth_register #(`ETH_MAC_ADDR0_WIDTH, `ETH_MAC_ADDR0_DEF) MAC_ADDR0
|
(
|
(
|
.DataIn (DataIn),
|
.DataIn (DataIn),
|
.DataOut (MAC_ADDR0Out),
|
.DataOut (MAC_ADDR0Out),
|
.Write (MAC_ADDR0_Wr),
|
.Write (MAC_ADDR0_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// MAC_ADDR1 Register
|
// MAC_ADDR1 Register
|
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF) MAC_ADDR1
|
eth_register #(`ETH_MAC_ADDR1_WIDTH, `ETH_MAC_ADDR1_DEF) MAC_ADDR1
|
(
|
(
|
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH-1:0]),
|
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
|
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH-1:0]),
|
.Write (MAC_ADDR1_Wr),
|
.Write (MAC_ADDR1_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
|
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH] = 0;
|
|
|
// RXHASH0 Register
|
// RXHASH0 Register
|
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF) RXHASH0
|
eth_register #(`ETH_HASH0_WIDTH, `ETH_HASH0_DEF) RXHASH0
|
(
|
(
|
.DataIn (DataIn),
|
.DataIn (DataIn),
|
.DataOut (HASH0Out),
|
.DataOut (HASH0Out),
|
.Write (HASH0_Wr),
|
.Write (HASH0_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
// RXHASH1 Register
|
// RXHASH1 Register
|
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF) RXHASH1
|
eth_register #(`ETH_HASH1_WIDTH, `ETH_HASH1_DEF) RXHASH1
|
(
|
(
|
.DataIn (DataIn),
|
.DataIn (DataIn),
|
.DataOut (HASH1Out),
|
.DataOut (HASH1Out),
|
.Write (HASH1_Wr),
|
.Write (HASH1_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
|
|
// TXCTRL Register
|
// TXCTRL Register
|
eth_register #((`ETH_TX_CTRL_WIDTH-1), {(`ETH_TX_CTRL_WIDTH-1){1'b0}}) TXCTRL0
|
eth_register #((`ETH_TX_CTRL_WIDTH-1), {(`ETH_TX_CTRL_WIDTH-1){1'b0}}) TXCTRL0
|
(
|
(
|
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH-2:0]),
|
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH-2:0]),
|
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH-2:0]),
|
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH-2:0]),
|
.Write (TXCTRL_Wr),
|
.Write (TXCTRL_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
|
|
eth_register #(1, 1'b0) TXCTRL1 // Request bit is synchronously reset
|
eth_register #(1, 1'b0) TXCTRL1 // Request bit is synchronously reset
|
(
|
(
|
.DataIn (DataIn[16]),
|
.DataIn (DataIn[16]),
|
.DataOut (TXCTRLOut[16]),
|
.DataOut (TXCTRLOut[16]),
|
.Write (TXCTRL_Wr),
|
.Write (TXCTRL_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (RstTxPauseRq)
|
.SyncReset (RstTxPauseRq)
|
);
|
);
|
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH] = 0;
|
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH] = 0;
|
|
|
|
|
// RXCTRL Register
|
// RXCTRL Register
|
eth_register #(`ETH_RX_CTRL_WIDTH, `ETH_RX_CTRL_DEF) RXCTRL
|
eth_register #(`ETH_RX_CTRL_WIDTH, `ETH_RX_CTRL_DEF) RXCTRL
|
(
|
(
|
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH-1:0]),
|
.DataIn (DataIn[`ETH_RX_CTRL_WIDTH-1:0]),
|
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH-1:0]),
|
.DataOut (RXCTRLOut[`ETH_RX_CTRL_WIDTH-1:0]),
|
.Write (RXCTRL_Wr),
|
.Write (RXCTRL_Wr),
|
.Clk (Clk),
|
.Clk (Clk),
|
.Reset (Reset),
|
.Reset (Reset),
|
.SyncReset (1'b0)
|
.SyncReset (1'b0)
|
);
|
);
|
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH] = 0;
|
assign RXCTRLOut[31:`ETH_RX_CTRL_WIDTH] = 0;
|
|
|
|
|
// Reading data from registers
|
// Reading data from registers
|
always @ (Address or Read or MODEROut or INT_SOURCEOut or
|
always @ (Address or Read or MODEROut or INT_SOURCEOut or
|
INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
|
INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
|
PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
|
PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
|
MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
|
MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
|
MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
|
MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
|
HASH0Out or HASH1Out or TXCTRLOut or RXCTRLOut
|
HASH0Out or HASH1Out or TXCTRLOut or RXCTRLOut
|
)
|
)
|
begin
|
begin
|
if(Read) // read
|
if(Read) // read
|
begin
|
begin
|
case(Address)
|
case(Address)
|
`ETH_MODER_ADR : DataOut<=MODEROut;
|
`ETH_MODER_ADR : DataOut<=MODEROut;
|
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
|
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
|
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
|
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
|
`ETH_IPGT_ADR : DataOut<=IPGTOut;
|
`ETH_IPGT_ADR : DataOut<=IPGTOut;
|
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
|
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
|
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
|
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
|
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
|
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
|
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
|
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
|
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
|
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
|
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
|
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
|
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
|
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
|
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
|
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
|
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
|
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
|
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
|
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
|
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
|
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
|
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
|
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
|
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
|
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
|
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
|
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
|
`ETH_HASH0_ADR : DataOut<=HASH0Out;
|
`ETH_HASH0_ADR : DataOut<=HASH0Out;
|
`ETH_HASH1_ADR : DataOut<=HASH1Out;
|
`ETH_HASH1_ADR : DataOut<=HASH1Out;
|
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
|
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
|
`ETH_RX_CTRL_ADR : DataOut<=RXCTRLOut;
|
`ETH_RX_CTRL_ADR : DataOut<=RXCTRLOut;
|
|
|
default: DataOut<=32'h0;
|
default: DataOut<=32'h0;
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
DataOut<=32'h0;
|
DataOut<=32'h0;
|
end
|
end
|
|
|
|
|
assign r_RecSmall = MODEROut[16];
|
assign r_RecSmall = MODEROut[16];
|
assign r_Pad = MODEROut[15];
|
assign r_Pad = MODEROut[15];
|
assign r_HugEn = MODEROut[14];
|
assign r_HugEn = MODEROut[14];
|
assign r_CrcEn = MODEROut[13];
|
assign r_CrcEn = MODEROut[13];
|
assign r_DlyCrcEn = MODEROut[12];
|
assign r_DlyCrcEn = MODEROut[12];
|
// assign r_Rst = MODEROut[11]; This signal is not used any more
|
// assign r_Rst = MODEROut[11]; This signal is not used any more
|
assign r_FullD = MODEROut[10];
|
assign r_FullD = MODEROut[10];
|
assign r_ExDfrEn = MODEROut[9];
|
assign r_ExDfrEn = MODEROut[9];
|
assign r_NoBckof = MODEROut[8];
|
assign r_NoBckof = MODEROut[8];
|
assign r_LoopBck = MODEROut[7];
|
assign r_LoopBck = MODEROut[7];
|
assign r_IFG = MODEROut[6];
|
assign r_IFG = MODEROut[6];
|
assign r_Pro = MODEROut[5];
|
assign r_Pro = MODEROut[5];
|
assign r_Iam = MODEROut[4];
|
assign r_Iam = MODEROut[4];
|
assign r_Bro = MODEROut[3];
|
assign r_Bro = MODEROut[3];
|
assign r_NoPre = MODEROut[2];
|
assign r_NoPre = MODEROut[2];
|
assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD.
|
assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD.
|
assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD.
|
assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD.
|
|
|
assign r_IPGT[6:0] = IPGTOut[6:0];
|
assign r_IPGT[6:0] = IPGTOut[6:0];
|
|
|
assign r_IPGR1[6:0] = IPGR1Out[6:0];
|
assign r_IPGR1[6:0] = IPGR1Out[6:0];
|
|
|
assign r_IPGR2[6:0] = IPGR2Out[6:0];
|
assign r_IPGR2[6:0] = IPGR2Out[6:0];
|
|
|
assign r_MinFL[15:0] = PACKETLENOut[31:16];
|
assign r_MinFL[15:0] = PACKETLENOut[31:16];
|
assign r_MaxFL[15:0] = PACKETLENOut[15:0];
|
assign r_MaxFL[15:0] = PACKETLENOut[15:0];
|
|
|
assign r_MaxRet[3:0] = COLLCONFOut[19:16];
|
assign r_MaxRet[3:0] = COLLCONFOut[19:16];
|
assign r_CollValid[5:0] = COLLCONFOut[5:0];
|
assign r_CollValid[5:0] = COLLCONFOut[5:0];
|
|
|
assign r_TxFlow = CTRLMODEROut[2];
|
assign r_TxFlow = CTRLMODEROut[2];
|
assign r_RxFlow = CTRLMODEROut[1];
|
assign r_RxFlow = CTRLMODEROut[1];
|
assign r_PassAll = CTRLMODEROut[0];
|
assign r_PassAll = CTRLMODEROut[0];
|
|
|
assign r_MiiNoPre = MIIMODEROut[8];
|
assign r_MiiNoPre = MIIMODEROut[8];
|
assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
|
assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
|
|
|
assign r_WCtrlData = MIICOMMANDOut[2];
|
assign r_WCtrlData = MIICOMMANDOut[2];
|
assign r_RStat = MIICOMMANDOut[1];
|
assign r_RStat = MIICOMMANDOut[1];
|
assign r_ScanStat = MIICOMMANDOut[0];
|
assign r_ScanStat = MIICOMMANDOut[0];
|
|
|
assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
|
assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
|
assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
|
assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
|
|
|
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
|
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
|
|
|
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
|
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
|
assign MIISTATUSOut[2] = NValid_stat ;
|
assign MIISTATUSOut[2] = NValid_stat ;
|
assign MIISTATUSOut[1] = Busy_stat ;
|
assign MIISTATUSOut[1] = Busy_stat ;
|
assign MIISTATUSOut[0] = LinkFail ;
|
assign MIISTATUSOut[0] = LinkFail ;
|
|
|
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
|
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
|
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
|
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
|
assign r_HASH1[31:0] = HASH1Out;
|
assign r_HASH1[31:0] = HASH1Out;
|
assign r_HASH0[31:0] = HASH0Out;
|
assign r_HASH0[31:0] = HASH0Out;
|
|
|
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
|
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
|
|
|
assign r_TxPauseTV[15:0] = TXCTRLOut[15:0];
|
assign r_TxPauseTV[15:0] = TXCTRLOut[15:0];
|
assign r_TxPauseRq = TXCTRLOut[16];
|
assign r_TxPauseRq = TXCTRLOut[16];
|
|
|
|
|
// Synchronizing TxC Interrupt
|
// Synchronizing TxC Interrupt
|
always @ (posedge TxClk or posedge Reset)
|
always @ (posedge TxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetTxCIrq_txclk <=#Tp 1'b0;
|
SetTxCIrq_txclk <=#Tp 1'b0;
|
else
|
else
|
if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
|
if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
|
SetTxCIrq_txclk <=#Tp 1'b1;
|
SetTxCIrq_txclk <=#Tp 1'b1;
|
else
|
else
|
if(ResetTxCIrq_sync2)
|
if(ResetTxCIrq_sync2)
|
SetTxCIrq_txclk <=#Tp 1'b0;
|
SetTxCIrq_txclk <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetTxCIrq_sync1 <=#Tp 1'b0;
|
SetTxCIrq_sync1 <=#Tp 1'b0;
|
else
|
else
|
SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
|
SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetTxCIrq_sync2 <=#Tp 1'b0;
|
SetTxCIrq_sync2 <=#Tp 1'b0;
|
else
|
else
|
SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
|
SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetTxCIrq_sync3 <=#Tp 1'b0;
|
SetTxCIrq_sync3 <=#Tp 1'b0;
|
else
|
else
|
SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
|
SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetTxCIrq <=#Tp 1'b0;
|
SetTxCIrq <=#Tp 1'b0;
|
else
|
else
|
SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
|
SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
|
end
|
end
|
|
|
always @ (posedge TxClk or posedge Reset)
|
always @ (posedge TxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ResetTxCIrq_sync1 <=#Tp 1'b0;
|
ResetTxCIrq_sync1 <=#Tp 1'b0;
|
else
|
else
|
ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
|
ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
|
end
|
end
|
|
|
always @ (posedge TxClk or posedge Reset)
|
always @ (posedge TxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ResetTxCIrq_sync2 <=#Tp 1'b0;
|
ResetTxCIrq_sync2 <=#Tp 1'b0;
|
else
|
else
|
ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
|
ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
|
end
|
end
|
|
|
|
|
// Synchronizing RxC Interrupt
|
// Synchronizing RxC Interrupt
|
always @ (posedge RxClk or posedge Reset)
|
always @ (posedge RxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetRxCIrq_rxclk <=#Tp 1'b0;
|
SetRxCIrq_rxclk <=#Tp 1'b0;
|
else
|
else
|
if(SetPauseTimer & r_RxFlow)
|
if(SetPauseTimer & r_RxFlow)
|
SetRxCIrq_rxclk <=#Tp 1'b1;
|
SetRxCIrq_rxclk <=#Tp 1'b1;
|
else
|
else
|
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
|
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
|
SetRxCIrq_rxclk <=#Tp 1'b0;
|
SetRxCIrq_rxclk <=#Tp 1'b0;
|
end
|
end
|
|
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetRxCIrq_sync1 <=#Tp 1'b0;
|
SetRxCIrq_sync1 <=#Tp 1'b0;
|
else
|
else
|
SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
|
SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetRxCIrq_sync2 <=#Tp 1'b0;
|
SetRxCIrq_sync2 <=#Tp 1'b0;
|
else
|
else
|
SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
|
SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetRxCIrq_sync3 <=#Tp 1'b0;
|
SetRxCIrq_sync3 <=#Tp 1'b0;
|
else
|
else
|
SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
|
SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
SetRxCIrq <=#Tp 1'b0;
|
SetRxCIrq <=#Tp 1'b0;
|
else
|
else
|
SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
|
SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
|
end
|
end
|
|
|
always @ (posedge RxClk or posedge Reset)
|
always @ (posedge RxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ResetRxCIrq_sync1 <=#Tp 1'b0;
|
ResetRxCIrq_sync1 <=#Tp 1'b0;
|
else
|
else
|
ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
|
ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
|
end
|
end
|
|
|
always @ (posedge RxClk or posedge Reset)
|
always @ (posedge RxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ResetRxCIrq_sync2 <=#Tp 1'b0;
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ResetRxCIrq_sync2 <=#Tp 1'b0;
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else
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else
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ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
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ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
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end
|
end
|
|
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always @ (posedge RxClk or posedge Reset)
|
always @ (posedge RxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ResetRxCIrq_sync3 <=#Tp 1'b0;
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ResetRxCIrq_sync3 <=#Tp 1'b0;
|
else
|
else
|
ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
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ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
|
end
|
end
|
|
|
|
|
|
|
// Interrupt generation
|
// Interrupt generation
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_txb <= 1'b0;
|
irq_txb <= 1'b0;
|
else
|
else
|
if(TxB_IRQ)
|
if(TxB_IRQ)
|
irq_txb <= #Tp 1'b1;
|
irq_txb <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[0])
|
if(INT_SOURCE_Wr & DataIn[0])
|
irq_txb <= #Tp 1'b0;
|
irq_txb <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_txe <= 1'b0;
|
irq_txe <= 1'b0;
|
else
|
else
|
if(TxE_IRQ)
|
if(TxE_IRQ)
|
irq_txe <= #Tp 1'b1;
|
irq_txe <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[1])
|
if(INT_SOURCE_Wr & DataIn[1])
|
irq_txe <= #Tp 1'b0;
|
irq_txe <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_rxb <= 1'b0;
|
irq_rxb <= 1'b0;
|
else
|
else
|
if(RxB_IRQ)
|
if(RxB_IRQ)
|
irq_rxb <= #Tp 1'b1;
|
irq_rxb <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[2])
|
if(INT_SOURCE_Wr & DataIn[2])
|
irq_rxb <= #Tp 1'b0;
|
irq_rxb <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_rxe <= 1'b0;
|
irq_rxe <= 1'b0;
|
else
|
else
|
if(RxE_IRQ)
|
if(RxE_IRQ)
|
irq_rxe <= #Tp 1'b1;
|
irq_rxe <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[3])
|
if(INT_SOURCE_Wr & DataIn[3])
|
irq_rxe <= #Tp 1'b0;
|
irq_rxe <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_busy <= 1'b0;
|
irq_busy <= 1'b0;
|
else
|
else
|
if(Busy_IRQ)
|
if(Busy_IRQ)
|
irq_busy <= #Tp 1'b1;
|
irq_busy <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[4])
|
if(INT_SOURCE_Wr & DataIn[4])
|
irq_busy <= #Tp 1'b0;
|
irq_busy <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_txc <= 1'b0;
|
irq_txc <= 1'b0;
|
else
|
else
|
if(SetTxCIrq)
|
if(SetTxCIrq)
|
irq_txc <= #Tp 1'b1;
|
irq_txc <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[5])
|
if(INT_SOURCE_Wr & DataIn[5])
|
irq_txc <= #Tp 1'b0;
|
irq_txc <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_rxc <= 1'b0;
|
irq_rxc <= 1'b0;
|
else
|
else
|
if(SetRxCIrq)
|
if(SetRxCIrq)
|
irq_rxc <= #Tp 1'b1;
|
irq_rxc <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[6])
|
if(INT_SOURCE_Wr & DataIn[6])
|
irq_rxc <= #Tp 1'b0;
|
irq_rxc <= #Tp 1'b0;
|
end
|
end
|
|
|
// Generating interrupt signal
|
// Generating interrupt signal
|
assign int_o = irq_txb & INT_MASKOut[0] |
|
assign int_o = irq_txb & INT_MASKOut[0] |
|
irq_txe & INT_MASKOut[1] |
|
irq_txe & INT_MASKOut[1] |
|
irq_rxb & INT_MASKOut[2] |
|
irq_rxb & INT_MASKOut[2] |
|
irq_rxe & INT_MASKOut[3] |
|
irq_rxe & INT_MASKOut[3] |
|
irq_busy & INT_MASKOut[4] |
|
irq_busy & INT_MASKOut[4] |
|
irq_txc & INT_MASKOut[5] |
|
irq_txc & INT_MASKOut[5] |
|
irq_rxc & INT_MASKOut[6] ;
|
irq_rxc & INT_MASKOut[6] ;
|
|
|
// For reading interrupt status
|
// For reading interrupt status
|
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
|
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
|
|
|
|
|
|
|
endmodule
|
endmodule
|
|
|