[Library]
|
[Library]
|
std = $MODEL_TECH/../std
|
std = $MODEL_TECH/../std
|
ieee = $MODEL_TECH/../ieee
|
ieee = $MODEL_TECH/../ieee
|
verilog = $MODEL_TECH/../verilog
|
verilog = $MODEL_TECH/../verilog
|
vital2000 = $MODEL_TECH/../vital2000
|
vital2000 = $MODEL_TECH/../vital2000
|
std_developerskit = $MODEL_TECH/../std_developerskit
|
std_developerskit = $MODEL_TECH/../std_developerskit
|
synopsys = $MODEL_TECH/../synopsys
|
synopsys = $MODEL_TECH/../synopsys
|
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
|
|
work = work
|
work = work
|
[vcom]
|
[vcom]
|
; Turn on VHDL-1993 as the default. Default is off (VHDL-1987).
|
; Turn on VHDL-1993 as the default. Default is off (VHDL-1987).
|
; VHDL93 = 1
|
; VHDL93 = 1
|
|
|
; Show source line containing error. Default is off.
|
; Show source line containing error. Default is off.
|
; Show_source = 1
|
; Show_source = 1
|
|
|
; Turn off unbound-component warnings. Default is on.
|
; Turn off unbound-component warnings. Default is on.
|
; Show_Warning1 = 0
|
; Show_Warning1 = 0
|
|
|
; Turn off process-without-a-wait-statement warnings. Default is on.
|
; Turn off process-without-a-wait-statement warnings. Default is on.
|
; Show_Warning2 = 0
|
; Show_Warning2 = 0
|
|
|
; Turn off null-range warnings. Default is on.
|
; Turn off null-range warnings. Default is on.
|
; Show_Warning3 = 0
|
; Show_Warning3 = 0
|
|
|
; Turn off no-space-in-time-literal warnings. Default is on.
|
; Turn off no-space-in-time-literal warnings. Default is on.
|
; Show_Warning4 = 0
|
; Show_Warning4 = 0
|
|
|
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
; Show_Warning5 = 0
|
; Show_Warning5 = 0
|
|
|
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
; Optimize_1164 = 0
|
; Optimize_1164 = 0
|
|
|
; Turn on resolving of ambiguous function overloading in favor of the
|
; Turn on resolving of ambiguous function overloading in favor of the
|
; "explicit" function declaration (not the one automatically created by
|
; "explicit" function declaration (not the one automatically created by
|
; the compiler for each type declaration). Default is off.
|
; the compiler for each type declaration). Default is off.
|
; The .ini file has Explict enabled so that std_logic_signed/unsigned
|
; The .ini file has Explict enabled so that std_logic_signed/unsigned
|
; will match the behavior of synthesis tools.
|
; will match the behavior of synthesis tools.
|
Explicit = 1
|
Explicit = 1
|
|
|
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
; NoVital = 1
|
; NoVital = 1
|
|
|
; Turn off VITAL compliance checking. Default is checking on.
|
; Turn off VITAL compliance checking. Default is checking on.
|
; NoVitalCheck = 1
|
; NoVitalCheck = 1
|
|
|
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
; IgnoreVitalErrors = 1
|
; IgnoreVitalErrors = 1
|
|
|
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
; Show_VitalChecksWarnings = false
|
; Show_VitalChecksWarnings = false
|
|
|
; Keep silent about case statement static warnings.
|
; Keep silent about case statement static warnings.
|
; Default is to give a warning.
|
; Default is to give a warning.
|
; NoCaseStaticError = 1
|
; NoCaseStaticError = 1
|
|
|
; Keep silent about warnings caused by aggregates that are not locally static.
|
; Keep silent about warnings caused by aggregates that are not locally static.
|
; Default is to give a warning.
|
; Default is to give a warning.
|
; NoOthersStaticError = 1
|
; NoOthersStaticError = 1
|
|
|
; Treat as errors:
|
; Treat as errors:
|
; case statement static warnings
|
; case statement static warnings
|
; warnings caused by aggregates that are not locally static
|
; warnings caused by aggregates that are not locally static
|
; Overrides NoCaseStaticError, NoOthersStaticError settings.
|
; Overrides NoCaseStaticError, NoOthersStaticError settings.
|
; PedanticErrors = 1
|
; PedanticErrors = 1
|
|
|
; Turn off inclusion of debugging info within design units.
|
; Turn off inclusion of debugging info within design units.
|
; Default is to include debugging info.
|
; Default is to include debugging info.
|
; NoDebug = 1
|
; NoDebug = 1
|
|
|
; Turn off "loading..." messages. Default is messages on.
|
; Turn off "loading..." messages. Default is messages on.
|
; Quiet = 1
|
; Quiet = 1
|
|
|
; Turn on some limited synthesis rule compliance checking. Checks only:
|
; Turn on some limited synthesis rule compliance checking. Checks only:
|
; -- signals used (read) by a process must be in the sensitivity list
|
; -- signals used (read) by a process must be in the sensitivity list
|
; CheckSynthesis = 1
|
; CheckSynthesis = 1
|
|
|
; Activate optimizations on expressions that do not involve signals,
|
; Activate optimizations on expressions that do not involve signals,
|
; waits, or function/procedure/task invocations. Default is off.
|
; waits, or function/procedure/task invocations. Default is off.
|
; ScalarOpts = 1
|
; ScalarOpts = 1
|
|
|
; Require the user to specify a configuration for all bindings,
|
; Require the user to specify a configuration for all bindings,
|
; and do not generate a compile time default binding for the
|
; and do not generate a compile time default binding for the
|
; component. This will result in an elaboration error of
|
; component. This will result in an elaboration error of
|
; 'component not bound' if the user fails to do so. Avoids the rare
|
; 'component not bound' if the user fails to do so. Avoids the rare
|
; issue of a false dependency upon the unused default binding.
|
; issue of a false dependency upon the unused default binding.
|
; RequireConfigForAllDefaultBinding = 1
|
; RequireConfigForAllDefaultBinding = 1
|
|
|
; Inhibit range checking on subscripts of arrays. Range checking on
|
; Inhibit range checking on subscripts of arrays. Range checking on
|
; scalars defined with subtypes is inhibited by default.
|
; scalars defined with subtypes is inhibited by default.
|
; NoIndexCheck = 1
|
; NoIndexCheck = 1
|
|
|
; Inhibit range checks on all (implicit and explicit) assignments to
|
; Inhibit range checks on all (implicit and explicit) assignments to
|
; scalar objects defined with subtypes.
|
; scalar objects defined with subtypes.
|
; NoRangeCheck = 1
|
; NoRangeCheck = 1
|
|
|
VHDL93 = 0
|
VHDL93 = 0
|
NoDebug = 0
|
NoDebug = 0
|
CheckSynthesis = 0
|
CheckSynthesis = 0
|
NoVitalCheck = 0
|
NoVitalCheck = 0
|
Optimize_1164 = 1
|
Optimize_1164 = 1
|
NoVital = 0
|
NoVital = 0
|
Quiet = 0
|
Quiet = 0
|
Show_source = 0
|
Show_source = 0
|
Show_Warning1 = 1
|
Show_Warning1 = 1
|
Show_Warning2 = 1
|
Show_Warning2 = 1
|
Show_Warning3 = 1
|
Show_Warning3 = 1
|
Show_Warning4 = 1
|
Show_Warning4 = 1
|
Show_Warning5 = 1
|
Show_Warning5 = 1
|
[vlog]
|
[vlog]
|
|
|
; Turn off inclusion of debugging info within design units.
|
; Turn off inclusion of debugging info within design units.
|
; Default is to include debugging info.
|
; Default is to include debugging info.
|
; NoDebug = 1
|
; NoDebug = 1
|
|
|
; Turn off "loading..." messages. Default is messages on.
|
; Turn off "loading..." messages. Default is messages on.
|
; Quiet = 1
|
; Quiet = 1
|
|
|
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
; Default is off.
|
; Default is off.
|
; Hazard = 1
|
; Hazard = 1
|
|
|
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
; insensitivity for module names. Default is no conversion.
|
; insensitivity for module names. Default is no conversion.
|
; UpCase = 1
|
; UpCase = 1
|
|
|
; Turn on incremental compilation of modules. Default is off.
|
; Turn on incremental compilation of modules. Default is off.
|
; Incremental = 1
|
; Incremental = 1
|
|
|
; Activate optimizations on expressions that do not involve signals,
|
; Activate optimizations on expressions that do not involve signals,
|
; waits, or function/procedure/task invocations. Default is off.
|
; waits, or function/procedure/task invocations. Default is off.
|
; ScalarOpts = 1
|
; ScalarOpts = 1
|
|
|
; Turns on lint-style checking.
|
; Turns on lint-style checking.
|
; Show_Lint = 1
|
; Show_Lint = 1
|
|
|
; Show source line containing error. Default is off.
|
; Show source line containing error. Default is off.
|
; Show_source = 1
|
; Show_source = 1
|
|
|
Quiet = 0
|
Quiet = 0
|
Show_source = 0
|
Show_source = 0
|
NoDebug = 0
|
NoDebug = 0
|
Hazard = 0
|
Hazard = 0
|
UpCase = 0
|
UpCase = 0
|
OptionFile = ../../../../sim/rtl_sim/modelsim_sim/bin/vlog.opt
|
OptionFile = ../../../../sim/rtl_sim/modelsim_sim/bin/vlog.opt
|
[vsim]
|
[vsim]
|
; Simulator resolution
|
; Simulator resolution
|
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
resolution = 1ns
|
resolution = 1ns
|
|
|
; User time unit for run commands
|
; User time unit for run commands
|
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
; unit specified for Resolution. For example, if Resolution is 100ps,
|
; unit specified for Resolution. For example, if Resolution is 100ps,
|
; then UserTimeUnit defaults to ps.
|
; then UserTimeUnit defaults to ps.
|
UserTimeUnit = ns
|
UserTimeUnit = ns
|
|
|
; Default run length
|
; Default run length
|
RunLength = 100
|
RunLength = 100
|
|
|
; Maximum iterations that can be run without advancing simulation time
|
; Maximum iterations that can be run without advancing simulation time
|
IterationLimit = 5000
|
IterationLimit = 5000
|
|
|
; Directives to license manager can be set either as single value or as
|
; Directives to license manager can be set either as single value or as
|
; space separated multi-values:
|
; space separated multi-values:
|
; vhdl Immediately reserve a VHDL license
|
; vhdl Immediately reserve a VHDL license
|
; vlog Immediately reserve a Verilog license
|
; vlog Immediately reserve a Verilog license
|
; plus Immediately reserve a VHDL and Verilog license
|
; plus Immediately reserve a VHDL and Verilog license
|
; nomgc Do not look for Mentor Graphics Licenses
|
; nomgc Do not look for Mentor Graphics Licenses
|
; nomti Do not look for Model Technology Licenses
|
; nomti Do not look for Model Technology Licenses
|
; noqueue Do not wait in the license queue when a license is not available
|
; noqueue Do not wait in the license queue when a license is not available
|
; viewsim Try for viewer license but accept simulator license(s) instead
|
; viewsim Try for viewer license but accept simulator license(s) instead
|
; of queuing for viewer license (PE ONLY)
|
; of queuing for viewer license (PE ONLY)
|
; Single value:
|
; Single value:
|
; License = plus
|
; License = plus
|
; Multi-value:
|
; Multi-value:
|
; License = noqueue plus
|
; License = noqueue plus
|
|
|
; Stop the simulator after an assertion message
|
; Stop the simulator after an assertion message
|
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
BreakOnAssertion = 3
|
BreakOnAssertion = 3
|
|
|
; Assertion Message Format
|
; Assertion Message Format
|
; %S - Severity Level
|
; %S - Severity Level
|
; %R - Report Message
|
; %R - Report Message
|
; %T - Time of assertion
|
; %T - Time of assertion
|
; %D - Delta
|
; %D - Delta
|
; %I - Instance or Region pathname (if available)
|
; %I - Instance or Region pathname (if available)
|
; %% - print '%' character
|
; %% - print '%' character
|
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
|
|
; Assertion File - alternate file for storing assertion messages
|
; Assertion File - alternate file for storing assertion messages
|
; AssertFile = assert.log
|
; AssertFile = assert.log
|
|
|
; Default radix for all windows and commands...
|
; Default radix for all windows and commands...
|
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
DefaultRadix = symbolic
|
DefaultRadix = symbolic
|
|
|
; VSIM Startup command
|
; VSIM Startup command
|
; Startup = do startup.do
|
; Startup = do startup.do
|
|
|
; File for saving command transcript
|
; File for saving command transcript
|
TranscriptFile = transcript
|
TranscriptFile = transcript
|
|
|
; File for saving command history
|
; File for saving command history
|
; CommandHistory = cmdhist.log
|
; CommandHistory = cmdhist.log
|
|
|
; Specify whether paths in simulator commands should be described
|
; Specify whether paths in simulator commands should be described
|
; in VHDL or Verilog format. For VHDL, PathSeparator = /
|
; in VHDL or Verilog format. For VHDL, PathSeparator = /
|
; for Verilog, PathSeparator = .
|
; for Verilog, PathSeparator = .
|
PathSeparator = /
|
PathSeparator = /
|
|
|
; Specify the dataset separator for fully rooted contexts.
|
; Specify the dataset separator for fully rooted contexts.
|
; The default is ':'. For example, sim:/top
|
; The default is ':'. For example, sim:/top
|
; Must not be the same character as PathSeparator.
|
; Must not be the same character as PathSeparator.
|
DatasetSeparator = :
|
DatasetSeparator = :
|
|
|
; Disable assertion messages
|
; Disable assertion messages
|
; IgnoreNote = 1
|
; IgnoreNote = 1
|
; IgnoreWarning = 1
|
; IgnoreWarning = 1
|
; IgnoreError = 1
|
; IgnoreError = 1
|
; IgnoreFailure = 1
|
; IgnoreFailure = 1
|
|
|
; Default force kind. May be freeze, drive, or deposit
|
; Default force kind. May be freeze, drive, or deposit
|
; or in other terms, fixed, wired, or charged.
|
; or in other terms, fixed, wired, or charged.
|
; DefaultForceKind = freeze
|
; DefaultForceKind = freeze
|
|
|
; If zero, open files when elaborated; otherwise, open files on
|
; If zero, open files when elaborated; otherwise, open files on
|
; first read or write. Default is 0.
|
; first read or write. Default is 0.
|
; DelayFileOpen = 1
|
; DelayFileOpen = 1
|
|
|
; Control VHDL files opened for write
|
; Control VHDL files opened for write
|
; 0 = Buffered, 1 = Unbuffered
|
; 0 = Buffered, 1 = Unbuffered
|
UnbufferedOutput = 0
|
UnbufferedOutput = 0
|
|
|
; Control number of VHDL files open concurrently
|
; Control number of VHDL files open concurrently
|
; This number should always be less than the
|
; This number should always be less than the
|
; current ulimit setting for max file descriptors.
|
; current ulimit setting for max file descriptors.
|
; 0 = unlimited
|
; 0 = unlimited
|
ConcurrentFileLimit = 40
|
ConcurrentFileLimit = 40
|
|
|
; Controls the number of hierarchical regions displayed as
|
; Controls the number of hierarchical regions displayed as
|
; part of a signal name shown in the waveform window. The default
|
; part of a signal name shown in the waveform window. The default
|
; value or a value of zero tells VSIM to display the full name.
|
; value or a value of zero tells VSIM to display the full name.
|
; WaveSignalNameWidth = 0
|
; WaveSignalNameWidth = 0
|
|
|
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
; and std_logic_signed packages.
|
; and std_logic_signed packages.
|
; StdArithNoWarnings = 1
|
; StdArithNoWarnings = 1
|
|
|
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
; NumericStdNoWarnings = 1
|
; NumericStdNoWarnings = 1
|
|
|
; Control the format of a generate statement label. Do not quote it.
|
; Control the format of a generate statement label. Do not quote it.
|
; GenerateFormat = %s__%d
|
; GenerateFormat = %s__%d
|
|
|
; Specify whether checkpoint files should be compressed.
|
; Specify whether checkpoint files should be compressed.
|
; The default is to be compressed.
|
; The default is to be compressed.
|
; CheckpointCompressMode = 0
|
; CheckpointCompressMode = 0
|
|
|
; List of dynamically loaded objects for Verilog PLI applications
|
; List of dynamically loaded objects for Verilog PLI applications
|
; Veriuser = veriuser.sl
|
; Veriuser = veriuser.sl
|
|
|
; Specify default options for the restart command. Options can be one
|
; Specify default options for the restart command. Options can be one
|
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
; DefaultRestartOptions = -force
|
; DefaultRestartOptions = -force
|
|
|
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
; (> 500 megabyte memory footprint). Default is disabled.
|
; (> 500 megabyte memory footprint). Default is disabled.
|
; Specify number of megabytes to lock.
|
; Specify number of megabytes to lock.
|
; LockedMemory = 1000
|
; LockedMemory = 1000
|
|
|
; Turn on (1) or off (0) WLF file compression.
|
; Turn on (1) or off (0) WLF file compression.
|
; The default is 1; compress WLF file.
|
; The default is 1; compress WLF file.
|
; WLFCompress = 0
|
; WLFCompress = 0
|
|
|
; Specify whether to save all design hierarchy (1) in WLF file
|
; Specify whether to save all design hierarchy (1) in WLF file
|
; or only regions containing logged signals (0).
|
; or only regions containing logged signals (0).
|
; The default is 0; log only regions with logged signals.
|
; The default is 0; log only regions with logged signals.
|
; WLFSaveAllRegions = 1
|
; WLFSaveAllRegions = 1
|
|
|
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
; to the specified amount of simulation time. When the limit is exceeded
|
; to the specified amount of simulation time. When the limit is exceeded
|
; the earliest times get truncated from the file.
|
; the earliest times get truncated from the file.
|
; If both time and size limits are specified the most restrictive is used.
|
; If both time and size limits are specified the most restrictive is used.
|
; UserTimeUnits are used if time units are not specified.
|
; UserTimeUnits are used if time units are not specified.
|
; The default is 0; no limit. Example: WLFTimeLimit = {100 ms}
|
; The default is 0; no limit. Example: WLFTimeLimit = {100 ms}
|
; WLFTimeLimit = 0
|
; WLFTimeLimit = 0
|
|
|
; WLF file size limit. Limit WLF file size, as closely as possible,
|
; WLF file size limit. Limit WLF file size, as closely as possible,
|
; to the specified number of megabytes. If both time and size limits
|
; to the specified number of megabytes. If both time and size limits
|
; are specified then the most restrictive is used.
|
; are specified then the most restrictive is used.
|
; The default is 0; no limit.
|
; The default is 0; no limit.
|
; WLFSizeLimit = 1000
|
; WLFSizeLimit = 1000
|
|
|
; Specify whether or not a WLF file should be deleted when the
|
; Specify whether or not a WLF file should be deleted when the
|
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
; The default is 0; do not delete WLF file when simulation ends.
|
; The default is 0; do not delete WLF file when simulation ends.
|
; WLFDeleteOnQuit = 1
|
; WLFDeleteOnQuit = 1
|
|
|
[lmc]
|
[lmc]
|
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
|
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
|
libsm = $MODEL_TECH/libsm.sl
|
libsm = $MODEL_TECH/libsm.sl
|
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
|
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
|
; libsm = $MODEL_TECH/libsm.dll
|
; libsm = $MODEL_TECH/libsm.dll
|
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
|
; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
|
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
|
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
|
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
|
; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
|
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
|
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
|
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
|
; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
|
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
|
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
|
; Logic Modeling's SmartModel SWIFT software (Windows NT)
|
; Logic Modeling's SmartModel SWIFT software (Windows NT)
|
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
|
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
|
; Logic Modeling's SmartModel SWIFT software (Linux)
|
; Logic Modeling's SmartModel SWIFT software (Linux)
|
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
|
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
|
|
|
; ModelSim's interface to Logic Modeling's hardware modeler SFI software
|
; ModelSim's interface to Logic Modeling's hardware modeler SFI software
|
libhm = $MODEL_TECH/libhm.sl
|
libhm = $MODEL_TECH/libhm.sl
|
; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
|
; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
|
; libhm = $MODEL_TECH/libhm.dll
|
; libhm = $MODEL_TECH/libhm.dll
|
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
|
; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
|
; libsfi = /lib/hp700/libsfi.sl
|
; libsfi = /lib/hp700/libsfi.sl
|
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
|
; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
|
; libsfi = /lib/rs6000/libsfi.a
|
; libsfi = /lib/rs6000/libsfi.a
|
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
|
; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
|
; libsfi = /lib/sun4.solaris/libsfi.so
|
; libsfi = /lib/sun4.solaris/libsfi.so
|
; Logic Modeling's hardware modeler SFI software (Windows NT)
|
; Logic Modeling's hardware modeler SFI software (Windows NT)
|
; libsfi = /lib/pcnt/lm_sfi.dll
|
; libsfi = /lib/pcnt/lm_sfi.dll
|
; Logic Modeling's hardware modeler SFI software (Linux)
|
; Logic Modeling's hardware modeler SFI software (Linux)
|
; libsfi = /lib/linux/libsfi.so
|
; libsfi = /lib/linux/libsfi.so
|
[Project]
|
[Project]
|
Project_Version = 3
|
Project_Version = 3
|
Project_DefaultLib = work
|
Project_DefaultLib = work
|
Project_SortMethod = alpha
|
Project_SortMethod = alpha
|
Project_Files_Count = 34
|
Project_Files_Count = 34
|
Project_File_0 = ../../../../rtl/verilog/eth_registers.v
|
Project_File_0 = ../../../../rtl/verilog/eth_registers.v
|
Project_File_P_0 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031654124 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 12 dont_compile 0
|
Project_File_P_0 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031654124 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 12 dont_compile 0
|
Project_File_1 = ../../../../rtl/verilog/eth_crc.v
|
Project_File_1 = ../../../../rtl/verilog/eth_crc.v
|
Project_File_P_1 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 2 dont_compile 0
|
Project_File_P_1 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 2 dont_compile 0
|
Project_File_2 = ../../../../rtl/verilog/eth_random.v
|
Project_File_2 = ../../../../rtl/verilog/eth_random.v
|
Project_File_P_2 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 9 dont_compile 0
|
Project_File_P_2 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 9 dont_compile 0
|
Project_File_3 = ../../../../bench/verilog/wb_bus_mon.v
|
Project_File_3 = ../../../../bench/verilog/wb_bus_mon.v
|
Project_File_P_3 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 30 dont_compile 0
|
Project_File_P_3 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 30 dont_compile 0
|
Project_File_4 = ../../../../bench/verilog/tb_ethernet.v
|
Project_File_4 = ../../../../bench/verilog/tb_ethernet.v
|
Project_File_P_4 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1032198830 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 29 dont_compile 0
|
Project_File_P_4 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1032198830 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 29 dont_compile 0
|
Project_File_5 = ../../../../rtl/verilog/eth_outputcontrol.v
|
Project_File_5 = ../../../../rtl/verilog/eth_outputcontrol.v
|
Project_File_P_5 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1026245520 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 8 dont_compile 0
|
Project_File_P_5 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1026245520 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 8 dont_compile 0
|
Project_File_6 = ../../../../rtl/verilog/eth_transmitcontrol.v
|
Project_File_6 = ../../../../rtl/verilog/eth_transmitcontrol.v
|
Project_File_P_6 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 20 dont_compile 0
|
Project_File_P_6 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 20 dont_compile 0
|
Project_File_7 = ../../../../rtl/verilog/eth_top.v
|
Project_File_7 = ../../../../rtl/verilog/eth_top.v
|
Project_File_P_7 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842218 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 19 dont_compile 0
|
Project_File_P_7 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842218 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 19 dont_compile 0
|
Project_File_8 = ../../../../rtl/verilog/eth_rxaddrcheck.v
|
Project_File_8 = ../../../../rtl/verilog/eth_rxaddrcheck.v
|
Project_File_P_8 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164866 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 13 dont_compile 0
|
Project_File_P_8 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164866 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 13 dont_compile 0
|
Project_File_9 = ../../../../bench/verilog/wb_model_defines.v
|
Project_File_9 = ../../../../bench/verilog/wb_model_defines.v
|
Project_File_P_9 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 33 dont_compile 0
|
Project_File_P_9 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 33 dont_compile 0
|
Project_File_10 = ../../../../rtl/verilog/eth_receivecontrol.v
|
Project_File_10 = ../../../../rtl/verilog/eth_receivecontrol.v
|
Project_File_P_10 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 10 dont_compile 0
|
Project_File_P_10 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 10 dont_compile 0
|
Project_File_11 = ../../../../rtl/verilog/eth_rxethmac.v
|
Project_File_11 = ../../../../rtl/verilog/eth_rxethmac.v
|
Project_File_P_11 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013843728 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 15 dont_compile 0
|
Project_File_P_11 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013843728 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 15 dont_compile 0
|
Project_File_12 = ../../../../bench/verilog/eth_phy_defines.v
|
Project_File_12 = ../../../../bench/verilog/eth_phy_defines.v
|
Project_File_P_12 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 27 dont_compile 0
|
Project_File_P_12 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 27 dont_compile 0
|
Project_File_13 = ../../../../rtl/verilog/eth_miim.v
|
Project_File_13 = ../../../../rtl/verilog/eth_miim.v
|
Project_File_P_13 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349930 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 7 dont_compile 0
|
Project_File_P_13 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349930 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 7 dont_compile 0
|
Project_File_14 = ../../../../rtl/verilog/eth_rxcounters.v
|
Project_File_14 = ../../../../rtl/verilog/eth_rxcounters.v
|
Project_File_P_14 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013771610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 14 dont_compile 0
|
Project_File_P_14 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013771610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 14 dont_compile 0
|
Project_File_15 = ../../../../rtl/verilog/eth_register.v
|
Project_File_15 = ../../../../rtl/verilog/eth_register.v
|
Project_File_P_15 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029535812 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 11 dont_compile 0
|
Project_File_P_15 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029535812 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 11 dont_compile 0
|
Project_File_16 = ../../../../bench/verilog/wb_slave_behavioral.v
|
Project_File_16 = ../../../../bench/verilog/wb_slave_behavioral.v
|
Project_File_P_16 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 34 dont_compile 0
|
Project_File_P_16 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 34 dont_compile 0
|
Project_File_17 = ../../../../bench/verilog/wb_master_behavioral.v
|
Project_File_17 = ../../../../bench/verilog/wb_master_behavioral.v
|
Project_File_P_17 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 31 dont_compile 0
|
Project_File_P_17 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 31 dont_compile 0
|
Project_File_18 = ../../../../rtl/verilog/eth_txethmac.v
|
Project_File_18 = ../../../../rtl/verilog/eth_txethmac.v
|
Project_File_P_18 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1014740642 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 22 dont_compile 0
|
Project_File_P_18 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1014740642 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 22 dont_compile 0
|
Project_File_19 = ../../../../rtl/verilog/eth_wishbone.v
|
Project_File_19 = ../../../../rtl/verilog/eth_wishbone.v
|
Project_File_P_19 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031753926 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 24 dont_compile 0
|
Project_File_P_19 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031753926 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 24 dont_compile 0
|
Project_File_20 = ../../../../rtl/verilog/eth_txcounters.v
|
Project_File_20 = ../../../../rtl/verilog/eth_txcounters.v
|
Project_File_P_20 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019487254 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 21 dont_compile 0
|
Project_File_P_20 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019487254 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 21 dont_compile 0
|
Project_File_21 = ../../../../bench/verilog/eth_phy.v
|
Project_File_21 = ../../../../bench/verilog/eth_phy.v
|
Project_File_P_21 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031928616 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 26 dont_compile 0
|
Project_File_P_21 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031928616 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 26 dont_compile 0
|
Project_File_22 = ../../../../bench/verilog/wb_master32.v
|
Project_File_22 = ../../../../bench/verilog/wb_master32.v
|
Project_File_P_22 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 32 dont_compile 0
|
Project_File_P_22 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 32 dont_compile 0
|
Project_File_23 = ../../../../rtl/verilog/eth_rxstatem.v
|
Project_File_23 = ../../../../rtl/verilog/eth_rxstatem.v
|
Project_File_P_23 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 16 dont_compile 0
|
Project_File_P_23 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 16 dont_compile 0
|
Project_File_24 = ../../../../bench/verilog/tb_eth_defines.v
|
Project_File_24 = ../../../../bench/verilog/tb_eth_defines.v
|
Project_File_P_24 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031942506 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 28 dont_compile 0
|
Project_File_P_24 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031942506 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 28 dont_compile 0
|
Project_File_25 = ../../../../rtl/verilog/eth_maccontrol.v
|
Project_File_25 = ../../../../rtl/verilog/eth_maccontrol.v
|
Project_File_P_25 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 5 dont_compile 0
|
Project_File_P_25 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 5 dont_compile 0
|
Project_File_26 = ../../../../rtl/verilog/eth_txstatem.v
|
Project_File_26 = ../../../../rtl/verilog/eth_txstatem.v
|
Project_File_P_26 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 23 dont_compile 0
|
Project_File_P_26 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 23 dont_compile 0
|
Project_File_27 = ../../../../rtl/verilog/eth_shiftreg.v
|
Project_File_27 = ../../../../rtl/verilog/eth_shiftreg.v
|
Project_File_P_27 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349020 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 17 dont_compile 0
|
Project_File_P_27 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349020 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 17 dont_compile 0
|
Project_File_28 = ../../../../rtl/verilog/eth_spram_256x32.v
|
Project_File_28 = ../../../../rtl/verilog/eth_spram_256x32.v
|
Project_File_P_28 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1027442170 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 18 dont_compile 0
|
Project_File_P_28 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1027442170 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 18 dont_compile 0
|
Project_File_29 = ../../../../rtl/verilog/eth_fifo.v
|
Project_File_29 = ../../../../rtl/verilog/eth_fifo.v
|
Project_File_P_29 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019483152 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0
|
Project_File_P_29 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019483152 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0
|
Project_File_30 = ../../../../rtl/verilog/eth_macstatus.v
|
Project_File_30 = ../../../../rtl/verilog/eth_macstatus.v
|
Project_File_P_30 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842216 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 6 dont_compile 0
|
Project_File_P_30 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842216 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 6 dont_compile 0
|
Project_File_31 = ../../../../rtl/verilog/eth_defines.v
|
Project_File_31 = ../../../../rtl/verilog/eth_defines.v
|
Project_File_P_31 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 3 dont_compile 0
|
Project_File_P_31 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 3 dont_compile 0
|
Project_File_32 = ../../../../rtl/verilog/eth_clockgen.v
|
Project_File_32 = ../../../../rtl/verilog/eth_clockgen.v
|
Project_File_P_32 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 0 dont_compile 0
|
Project_File_P_32 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 0 dont_compile 0
|
Project_File_33 = ../../../../rtl/verilog/timescale.v
|
Project_File_33 = ../../../../rtl/verilog/timescale.v
|
Project_File_P_33 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 25 dont_compile 0
|
Project_File_P_33 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 25 dont_compile 0
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Project_Sim_Count = 0
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Project_Sim_Count = 0
|
Project_Folder_Count = 0
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Project_Folder_Count = 0
|
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