ࡱ > 7 $ bjbjUU ( 7| 7| r l t t t T p HW HW HW W X p Y ] ^ ^ ^ ` d 4 e $ 3 S t f ` ` f f bx ^ ^ 5 : bx bx bx f x
^ R ^ bx f bx bx z q a R R " ^ Y 9Cp 6 HW s . o <
x L bx
|
ࡱ > 7 $ bjbjUU ( 7| 7| r l t t t T p HW HW HW W X p Y ] ^ ^ ^ ` d 4 e $ 3 S t f ` ` f f bx ^ ^ 5 : bx bx bx f x
^ R ^ bx f bx bx z q a R R " ^ Y 9Cp 6 HW s . o <
x L bx
|
Ethernet IP Core Design Document
Author: Igor Mohor
IgorM@opencores.org
Rev. 0.1
DATE \@ "MMMM d, yyyy" \* MERGEFORMAT August 14, 2002
This page has been intentionally left blank.
Revision History
Rev.DateAuthorDescription0.124/04/02Igor MohorFirst Draft
List of Contents
TOC \o "1-3" \h \z HYPERLINK \l "_Toc17022758" 1 PAGEREF _Toc17022758 \h 1
HYPERLINK \l "_Toc17022759" Introduction PAGEREF _Toc17022759 \h 1
HYPERLINK \l "_Toc17022760" 1.1 Ethernet IP Core Introduction PAGEREF _Toc17022760 \h 1
HYPERLINK \l "_Toc17022761" 1.2 Ethernet IP Core Features PAGEREF _Toc17022761 \h 1
HYPERLINK \l "_Toc17022762" 1.3 Ethernet IP Core Directory Structure PAGEREF _Toc17022762 \h 2
HYPERLINK \l "_Toc17022763" 2 PAGEREF _Toc17022763 \h 5
HYPERLINK \l "_Toc17022764" Ethernet MAC IP Core PAGEREF _Toc17022764 \h 5
HYPERLINK \l "_Toc17022765" 2.1 Overview PAGEREF _Toc17022765 \h 5
HYPERLINK \l "_Toc17022766" 2.1.1 WISHBONE Interface PAGEREF _Toc17022766 \h 5
HYPERLINK \l "_Toc17022767" 2.1.2 Transmit Module PAGEREF _Toc17022767 \h 5
HYPERLINK \l "_Toc17022768" 2.1.3 Receive Module PAGEREF _Toc17022768 \h 5
HYPERLINK \l "_Toc17022769" 2.1.4 Control Module PAGEREF _Toc17022769 \h 6
HYPERLINK \l "_Toc17022770" 2.1.5 MII Module (Media Independent Module) PAGEREF _Toc17022770 \h 6
HYPERLINK \l "_Toc17022771" 2.2 Core File Hierarchy PAGEREF _Toc17022771 \h 6
HYPERLINK \l "_Toc17022772" 2.3 Description of Core Modules PAGEREF _Toc17022772 \h 8
HYPERLINK \l "_Toc17022773" 2.3.1 Description of the MII (eth_miim.v) module PAGEREF _Toc17022773 \h 8
HYPERLINK \l "_Toc17022774" 2.3.2 Description of the Receive module (eth_rxethmac.v) PAGEREF _Toc17022774 \h 11
HYPERLINK \l "_Toc17022775" 2.3.3 Description of the Transmit module (eth_txethmac.v) PAGEREF _Toc17022775 \h 15
HYPERLINK \l "_Toc17022776" 2.3.4 Description of the Control module (eth_maccontrol.v) PAGEREF _Toc17022776 \h 4
HYPERLINK \l "_Toc17022777" 2.3.5 Description of the Status module (eth_macstatus) PAGEREF _Toc17022777 \h 6
HYPERLINK \l "_Toc17022778" 3 PAGEREF _Toc17022778 \h 7
HYPERLINK \l "_Toc17022779" Registers PAGEREF _Toc17022779 \h 7
HYPERLINK \l "_Toc17022780" 4 PAGEREF _Toc17022780 \h 8
HYPERLINK \l "_Toc17022781" Operation PAGEREF _Toc17022781 \h 8
HYPERLINK \l "_Toc17022782" 5 PAGEREF _Toc17022782 \h 9
HYPERLINK \l "_Toc17022783" Architecture PAGEREF _Toc17022783 \h 9
List of Tables
TOC \h \z \t "Caption,1" Error! No table of contents entries found.
List of Figures
TOC \h \z \t "Caption 1,1" Error! No table of contents entries found.
Introduction
1.1 Ethernet IP Core Introduction
The Ethernet IP Core is a MAC (Media Access Controller). It connects to the Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other. The core has been designed to offer as much flexibility as possible to all kinds of applications.
The chapter 2 describes file hierarchy, description of modules, core design considerations and constants regarding the Ethernet IP Core.
The chapter 3 describes test bench file hierarchy, description of modules, test bench design considerations, description of test cases and constants regarding the test bench.
1.2 Ethernet IP Core Features
The following lists the main features of the Ethernet IP core.
Performing MAC layer functions of IEEE 802.3 and Ethernet
Automatic 32-bit CRC generation and checking
Delayed CRC generation
Preamble generation and removal
Automatically pad short frames on transmit
Detection of too long or too short packets (length limits)
Possible transmission of packets that are bigger than standard packets.
Full duplex support
10 and 100 Mbps bit rates supported
Automatic packet abortion on Excessive deferral limit, too small inter packet gap, when enabled
Flow control and automatic generation of control frames in full duplex mode (IEEE 802.3x)
Collision detection and auto retransmission on collisions in half duplex mode (CSMA/CD protocol)
Complete status for TX/RX packets
IEEE 802.3 Media Independent Interface (MII)
WISHBONE SoC Interconnection Rev. B compliant interface
Internal RAM for holding 128 TX/RX buffer descriptors
Interrupt generation an all events
1.3 Ethernet IP Core Directory Structure
Following picture shows the structure of directories of the Ethernet IP core.
There are three major parts of the Verilog code in the ethernet directory. First one is the code for the Ethernet MAC IP core. The Verilog files are in the ethernet\rtl\verilog subdirectory. The second one is the code for the Ethernet MAC Testbench. These files are used together with files for the Ethernet MAC. There are also some exceptions, but those will be mentioned later. The Verilog files are in the ethernet\bench\verilog subdirectory.
The documentation is in the subdirectory ethernet\doc. Documentation consists of Ethernet IP Core Data Sheet, Ethernet IP Core Specification and Ethernet IP Core Design document.
ethernet\sim subdirectory is used for running simulation testbench. The rtl_sim subdirectory
is used for RTL ( functional ) simulation of the core. There are a few directories included
here:
bin includes various scripts needed for running Ncsim simulator
run the directory from which the simulation is ran. It provides a script for starting the simulation and a script for cleaning all the results produced by previous simulation runs
log Ncvlog, Ncelab and Ncsim log files are stored here for review.
out simulation output directory simulation stores all the results into this directory ( dump files for viewing with Signalscan, testbench text output etc. )
The gate_sim directory is used the same way as rtl_sim, except simulation is run with the netlist provided from synthesis tool.
Generated files from synthesis tools, like gate level Verilog and log files, are stored in the ethernet\syn subdirectory and its subdirectories.
Ethernet MAC IP Core
2.1 Overview
The Ethernet MAC IP Core consists of seven main units: WISHBONE interface, transmit module, receive module, control module, MII module, status module and register module. Many of these modules have sub-modules. Module and sub-module operations are described later in this section.
2.1.1 WISHBONE Interface
Consists of both master and slave interfaces and connects the core to the WISHBONE bus. Master interface is used for storing the received data frames to the memory and loading the data that needs to be sent from the memory to the Ethernet core. Interface is WISHBONE Revision B.1 compatible.
2.1.2 Transmit Module
Performs all transmitting related operations (preamble generation, padding, CRC, etc.).
2.1.3 Receive Module
Performs all reception related operations (preamble removal, CRC check, etc).
2.1.4 Control Module
Performs all flow control related operations when Ethernet is used in full duplex mode.
2.1.5 MII Module (Media Independent Module)
Provides a Media independent interface to the external Ethernet PHY chip.
2.1.6 Status Module
dqweq
2.2 Core File Hierarchy
The hierarchy of modules in the Ethernet core is shown here with file tree. Each file implements one module in a hierarchy. RTL source files of the Ethernet core are in the ethernet\rtl\verilog subdirectory.
ethernet
. sim
. . rtl_sim
. . . src
. . . run
. rtl
. . verilog
. . . eth_top.v
. . . eth_crc.v
. . . eth_defines.v.bak
. . . eth_miim.v
. . . eth_defines.v
. . . timescale.v
. . . eth_random.v
. . . eth_fifo.v
. . . eth_wishbone.v
. . . eth_maccontrol.v
. . . eth_crc.v.bak
. . . eth_rxaddrcheck.v
. . . eth_txstatem.v
. . . eth_transmitcontrol.v
. . . eth_txethmac.v
. . . generic_spram.v
. . . eth_rxcounters.v
. . . eth_rxstatem.v
. . . eth_outputcontrol.v
. . . eth_register.v
. . . eth_receivecontrol.v
. . . eth_registers.v
. . . eth_shiftreg.v
. . . eth_txcounters.v
. . . eth_clockgen.v
. . . eth_rxethmac.v
. . . eth_macstatus.v
. doc
. . eth_speci.pdf
. . eth_design_document.pdf
. . Ethernet Datasheet (prl.).pdf
. . src
. . . eth_speci.doc
. . . eth_design_document.doc
. . . Ethernet Datasheet (prl.).doc
. bench
. . verilog
. . . tb_eth_top.v
2.3 Description of Core Modules
The module eth_top.v consists of sub modules eth_miim.v, eth_registers.v, eth_maccontrol.v, eth_txethmac.v, eth_rxethmac.v, eth_wishbone.v, eth_macstatus.v and some logic for synchronizing, multiplexing and registering outputs.
Put a figure here !!!
2.3.1 Description of the MII (eth_miim.v) module
The MII module (Media Independent Interface) is an interface to the external Ethernet PHY chip. It is used for setting PHYs configuration registers and reading status from it. The interface consists of only two signals: clock (MDC) and bi-directional data signal (MDIO). Bi-directional MDIO signal needs to be combined from input signal Mdi, output signal Mdo, and enable signal MdoEn in additional module. This is done because the same Ethernet core will be implemented in both ASIC and FPGA.
The MII module is the top module for the MII and consists of several sub modules (eth_clockgen.v, eth_shiftreg.v, eth_outputcontrol.v) and additional logic. This logic is used for generating number of signals:
Synchronized request for write (WriteDataOp), read (ReadStatusOp) and scan (ScanStatusOp) operations.
Signal for updating the MIIRX_DATA register (UpdateMIIRX_DATAReg)
Counter (BitCounter) is the primary counter for the MII Interface (many operations depend on it.
Byte select signals used when data is shifted out (ByteSelect [3:0]).
Signals used for latching the input data (LatchByte [1:0]).
When there is a need to read or write the data from the PHY chip, several operations need to be performed:
MIIMODER register needs to be set:
Clock divider needs to be set to provide clock signal Mdc of the appropriate frequency (read PHY documentation to obtain the value of the Mdc frequency)
Preamble generation might be disabled (if PHY supports transmissions without the preamble). By default 32-bit preamble is transmitted.
MII Module might be reset prior to its usage.
PHY Address (several PHY chips might be connected to the MII interface) and address of the register within the selected PHY chip need to be set in the MIIADDRESS register.
If there is a need to write data to the selected register, data needs to be written to the MIITX_DATA register.
Writing appropriate value to the MIICOMMAND register starts requested operation.
If Read status or Scan status operation were requested than the value that was received from the PHY can be read from the MIIRX_DATA register.
MIISTATUS register reflects the status of the MII module. The LinkFail status is cleared only after the read to the PHYs status register (address 0x1) returns status that is OK.
2.3.2.1 Description of the eth_outputcontrol module
This module performs two tasks:
Generates MII serial output signal (Mdo)
Generates enable signal (MdoEn) for the Mdo.
Since the MII serial data signal is a bi-directional signal, these two signals need to be combined together with the MII serial input signal (Mdi) in additional module that is not part of the Ethernet MAC IP Core.
The eth_outputcontrol module also generates the MII preamble. When MII preamble is enabled (bit 8 in the MIIMODER register set to 0), 32-bit preamble is transmitted prior to the data.
2.3.2.2 Description of the eth_clockgen module
The eth_clockgen module is used for:
Generating MII clock signal (Mdc). This is output clock signal used for clocking the MII interface of the Ethernet PHY chip. You should read the specification for the used PHY chip to properly set the Mdc frequency (usually frequencies up to 10 MHz can be used)
Generating MdcEn signal. This signal is an enable signal. All flip-flops used in the MII are clocked with the high frequency clock Clk. The reduced frequency (equal to Mdc) is obtained by using the MdcEn signal.
Mdc is obtained by dividing the Clk signal with the value that is written in the MIIMODER register (any value within range [1:255]).
2.3.2.3 Description of the eth_shiftreg module
The eth_shiftreg module is used for:
Serialize the data that goes towards Ethernet PHY chip (Mdo)
Parallelize input data that comes from Ethernet PHY chip (Mdi) and temporally store it to the Prsd register. This value is then stored to the MIIRX_DATA register.
Generating LinkFail signal (bit 0 of the MIISTATUS register reflects its value).
2.3.2 Description of the Receive module (eth_rxethmac.v)
The Receive module is in charge for receiving data. External PHY chip receives serial data from the physical layer (cable), assembles it to nibbles and sends to the receive module (MRxD [3:0]) together with the data valid marker (MRxDV). The receive module then assembles this data nibbles to data bytes, and sends them to the WISHBONE interface module together with few signals that mark start and end of the data. Receive module also removes the preamble and the CRC.
The Receive module consists of four sub modules:
eth_crc Cyclic Redundancy Check (CRC) module
eth_rxaddrcheck Address recognition module
eth_rxcounters Various counters needed for packet reception
eth_rxstatem State machine for Receive module
Besides the above sub modules, eth_rxethmac module also consists of logic that is used for:
Generating CrcHash value and CrcHashGood marker that are used in address recognition system.
Latching the data that is received from the PHY chip (RxData).
Generating Broadcast and Multicast marker (when packets with broadcast or multicast destination address are received).
Generating RxValid, RxStartFrm, RxEndFrm signals that are marking valid data.
Receiver can operate in various modes. For that reason number of registers need to be configured prior to Receivers use.
Signals related to the receiver operation are:
HugEn Reception of big packets is enabled (packets, bigger than the standard Ethernet packets). When HugEn is disabled, packets that smaller or equal to MaxFL and bigger or equal to MinFL are received. (MaxFL and MinFL are set in the PACKETLEN register).
DlyCrcEn Delayed CRC (Cyclic Redundancy Check) is enabled. CRC checking starts 4 bytes after the data becomes valid. This option is useful when additional data is added to the data frame.
r_IFG Minimum Inter Frame Gap Enable. When this signal is set to zero, minimum inter frame gap is required between two packets. After this time receiver starts with reception again. When r_IFG is set to 1, no inter packet gap is needed. All frames are received regardless to the IFG.
r_Pro, r_Bro, r_Iam and registers MAC, HASH0 and HASH1 are used for address recognition.
2.3.3.1 Description of the CRC (Cyclic Redundancy Check) module (eth_crc.v)
This module is used for validating the correctness of the incoming packet by checking the CRC value of the packet. CRC module is also used for the CRC generation for the TX module.
To better understand the CRC checking, here is a brief description how CRC is send and checked.
Before a transmitter sends the data, it appends the CRC (this CRC is calculated from the data) to it. This means that the packet is now bigger for 4 bytes. Receiver receives this data (that also includes the CRC of the data) and calculates a new CRC value from it (received CRC is also used for the CRC calculation). If the new CRC differs from the CRC Magic Number (0xc704dd7b), then received data differs from the sent data and CrcError signal is set.
2.3.3.2 Description of the address recognition module (eth_rxaddrcheck.v)
The address recognition module decides whether the packet will be received or not. Ethernet IP core starts receiving all packets regardless to their destination address. Destination address is then checked in the eth_rxaddrcheck sub module. Frame reception depends on few conditions:
If r_Pro bit is set in the MODER register (Promiscuous mode), then all frames are received regardless to their destination address. If r_Pro bit is cleared then destination address is checked.
If r_Bro bit is set in the MODER register then all frames containing broadcast addresses are rejected (r_Pro must be cleared).
MAC MAC address of the used Ethernet MAC IP Core. This is individual address of the used Ethernet core. When r_Pro bit is cleared then every destination address is compared to the MAC address. Frame is accepted only when two address match.
When r_Iam signal is set then besides checking the MAC address, hash table algorithm is used. The Ethernet controller maps any 48-bit address into one of 64 bits. If that bit is set in the HASH registers (HASH0 and r_HASH1 are making one 64-bit hash register), then frame is accepted.
As said before, packet reception always starts regardless of the destination address of the incoming packet. As soon as the destination address is received, it is checked if it matches with any of the above-mentioned conditions. If the match doesnt occur than the reception of the whole packet is aborted (signal RxAbort is set to 1). The packet is not written to the memory and receive buffer is flushed.
2.3.3.3 Description of the rxcounters module (eth_rxcounters.v)
The module consists of three counters, which are:
ByteCnt generally used counter in the receive module.
IFGCounter used for counting the IFG (inter frame gap)
DlyCrcCnt counter, used when delayed CRC operation is enabled.
Besides that a number of comparators are in this module, used for various purposes.
2.3.3.4 Description of the rxstatem module (eth_rxstatem.v)
There is just one state machine used in the receive module of the Ethernet IP core. This module is placed in the eth_rxstatem sub-module.
The state machine has six different states:
Idle state
Drop state
Preamble state
SFD (standard frame delimiter) state
Data 0 state
Data 1 state
State machine (SM) goes to the drop state (StateDrop) after the reset and immediately after that to the idle state (StateIdle) because MRxDV is set to 0. As soon as there is a valid data available on the PHYs data lines (MRxD), PHY informs receiver about that by setting the MRxDV signal to one.
Normally receiver expects preamble at the beginning of each packet. Standard preamble is 7 byte long (0xee). After that a one-byte SFD (start frame delimiter) is expected (0xde). If we put this together, then sample 0xdeeeeeee is expected (LSB received first).
Because the Ethernet IP core can also accept packets that dont have a standard 7-byte preamble but only the SFD, receivers SM waits for the first 0x5 nibble (it is not important whether this nibble is part of the preamble or of the SFD). If the received character differs from the expected nibble, then the SM goes to the preamble state (StatePreamble) and remains there until the correct nibble (0x5) is received. Once the 0x5 nibble is received, SM goes to the SFD state (StateSFD) where it waits for the 0xd nibble.
From here two things, depending on the value of the IFGCounterEq24 signal, may occur (next paragraph describes IFGCounterEq24 signal). If IFGCounterEq24 is set then:
SM goes to the data0 state (StateData0) where lower data nibble is received and then to the data1 state (StateData1) where higher data nibble is received. SM goes back to the data0 state. SM continues going from data state 0 to data state 1 and vice versa until whole data packet is received and end of packet is detected (PHY clears the MRxDV signal). Once the data valid signal is cleared, SM goes to the idle state (StateIdle) and everything starts again.
else (IFGCounterEq24 is cleared)
SM goes to the drop state (StateDrop) and remains there until the end of valid data is reported (PHY clears the MRxDV signal). After that SM goes to the idle state (StateIdle) and everything starts again.
Signal IFGCounterEq24 is used for detecting the proper gap between two consecutive received frames (Inter Frame Gap). By the standard this gap must be at least 960 ns for 100 Mbps mode or 9600ns for 10 Mbps mode. If the gap is appropriate (equal or greater than requested), then IFGCounterEq24 is set to 1. Signal IFGCounterEq24 is also set to 1, when IFG bit in the MODER register is set (minimum inter frame gap is not checked). If the IFG gap between two frames is too small, frame wont be accepted but dropped.
2.3.3 Description of the Transmit module (eth_txethmac.v)
The Transmit module (TX) is in charge for transmitting data. TX module gets data that needs to be transmitted from WISHBONE interface (WBI) module in the byte form. Besides that it also receives signals that mark start of the data frame (TxStartFrm) and end of the data frame (TxEndFrm). As soon as the TX module needs next data byte, it sets the TxUsedData and WBI module provides the next byte.
TX module sets number of signals to inform WBI module on one side and Ethernet PHY chip on the other about the operation status (done, retry, abort, error, etc.).
The Transmit module consists of four sub modules:
eth_crc Cyclic Redundancy Check (CRC) module generates 32-bit CRC that is appended to the data field.
eth_random Generates random delay that is needed when back off is performed (after the collision)
eth_txcounters Various counters needed for packet transmission
eth_txstatem State machine for TX module
Signals, connected to the Ethernet PHY chip are:
Data nibble MTxD. This is the data that will be sent on the Ethernet by the PHY.
Transmit enable MTxEn tells PHY that data MTxD is valid and transmission should start.
Transmit error MTxErr tells PHY that an error happened during the transmission.
Signals, connected to the upper layer module (WBI module) are:
Transmit packet done TxDone (see next paragraph)
Transmit packet retry TxRetry (see next paragraph)
Transmit packet abort TxAbort (see next paragraph)
TxUsedData;
Every transmission ends in one of the following ways:
Transmission is successfully finished. Signal TxDone is set.
Transmission needs to be repeated. Signal TxRetry is set. This happens when a normal collision occurs (in half-duplex mode).
Transmission is aborted. Signal TxAbort is set. This happens in the following situations:
Packet is too big (bigger than the max. packet (See MAXFL field of the PACKETLEN register)).
Underrun occurs (WBI module can not provide data on time).
Excessive deferral occurs (TX state machine remains in the defer state for too long).
Late collision occurs (late collision is every collision that happens later than COLLVALID bytes after the preamble (See COLLCONF register)).
Maximum number of collisions happens (See MAXRET field of the COLLCONF register).
Besides all previously mentioned signals, TX module provides other signals:
WillTransmit notifies the receiver that transmitter will start transmitting. Receiver stops receiving until WillTransmit is cleared.
Generating the collision reset signal (collision detected asynchronously comes from the PHY chip and is synchronized to the TX clock signal). ResetCollision signal is used to reset synchronizing flip-flop.
Collision window ColWindow marks a window within every collision is treated as a valid (regular) collision. After a collision packet is retransmitted. Every collision that occurs after that is a late collision (packets with late collision are aborted).
Retry counter RetryCnt.
Data_Crc, Enable_Crc and Initialize_Crc that are used for CRC generation.
2.3.4.1 Description of the CRC (Cyclic Redundancy Check) module (eth_crc.v)
This module is used for CRC calculation. The calculated CRC is appended to the data frame. This module is also used in the RX module for CRC checking.
2.3.4.2 Description of the random module (eth_random.v)
When a collision occurs, TX module first sends a jam pattern (0x99999999) and then stops transmitting. Before a retransmission starts, TX performs a backoff. TX waits before it starts transmitting for some amount of time. The amount of time is semi random and is calculated in the eth_random module. Binary Exponential algorithm is used for that purpose. Backoff time is random within predefined limits. This limits increase with the number of collisions.
2.3.4.3 Description of the TX counters module (eth_txcounters.v)
There are three counters in the eth_txcounters module. These counters are only used in the TX modules.
The DlyCrcCnt counter is used when a delayed CRC generation is needed to count
The nibble counter NibCnt count nibbles while ByteCnt counts bytes. Which one of the counters is used depends off the needed resolution.
2.3.4.4 Description of the TX state machine module (eth_txstatem.v)
The TX module has one general state machine that is in the eth_txstatem module. This state machine has eleven states:
StateIdle
StatePreamble
StateData0
StateData1
StatePAD
StateFCS
StateIPG
StateJam
StateJam_q
StateBackOff
StateDefer
After the reset defer state (StateDefer) is activated. After that the state machine goes to the Inter Packet Gap state (StateIPG) and then to the idle state (StateIdle). Why this is so, is not important at the moment.
Lets start with the description after the state machine comes to the idle state. This is the most often used state. When transmitter has nothing to do, it waits in the idle mode for the transmission request. Wishbone Interface (WBI) requests the transmission by setting the TxStartFrm signal to 1 for two clock cycles (together with the first byte of the data that needs to be sent). This forces the state machine (SM) to go to the preamble state (StatePreamble). In the preamble state MTxEn signal is set to 1, informing the Ethernet PHY chip that transmission will start. Together with the MTxEn signal, data signal MTxD is set to the preamble value 0x5. After the preamble is sent (0x5555555), SFD is sent (Start Frame Delimiter (0xd)). After that SM goes to the data0 state (StateData0) and signal TxUsedData is set to inform the WBI to provide next data byte. LSB nibble of the data byte is sent and then SM goes to the data1 state (StateData1), where the MSB nibble of the data byte is sent. SM continues to switch between the data0 and data1 states until the end of the packet. When there is just one byte left to be send, WBI sets the signal TxEndFrm that marks the last byte of the data that needs to be sent.
From here, there are several possibilities:
If the data length is greater or equal to the minimum frame length (value written in the MINFL field of the PACKETLEN register) and CRC is enabled (bit CRCEN in the MODER register is set to 1 or bit CRC of the transmit descriptor is set to 1) then SM goes to the StateFCS state where the 32-bit CRC value, calculated from the data, is appended. Then the SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
If the data length is greater or equal to the minimum frame length (value written in the MINFL field of the PACKETLEN register) and CRC is disabled (bit CRCEN in the MODER register is set to 0 and bit CRC of the transmit descriptor is set to 0) then SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
If the data length is smaller than the minimum frame length (value written in the MINFL field of the PACKETLEN register) and padding is enabled (bit PAD in the MODER register is set to 1 or bit PAD of the transmit descriptor is set to 1), then the SM goes to the pad state (StatePAD) where data is padded with zeros until the minimum frame length is achieved. Then the SM goes to the StateFCS state where the 32-bit CRC value, calculated from the data, is appended. Then the SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
If the data length is smaller than the minimum frame length (value written in the MINFL field of the PACKETLEN register), padding is disabled (bit PAD in the MODER register is set to01 and bit PAD of the transmit descriptor is set to 0) and CRC is enabled (bit CRCEN in the MODER register is set to 1 or bit CRC of the transmit descriptor is set to 1) then the SM goes to the StateFCS state where the 32-bit CRC value, calculated from the data, is appended. Then the SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
If the data length is smaller than the minimum frame length (value written in the MINFL field of the PACKETLEN register), padding is disabled (bit PAD in the MODER register is set to01 and bit PAD of the transmit descriptor is set to 0) and CRC is disabled (bit CRCEN in the MODER register is set to 0 and bit CRC of the transmit descriptor is set to 0) then the SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
2.3.4 Description of the Control module (eth_maccontrol.v)
The Control module is in charge for data flow control, when Ethernet IP Core is in the 100Mbps full duplex operating mode.
Control module consists of multiplexing logic and two sub modules:
eth_transmitcontrol
eth_receivecontrol
Flow control is done by sending and receiving pause control frames.
When the device that is connected to the WISHBONE interface of Ethernet IP Core (usually a processor) cannot process all those packets that it has received (and is still receiving), it requests a pause from the other station that is sending packets. The pause is requested by sending a pause control frame to the other station (see Ethernet IP Core Specification for details about the control frame). As soon as the other station receives pause request, it stops transmitting. The transmission is restarted after the requested pause time passes or pause request is switched off. The transmit flow control is done in the eth_transmitcontrol module. See description of the eth_transmitcontrol module for more details.
When the Ethernet IP Core receives a pause request, it stops transmitting for the requested time. This is done in the eth_receivecontrol module. See description of the eth_receivecontrol module for more details.
Multiplexing logic is used for multiplexing data and control signal used in normal transmission with data and control signals used for control frame transmission (see signals TxUsedDataOut, TxAbortOut, TxDoneOut, TxEndFrmOut, TxStartFrmOut).
When control frames are sent, padding and CRC generation is automatically switched on (see PadOut and CrcEnOut signals).
Insert figure how things are multiplexed
Tu dodaj se opis ce slucajno manjka !!!
2.3.4.1 Description of the CRC (Cyclic Redundancy Check) module (eth_crc.v)
This module is used for CRC calculation. The calculated CRC is appended to the
2.3.5 Description of the Status module (eth_macstatus)
The Status module is in charge for monitoring the Ethernet MAC operations. Module monitors several conditions and after every completed operation (received or sent frame), it writes a status to the related buffer descriptor. Not all statuses are written to the buffer descriptors. See following sections for more details.
Statuses for received frames are normally latched at the end of the reception stage (when signal TakeSample goes to 1). Soon after that statuses are reset (when signal LoadRxStatus goes to 1).
2.3.5.1 Rx Error (LatchedMRxErr)
This error notifies that the PHY detected an error while receiving a frame. In this case frame reception is aborted and no error reported. When invalid symbol is accepted, frame is still received and invalid symbol error reported in the Rx BD.
2.3.5.2 Rx CRC Error (LatchedCrcError)
This error notifies that a frame with invalid CRC was received. Such frame is normally received except that the CRC error status is set in the related Rx BD. If received frame is a control frame (pause frame), then pause timer value is not set.
2.3.5.3 Rx Invalid Symbol (InvalidSymbol)
This error notifies that a frame with invalid symbol was received. Invalid symbol is reported by the PHY when it is operating in the 100 Mbps mode (PHY sets data lines to 0xe when symbol error is detected).
2.3.5.4 Rx Late Collision (RxLateCollision)
When a late collision occurs, frame is normally received and late collision reported in the Rx BD. Late collision reflects the abnormal operation on the Ethernet (should never happen). See COLLCONF register in the Ethernet IP Core Specification for more details about the late collision.
2.3.5.5 Rx Short Frame (ShortFrame)
Short frames are normally (by default) aborted. This means that their appearance is not recorded anywhere. However if their reception is enabled (by setting the RECSMALL bit in the MODER register to 1), then the SF bit is set to 1 in the Rx BD when a short frame appears. Minimum length is defined in the PACKETLEN register in the Ethernet IP Core Specification.
2.3.5.6 Rx Big Frames (ReceivedPacketTooBig)
By default the reception of the big frames is switched off. If frame that is bigger than the maximum frame specified in the PACKETLEN register (See the Ethernet IP Core Specification) is received, then frame reception is automatically stopped at the maximum value (no big frame status is written anywhere). If reception of the big frames is enabled (See HUGEN bit in the MODER register in the Ethernet IP Core Specification), then the TL bit is set in the Rx BD when packet bigger then the maximum size is received.
2.3.5.7 Rx Dribble Nibble (DribbleNibble)
DN bit is set in the Rx BD when an extra nibble is received as a part of the frame (frame is not byte aligned). CRC error occurs at the same time, so both errors are simultaneously reported.
2.3.5.8 Tx Retry Count (RetryCntLatched)
After every frame is transmitted the number of retries is written to the RTRY field of the Tx BD. The retry count gives information about that how many times transmitter retried before successfully transmitting a frame.
2.3.5.9 Tx Retry Limit (RetryLimit)
When a number of retransmission attempts is bigger then specified in the COLLCONF register (see Ethernet IP Core Specification), frame transmission is aborted and bit RL is set in the Tx BD.
2.3.5.10 Tx Late Collision (LateCollLatched)
Late collision should never occur. If it occurs during the frame transmission, the transmission is aborted and LC status is written to the associated Tx BD. See COLLVALID field of the COLLCONF register (Ethernet IP Core Specification) for more information on late collision.
2.3.5.11 Tx Defer (DeferLatched)
When frame was deferred before being sent successfully (i.e. the transmitter had to wait for Carrier Sense before sending because the line was busy), the DF bit is set in the associated Tx BD. This is not a collision indication. Collisions are indicated in RTRY.
2.3.5.12 Tx Carrier Sense Lost (CarrierSenseLost)
When Carrier Sense is lost during a frame transmission, bit CS is set in the associated Tx BD. Status is written after the frame is sent.
Following statuses are not part of the Status Module. They are generated in the Wishbone module and used in the Tx and Rx BD.
2.3.5.13 Tx Underrun (UnderRun)
Underrun is detected in the WISHBONE module and reported in the Tx BD after frame transmission is aborted due to the underrun. This means that the host was not able to provide data is being transmitted on time. This is not a normal condition and should never happen.
2.3.5.14 Rx Overrun (OverRun)
Overrun is detected in the WISHBONE module and reported in the Rx BD. When Overrun status is set, It means that the host was not able to store received data to the memory on time and Rx FIFO overrun happened. Some of the data was lost.
2.3.5.15 Rx Miss (Miss)
When Ethernet MAC is configured to accept all frames regardless of their destination address (PRO bit is set in the MODER register (see Ethernet IP Core Specification)), MISS bit tells if a received frame contains a valid address or not.
Additionally following signals are generated in this module:
ReceivedLengthOK reports when the received frame has a valid length
ReceiveEnd reports the end of the reception. This signal is used in the control module for resetting several flip-flops and setting the pause timer.
Registers
This section describes all base, control, and status registers inside the Ethernet IP Core. The Address field indicates a relative address in hexadecimal. Width specifies the number of bits in the register, and Access specifies the valid access types to that register. RW stands for read and write access, RO for read-only access. A C appended to RW or RO indicates that some or all of the bits are cleared after a read.
Operation
This section describes the Ethernet IP Core operation.
The core consists of five modules:
The host interface connects the Ethernet Core to the rest of the system via the WISHBONE (using DMA transfers). Registers are also part of the host interface.
The TX Ethernet MAC performs transmit functions.
The RX Ethernet MAC performs receive functions.
Architecture
The Ethernet IP Core consists of 5 modules:
Host Interface and the BD structure
TX Ethernet MAC (transmit function)
RX Ethernet MAC (receive function)
MAC Control Module
MII Management Module
TIME \@ "MMMM d, yyyy" August 14, 2002 Ethernet IP Core Design Document
http://www.opencores.org Rev 0.1 Preliminary PAGE ii
HYPERLINK "http://www.opencores.org" http://www.opencores.org Rev 0.1 Preliminary PAGE vi
HYPERLINK "http://www.opencores.org" http://www.opencores.org Rev 0.1 Preliminary PAGE 6 of SECTIONPAGES19
+ - T W ` a I J ^ _ ` a | } ~ ƲΨq )5;CJ OJ QJ aJ mH nH sH$tH$uj{ UmH nH u j UmH nH umH nH u 0J aJ` mH nH u&j >*B*UmH nH ph u 0J mH nH uj 0J UmH nH u ; j ;U 5\ 5CJ mH nH u j U6CJ 5CJ4 '
|
Ethernet IP Core Design Document
Author: Igor Mohor
IgorM@opencores.org
Rev. 0.1
DATE \@ "MMMM d, yyyy" \* MERGEFORMAT August 14, 2002
This page has been intentionally left blank.
Revision History
Rev.DateAuthorDescription0.124/04/02Igor MohorFirst Draft
List of Contents
TOC \o "1-3" \h \z HYPERLINK \l "_Toc17022758" 1 PAGEREF _Toc17022758 \h 1
HYPERLINK \l "_Toc17022759" Introduction PAGEREF _Toc17022759 \h 1
HYPERLINK \l "_Toc17022760" 1.1 Ethernet IP Core Introduction PAGEREF _Toc17022760 \h 1
HYPERLINK \l "_Toc17022761" 1.2 Ethernet IP Core Features PAGEREF _Toc17022761 \h 1
HYPERLINK \l "_Toc17022762" 1.3 Ethernet IP Core Directory Structure PAGEREF _Toc17022762 \h 2
HYPERLINK \l "_Toc17022763" 2 PAGEREF _Toc17022763 \h 5
HYPERLINK \l "_Toc17022764" Ethernet MAC IP Core PAGEREF _Toc17022764 \h 5
HYPERLINK \l "_Toc17022765" 2.1 Overview PAGEREF _Toc17022765 \h 5
HYPERLINK \l "_Toc17022766" 2.1.1 WISHBONE Interface PAGEREF _Toc17022766 \h 5
HYPERLINK \l "_Toc17022767" 2.1.2 Transmit Module PAGEREF _Toc17022767 \h 5
HYPERLINK \l "_Toc17022768" 2.1.3 Receive Module PAGEREF _Toc17022768 \h 5
HYPERLINK \l "_Toc17022769" 2.1.4 Control Module PAGEREF _Toc17022769 \h 6
HYPERLINK \l "_Toc17022770" 2.1.5 MII Module (Media Independent Module) PAGEREF _Toc17022770 \h 6
HYPERLINK \l "_Toc17022771" 2.2 Core File Hierarchy PAGEREF _Toc17022771 \h 6
HYPERLINK \l "_Toc17022772" 2.3 Description of Core Modules PAGEREF _Toc17022772 \h 8
HYPERLINK \l "_Toc17022773" 2.3.1 Description of the MII (eth_miim.v) module PAGEREF _Toc17022773 \h 8
HYPERLINK \l "_Toc17022774" 2.3.2 Description of the Receive module (eth_rxethmac.v) PAGEREF _Toc17022774 \h 11
HYPERLINK \l "_Toc17022775" 2.3.3 Description of the Transmit module (eth_txethmac.v) PAGEREF _Toc17022775 \h 15
HYPERLINK \l "_Toc17022776" 2.3.4 Description of the Control module (eth_maccontrol.v) PAGEREF _Toc17022776 \h 4
HYPERLINK \l "_Toc17022777" 2.3.5 Description of the Status module (eth_macstatus) PAGEREF _Toc17022777 \h 6
HYPERLINK \l "_Toc17022778" 3 PAGEREF _Toc17022778 \h 7
HYPERLINK \l "_Toc17022779" Registers PAGEREF _Toc17022779 \h 7
HYPERLINK \l "_Toc17022780" 4 PAGEREF _Toc17022780 \h 8
HYPERLINK \l "_Toc17022781" Operation PAGEREF _Toc17022781 \h 8
HYPERLINK \l "_Toc17022782" 5 PAGEREF _Toc17022782 \h 9
HYPERLINK \l "_Toc17022783" Architecture PAGEREF _Toc17022783 \h 9
List of Tables
TOC \h \z \t "Caption,1" Error! No table of contents entries found.
List of Figures
TOC \h \z \t "Caption 1,1" Error! No table of contents entries found.
Introduction
1.1 Ethernet IP Core Introduction
The Ethernet IP Core is a MAC (Media Access Controller). It connects to the Ethernet PHY chip on one side and to the WISHBONE SoC bus on the other. The core has been designed to offer as much flexibility as possible to all kinds of applications.
The chapter 2 describes file hierarchy, description of modules, core design considerations and constants regarding the Ethernet IP Core.
The chapter 3 describes test bench file hierarchy, description of modules, test bench design considerations, description of test cases and constants regarding the test bench.
1.2 Ethernet IP Core Features
The following lists the main features of the Ethernet IP core.
Performing MAC layer functions of IEEE 802.3 and Ethernet
Automatic 32-bit CRC generation and checking
Delayed CRC generation
Preamble generation and removal
Automatically pad short frames on transmit
Detection of too long or too short packets (length limits)
Possible transmission of packets that are bigger than standard packets.
Full duplex support
10 and 100 Mbps bit rates supported
Automatic packet abortion on Excessive deferral limit, too small inter packet gap, when enabled
Flow control and automatic generation of control frames in full duplex mode (IEEE 802.3x)
Collision detection and auto retransmission on collisions in half duplex mode (CSMA/CD protocol)
Complete status for TX/RX packets
IEEE 802.3 Media Independent Interface (MII)
WISHBONE SoC Interconnection Rev. B compliant interface
Internal RAM for holding 128 TX/RX buffer descriptors
Interrupt generation an all events
1.3 Ethernet IP Core Directory Structure
Following picture shows the structure of directories of the Ethernet IP core.
There are three major parts of the Verilog code in the ethernet directory. First one is the code for the Ethernet MAC IP core. The Verilog files are in the ethernet\rtl\verilog subdirectory. The second one is the code for the Ethernet MAC Testbench. These files are used together with files for the Ethernet MAC. There are also some exceptions, but those will be mentioned later. The Verilog files are in the ethernet\bench\verilog subdirectory.
The documentation is in the subdirectory ethernet\doc. Documentation consists of Ethernet IP Core Data Sheet, Ethernet IP Core Specification and Ethernet IP Core Design document.
ethernet\sim subdirectory is used for running simulation testbench. The rtl_sim subdirectory
is used for RTL ( functional ) simulation of the core. There are a few directories included
here:
bin includes various scripts needed for running Ncsim simulator
run the directory from which the simulation is ran. It provides a script for starting the simulation and a script for cleaning all the results produced by previous simulation runs
log Ncvlog, Ncelab and Ncsim log files are stored here for review.
out simulation output directory simulation stores all the results into this directory ( dump files for viewing with Signalscan, testbench text output etc. )
The gate_sim directory is used the same way as rtl_sim, except simulation is run with the netlist provided from synthesis tool.
Generated files from synthesis tools, like gate level Verilog and log files, are stored in the ethernet\syn subdirectory and its subdirectories.
Ethernet MAC IP Core
2.1 Overview
The Ethernet MAC IP Core consists of seven main units: WISHBONE interface, transmit module, receive module, control module, MII module, status module and register module. Many of these modules have sub-modules. Module and sub-module operations are described later in this section.
2.1.1 WISHBONE Interface
Consists of both master and slave interfaces and connects the core to the WISHBONE bus. Master interface is used for storing the received data frames to the memory and loading the data that needs to be sent from the memory to the Ethernet core. Interface is WISHBONE Revision B.1 compatible.
2.1.2 Transmit Module
Performs all transmitting related operations (preamble generation, padding, CRC, etc.).
2.1.3 Receive Module
Performs all reception related operations (preamble removal, CRC check, etc).
2.1.4 Control Module
Performs all flow control related operations when Ethernet is used in full duplex mode.
2.1.5 MII Module (Media Independent Module)
Provides a Media independent interface to the external Ethernet PHY chip.
2.1.6 Status Module
dqweq
2.2 Core File Hierarchy
The hierarchy of modules in the Ethernet core is shown here with file tree. Each file implements one module in a hierarchy. RTL source files of the Ethernet core are in the ethernet\rtl\verilog subdirectory.
ethernet
. sim
. . rtl_sim
. . . src
. . . run
. rtl
. . verilog
. . . eth_top.v
. . . eth_crc.v
. . . eth_defines.v.bak
. . . eth_miim.v
. . . eth_defines.v
. . . timescale.v
. . . eth_random.v
. . . eth_fifo.v
. . . eth_wishbone.v
. . . eth_maccontrol.v
. . . eth_crc.v.bak
. . . eth_rxaddrcheck.v
. . . eth_txstatem.v
. . . eth_transmitcontrol.v
. . . eth_txethmac.v
. . . generic_spram.v
. . . eth_rxcounters.v
. . . eth_rxstatem.v
. . . eth_outputcontrol.v
. . . eth_register.v
. . . eth_receivecontrol.v
. . . eth_registers.v
. . . eth_shiftreg.v
. . . eth_txcounters.v
. . . eth_clockgen.v
. . . eth_rxethmac.v
. . . eth_macstatus.v
. doc
. . eth_speci.pdf
. . eth_design_document.pdf
. . Ethernet Datasheet (prl.).pdf
. . src
. . . eth_speci.doc
. . . eth_design_document.doc
. . . Ethernet Datasheet (prl.).doc
. bench
. . verilog
. . . tb_eth_top.v
2.3 Description of Core Modules
The module eth_top.v consists of sub modules eth_miim.v, eth_registers.v, eth_maccontrol.v, eth_txethmac.v, eth_rxethmac.v, eth_wishbone.v, eth_macstatus.v and some logic for synchronizing, multiplexing and registering outputs.
Put a figure here !!!
2.3.1 Description of the MII (eth_miim.v) module
The MII module (Media Independent Interface) is an interface to the external Ethernet PHY chip. It is used for setting PHYs configuration registers and reading status from it. The interface consists of only two signals: clock (MDC) and bi-directional data signal (MDIO). Bi-directional MDIO signal needs to be combined from input signal Mdi, output signal Mdo, and enable signal MdoEn in additional module. This is done because the same Ethernet core will be implemented in both ASIC and FPGA.
The MII module is the top module for the MII and consists of several sub modules (eth_clockgen.v, eth_shiftreg.v, eth_outputcontrol.v) and additional logic. This logic is used for generating number of signals:
Synchronized request for write (WriteDataOp), read (ReadStatusOp) and scan (ScanStatusOp) operations.
Signal for updating the MIIRX_DATA register (UpdateMIIRX_DATAReg)
Counter (BitCounter) is the primary counter for the MII Interface (many operations depend on it.
Byte select signals used when data is shifted out (ByteSelect [3:0]).
Signals used for latching the input data (LatchByte [1:0]).
When there is a need to read or write the data from the PHY chip, several operations need to be performed:
MIIMODER register needs to be set:
Clock divider needs to be set to provide clock signal Mdc of the appropriate frequency (read PHY documentation to obtain the value of the Mdc frequency)
Preamble generation might be disabled (if PHY supports transmissions without the preamble). By default 32-bit preamble is transmitted.
MII Module might be reset prior to its usage.
PHY Address (several PHY chips might be connected to the MII interface) and address of the register within the selected PHY chip need to be set in the MIIADDRESS register.
If there is a need to write data to the selected register, data needs to be written to the MIITX_DATA register.
Writing appropriate value to the MIICOMMAND register starts requested operation.
If Read status or Scan status operation were requested than the value that was received from the PHY can be read from the MIIRX_DATA register.
MIISTATUS register reflects the status of the MII module. The LinkFail status is cleared only after the read to the PHYs status register (address 0x1) returns status that is OK.
2.3.2.1 Description of the eth_outputcontrol module
This module performs two tasks:
Generates MII serial output signal (Mdo)
Generates enable signal (MdoEn) for the Mdo.
Since the MII serial data signal is a bi-directional signal, these two signals need to be combined together with the MII serial input signal (Mdi) in additional module that is not part of the Ethernet MAC IP Core.
The eth_outputcontrol module also generates the MII preamble. When MII preamble is enabled (bit 8 in the MIIMODER register set to 0), 32-bit preamble is transmitted prior to the data.
2.3.2.2 Description of the eth_clockgen module
The eth_clockgen module is used for:
Generating MII clock signal (Mdc). This is output clock signal used for clocking the MII interface of the Ethernet PHY chip. You should read the specification for the used PHY chip to properly set the Mdc frequency (usually frequencies up to 10 MHz can be used)
Generating MdcEn signal. This signal is an enable signal. All flip-flops used in the MII are clocked with the high frequency clock Clk. The reduced frequency (equal to Mdc) is obtained by using the MdcEn signal.
Mdc is obtained by dividing the Clk signal with the value that is written in the MIIMODER register (any value within range [1:255]).
2.3.2.3 Description of the eth_shiftreg module
The eth_shiftreg module is used for:
Serialize the data that goes towards Ethernet PHY chip (Mdo)
Parallelize input data that comes from Ethernet PHY chip (Mdi) and temporally store it to the Prsd register. This value is then stored to the MIIRX_DATA register.
Generating LinkFail signal (bit 0 of the MIISTATUS register reflects its value).
2.3.2 Description of the Receive module (eth_rxethmac.v)
The Receive module is in charge for receiving data. External PHY chip receives serial data from the physical layer (cable), assembles it to nibbles and sends to the receive module (MRxD [3:0]) together with the data valid marker (MRxDV). The receive module then assembles this data nibbles to data bytes, and sends them to the WISHBONE interface module together with few signals that mark start and end of the data. Receive module also removes the preamble and the CRC.
The Receive module consists of four sub modules:
eth_crc Cyclic Redundancy Check (CRC) module
eth_rxaddrcheck Address recognition module
eth_rxcounters Various counters needed for packet reception
eth_rxstatem State machine for Receive module
Besides the above sub modules, eth_rxethmac module also consists of logic that is used for:
Generating CrcHash value and CrcHashGood marker that are used in address recognition system.
Latching the data that is received from the PHY chip (RxData).
Generating Broadcast and Multicast marker (when packets with broadcast or multicast destination address are received).
Generating RxValid, RxStartFrm, RxEndFrm signals that are marking valid data.
Receiver can operate in various modes. For that reason number of registers need to be configured prior to Receivers use.
Signals related to the receiver operation are:
HugEn Reception of big packets is enabled (packets, bigger than the standard Ethernet packets). When HugEn is disabled, packets that smaller or equal to MaxFL and bigger or equal to MinFL are received. (MaxFL and MinFL are set in the PACKETLEN register).
DlyCrcEn Delayed CRC (Cyclic Redundancy Check) is enabled. CRC checking starts 4 bytes after the data becomes valid. This option is useful when additional data is added to the data frame.
r_IFG Minimum Inter Frame Gap Enable. When this signal is set to zero, minimum inter frame gap is required between two packets. After this time receiver starts with reception again. When r_IFG is set to 1, no inter packet gap is needed. All frames are received regardless to the IFG.
r_Pro, r_Bro, r_Iam and registers MAC, HASH0 and HASH1 are used for address recognition.
2.3.3.1 Description of the CRC (Cyclic Redundancy Check) module (eth_crc.v)
This module is used for validating the correctness of the incoming packet by checking the CRC value of the packet. CRC module is also used for the CRC generation for the TX module.
To better understand the CRC checking, here is a brief description how CRC is send and checked.
Before a transmitter sends the data, it appends the CRC (this CRC is calculated from the data) to it. This means that the packet is now bigger for 4 bytes. Receiver receives this data (that also includes the CRC of the data) and calculates a new CRC value from it (received CRC is also used for the CRC calculation). If the new CRC differs from the CRC Magic Number (0xc704dd7b), then received data differs from the sent data and CrcError signal is set.
2.3.3.2 Description of the address recognition module (eth_rxaddrcheck.v)
The address recognition module decides whether the packet will be received or not. Ethernet IP core starts receiving all packets regardless to their destination address. Destination address is then checked in the eth_rxaddrcheck sub module. Frame reception depends on few conditions:
If r_Pro bit is set in the MODER register (Promiscuous mode), then all frames are received regardless to their destination address. If r_Pro bit is cleared then destination address is checked.
If r_Bro bit is set in the MODER register then all frames containing broadcast addresses are rejected (r_Pro must be cleared).
MAC MAC address of the used Ethernet MAC IP Core. This is individual address of the used Ethernet core. When r_Pro bit is cleared then every destination address is compared to the MAC address. Frame is accepted only when two address match.
When r_Iam signal is set then besides checking the MAC address, hash table algorithm is used. The Ethernet controller maps any 48-bit address into one of 64 bits. If that bit is set in the HASH registers (HASH0 and r_HASH1 are making one 64-bit hash register), then frame is accepted.
As said before, packet reception always starts regardless of the destination address of the incoming packet. As soon as the destination address is received, it is checked if it matches with any of the above-mentioned conditions. If the match doesnt occur than the reception of the whole packet is aborted (signal RxAbort is set to 1). The packet is not written to the memory and receive buffer is flushed.
2.3.3.3 Description of the rxcounters module (eth_rxcounters.v)
The module consists of three counters, which are:
ByteCnt generally used counter in the receive module.
IFGCounter used for counting the IFG (inter frame gap)
DlyCrcCnt counter, used when delayed CRC operation is enabled.
Besides that a number of comparators are in this module, used for various purposes.
2.3.3.4 Description of the rxstatem module (eth_rxstatem.v)
There is just one state machine used in the receive module of the Ethernet IP core. This module is placed in the eth_rxstatem sub-module.
The state machine has six different states:
Idle state
Drop state
Preamble state
SFD (standard frame delimiter) state
Data 0 state
Data 1 state
State machine (SM) goes to the drop state (StateDrop) after the reset and immediately after that to the idle state (StateIdle) because MRxDV is set to 0. As soon as there is a valid data available on the PHYs data lines (MRxD), PHY informs receiver about that by setting the MRxDV signal to one.
Normally receiver expects preamble at the beginning of each packet. Standard preamble is 7 byte long (0xee). After that a one-byte SFD (start frame delimiter) is expected (0xde). If we put this together, then sample 0xdeeeeeee is expected (LSB received first).
Because the Ethernet IP core can also accept packets that dont have a standard 7-byte preamble but only the SFD, receivers SM waits for the first 0x5 nibble (it is not important whether this nibble is part of the preamble or of the SFD). If the received character differs from the expected nibble, then the SM goes to the preamble state (StatePreamble) and remains there until the correct nibble (0x5) is received. Once the 0x5 nibble is received, SM goes to the SFD state (StateSFD) where it waits for the 0xd nibble.
From here two things, depending on the value of the IFGCounterEq24 signal, may occur (next paragraph describes IFGCounterEq24 signal). If IFGCounterEq24 is set then:
SM goes to the data0 state (StateData0) where lower data nibble is received and then to the data1 state (StateData1) where higher data nibble is received. SM goes back to the data0 state. SM continues going from data state 0 to data state 1 and vice versa until whole data packet is received and end of packet is detected (PHY clears the MRxDV signal). Once the data valid signal is cleared, SM goes to the idle state (StateIdle) and everything starts again.
else (IFGCounterEq24 is cleared)
SM goes to the drop state (StateDrop) and remains there until the end of valid data is reported (PHY clears the MRxDV signal). After that SM goes to the idle state (StateIdle) and everything starts again.
Signal IFGCounterEq24 is used for detecting the proper gap between two consecutive received frames (Inter Frame Gap). By the standard this gap must be at least 960 ns for 100 Mbps mode or 9600ns for 10 Mbps mode. If the gap is appropriate (equal or greater than requested), then IFGCounterEq24 is set to 1. Signal IFGCounterEq24 is also set to 1, when IFG bit in the MODER register is set (minimum inter frame gap is not checked). If the IFG gap between two frames is too small, frame wont be accepted but dropped.
2.3.3 Description of the Transmit module (eth_txethmac.v)
The Transmit module (TX) is in charge for transmitting data. TX module gets data that needs to be transmitted from WISHBONE interface (WBI) module in the byte form. Besides that it also receives signals that mark start of the data frame (TxStartFrm) and end of the data frame (TxEndFrm). As soon as the TX module needs next data byte, it sets the TxUsedData and WBI module provides the next byte.
TX module sets number of signals to inform WBI module on one side and Ethernet PHY chip on the other about the operation status (done, retry, abort, error, etc.).
The Transmit module consists of four sub modules:
eth_crc Cyclic Redundancy Check (CRC) module generates 32-bit CRC that is appended to the data field.
eth_random Generates random delay that is needed when back off is performed (after the collision)
eth_txcounters Various counters needed for packet transmission
eth_txstatem State machine for TX module
Signals, connected to the Ethernet PHY chip are:
Data nibble MTxD. This is the data that will be sent on the Ethernet by the PHY.
Transmit enable MTxEn tells PHY that data MTxD is valid and transmission should start.
Transmit error MTxErr tells PHY that an error happened during the transmission.
Signals, connected to the upper layer module (WBI module) are:
Transmit packet done TxDone (see next paragraph)
Transmit packet retry TxRetry (see next paragraph)
Transmit packet abort TxAbort (see next paragraph)
TxUsedData;
Every transmission ends in one of the following ways:
Transmission is successfully finished. Signal TxDone is set.
Transmission needs to be repeated. Signal TxRetry is set. This happens when a normal collision occurs (in half-duplex mode).
Transmission is aborted. Signal TxAbort is set. This happens in the following situations:
Packet is too big (bigger than the max. packet (See MAXFL field of the PACKETLEN register)).
Underrun occurs (WBI module can not provide data on time).
Excessive deferral occurs (TX state machine remains in the defer state for too long).
Late collision occurs (late collision is every collision that happens later than COLLVALID bytes after the preamble (See COLLCONF register)).
Maximum number of collisions happens (See MAXRET field of the COLLCONF register).
Besides all previously mentioned signals, TX module provides other signals:
WillTransmit notifies the receiver that transmitter will start transmitting. Receiver stops receiving until WillTransmit is cleared.
Generating the collision reset signal (collision detected asynchronously comes from the PHY chip and is synchronized to the TX clock signal). ResetCollision signal is used to reset synchronizing flip-flop.
Collision window ColWindow marks a window within every collision is treated as a valid (regular) collision. After a collision packet is retransmitted. Every collision that occurs after that is a late collision (packets with late collision are aborted).
Retry counter RetryCnt.
Data_Crc, Enable_Crc and Initialize_Crc that are used for CRC generation.
2.3.4.1 Description of the CRC (Cyclic Redundancy Check) module (eth_crc.v)
This module is used for CRC calculation. The calculated CRC is appended to the data frame. This module is also used in the RX module for CRC checking.
2.3.4.2 Description of the random module (eth_random.v)
When a collision occurs, TX module first sends a jam pattern (0x99999999) and then stops transmitting. Before a retransmission starts, TX performs a backoff. TX waits before it starts transmitting for some amount of time. The amount of time is semi random and is calculated in the eth_random module. Binary Exponential algorithm is used for that purpose. Backoff time is random within predefined limits. This limits increase with the number of collisions.
2.3.4.3 Description of the TX counters module (eth_txcounters.v)
There are three counters in the eth_txcounters module. These counters are only used in the TX modules.
The DlyCrcCnt counter is used when a delayed CRC generation is needed to count
The nibble counter NibCnt count nibbles while ByteCnt counts bytes. Which one of the counters is used depends off the needed resolution.
2.3.4.4 Description of the TX state machine module (eth_txstatem.v)
The TX module has one general state machine that is in the eth_txstatem module. This state machine has eleven states:
StateIdle
StatePreamble
StateData0
StateData1
StatePAD
StateFCS
StateIPG
StateJam
StateJam_q
StateBackOff
StateDefer
After the reset defer state (StateDefer) is activated. After that the state machine goes to the Inter Packet Gap state (StateIPG) and then to the idle state (StateIdle). Why this is so, is not important at the moment.
Lets start with the description after the state machine comes to the idle state. This is the most often used state. When transmitter has nothing to do, it waits in the idle mode for the transmission request. Wishbone Interface (WBI) requests the transmission by setting the TxStartFrm signal to 1 for two clock cycles (together with the first byte of the data that needs to be sent). This forces the state machine (SM) to go to the preamble state (StatePreamble). In the preamble state MTxEn signal is set to 1, informing the Ethernet PHY chip that transmission will start. Together with the MTxEn signal, data signal MTxD is set to the preamble value 0x5. After the preamble is sent (0x5555555), SFD is sent (Start Frame Delimiter (0xd)). After that SM goes to the data0 state (StateData0) and signal TxUsedData is set to inform the WBI to provide next data byte. LSB nibble of the data byte is sent and then SM goes to the data1 state (StateData1), where the MSB nibble of the data byte is sent. SM continues to switch between the data0 and data1 states until the end of the packet. When there is just one byte left to be send, WBI sets the signal TxEndFrm that marks the last byte of the data that needs to be sent.
From here, there are several possibilities:
If the data length is greater or equal to the minimum frame length (value written in the MINFL field of the PACKETLEN register) and CRC is enabled (bit CRCEN in the MODER register is set to 1 or bit CRC of the transmit descriptor is set to 1) then SM goes to the StateFCS state where the 32-bit CRC value, calculated from the data, is appended. Then the SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
If the data length is greater or equal to the minimum frame length (value written in the MINFL field of the PACKETLEN register) and CRC is disabled (bit CRCEN in the MODER register is set to 0 and bit CRC of the transmit descriptor is set to 0) then SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
If the data length is smaller than the minimum frame length (value written in the MINFL field of the PACKETLEN register) and padding is enabled (bit PAD in the MODER register is set to 1 or bit PAD of the transmit descriptor is set to 1), then the SM goes to the pad state (StatePAD) where data is padded with zeros until the minimum frame length is achieved. Then the SM goes to the StateFCS state where the 32-bit CRC value, calculated from the data, is appended. Then the SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
If the data length is smaller than the minimum frame length (value written in the MINFL field of the PACKETLEN register), padding is disabled (bit PAD in the MODER register is set to01 and bit PAD of the transmit descriptor is set to 0) and CRC is enabled (bit CRCEN in the MODER register is set to 1 or bit CRC of the transmit descriptor is set to 1) then the SM goes to the StateFCS state where the 32-bit CRC value, calculated from the data, is appended. Then the SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
If the data length is smaller than the minimum frame length (value written in the MINFL field of the PACKETLEN register), padding is disabled (bit PAD in the MODER register is set to01 and bit PAD of the transmit descriptor is set to 0) and CRC is disabled (bit CRCEN in the MODER register is set to 0 and bit CRC of the transmit descriptor is set to 0) then the SM goes to the defer state (StateDefer), then to the Inter Packet Gap state (StateIPG) and from there to the idle state (StateIdle) where everything starts again.
2.3.4 Description of the Control module (eth_maccontrol.v)
The Control module is in charge for data flow control, when Ethernet IP Core is in the 100Mbps full duplex operating mode.
Control module consists of multiplexing logic and two sub modules:
eth_transmitcontrol
eth_receivecontrol
Flow control is done by sending and receiving pause control frames.
When the device that is connected to the WISHBONE interface of Ethernet IP Core (usually a processor) cannot process all those packets that it has received (and is still receiving), it requests a pause from the other station that is sending packets. The pause is requested by sending a pause control frame to the other station (see Ethernet IP Core Specification for details about the control frame). As soon as the other station receives pause request, it stops transmitting. The transmission is restarted after the requested pause time passes or pause request is switched off. The transmit flow control is done in the eth_transmitcontrol module. See description of the eth_transmitcontrol module for more details.
When the Ethernet IP Core receives a pause request, it stops transmitting for the requested time. This is done in the eth_receivecontrol module. See description of the eth_receivecontrol module for more details.
Multiplexing logic is used for multiplexing data and control signal used in normal transmission with data and control signals used for control frame transmission (see signals TxUsedDataOut, TxAbortOut, TxDoneOut, TxEndFrmOut, TxStartFrmOut).
When control frames are sent, padding and CRC generation is automatically switched on (see PadOut and CrcEnOut signals).
Insert figure how things are multiplexed
Tu dodaj se opis ce slucajno manjka !!!
2.3.4.1 Description of the CRC (Cyclic Redundancy Check) module (eth_crc.v)
This module is used for CRC calculation. The calculated CRC is appended to the
2.3.5 Description of the Status module (eth_macstatus)
The Status module is in charge for monitoring the Ethernet MAC operations. Module monitors several conditions and after every completed operation (received or sent frame), it writes a status to the related buffer descriptor. Not all statuses are written to the buffer descriptors. See following sections for more details.
Statuses for received frames are normally latched at the end of the reception stage (when signal TakeSample goes to 1). Soon after that statuses are reset (when signal LoadRxStatus goes to 1).
2.3.5.1 Rx Error (LatchedMRxErr)
This error notifies that the PHY detected an error while receiving a frame. In this case frame reception is aborted and no error reported. When invalid symbol is accepted, frame is still received and invalid symbol error reported in the Rx BD.
2.3.5.2 Rx CRC Error (LatchedCrcError)
This error notifies that a frame with invalid CRC was received. Such frame is normally received except that the CRC error status is set in the related Rx BD. If received frame is a control frame (pause frame), then pause timer value is not set.
2.3.5.3 Rx Invalid Symbol (InvalidSymbol)
This error notifies that a frame with invalid symbol was received. Invalid symbol is reported by the PHY when it is operating in the 100 Mbps mode (PHY sets data lines to 0xe when symbol error is detected).
2.3.5.4 Rx Late Collision (RxLateCollision)
When a late collision occurs, frame is normally received and late collision reported in the Rx BD. Late collision reflects the abnormal operation on the Ethernet (should never happen). See COLLCONF register in the Ethernet IP Core Specification for more details about the late collision.
2.3.5.5 Rx Short Frame (ShortFrame)
Short frames are normally (by default) aborted. This means that their appearance is not recorded anywhere. However if their reception is enabled (by setting the RECSMALL bit in the MODER register to 1), then the SF bit is set to 1 in the Rx BD when a short frame appears. Minimum length is defined in the PACKETLEN register in the Ethernet IP Core Specification.
2.3.5.6 Rx Big Frames (ReceivedPacketTooBig)
By default the reception of the big frames is switched off. If frame that is bigger than the maximum frame specified in the PACKETLEN register (See the Ethernet IP Core Specification) is received, then frame reception is automatically stopped at the maximum value (no big frame status is written anywhere). If reception of the big frames is enabled (See HUGEN bit in the MODER register in the Ethernet IP Core Specification), then the TL bit is set in the Rx BD when packet bigger then the maximum size is received.
2.3.5.7 Rx Dribble Nibble (DribbleNibble)
DN bit is set in the Rx BD when an extra nibble is received as a part of the frame (frame is not byte aligned). CRC error occurs at the same time, so both errors are simultaneously reported.
2.3.5.8 Tx Retry Count (RetryCntLatched)
After every frame is transmitted the number of retries is written to the RTRY field of the Tx BD. The retry count gives information about that how many times transmitter retried before successfully transmitting a frame.
2.3.5.9 Tx Retry Limit (RetryLimit)
When a number of retransmission attempts is bigger then specified in the COLLCONF register (see Ethernet IP Core Specification), frame transmission is aborted and bit RL is set in the Tx BD.
2.3.5.10 Tx Late Collision (LateCollLatched)
Late collision should never occur. If it occurs during the frame transmission, the transmission is aborted and LC status is written to the associated Tx BD. See COLLVALID field of the COLLCONF register (Ethernet IP Core Specification) for more information on late collision.
2.3.5.11 Tx Defer (DeferLatched)
When frame was deferred before being sent successfully (i.e. the transmitter had to wait for Carrier Sense before sending because the line was busy), the DF bit is set in the associated Tx BD. This is not a collision indication. Collisions are indicated in RTRY.
2.3.5.12 Tx Carrier Sense Lost (CarrierSenseLost)
When Carrier Sense is lost during a frame transmission, bit CS is set in the associated Tx BD. Status is written after the frame is sent.
Following statuses are not part of the Status Module. They are generated in the Wishbone module and used in the Tx and Rx BD.
2.3.5.13 Tx Underrun (UnderRun)
Underrun is detected in the WISHBONE module and reported in the Tx BD after frame transmission is aborted due to the underrun. This means that the host was not able to provide data is being transmitted on time. This is not a normal condition and should never happen.
2.3.5.14 Rx Overrun (OverRun)
Overrun is detected in the WISHBONE module and reported in the Rx BD. When Overrun status is set, It means that the host was not able to store received data to the memory on time and Rx FIFO overrun happened. Some of the data was lost.
2.3.5.15 Rx Miss (Miss)
When Ethernet MAC is configured to accept all frames regardless of their destination address (PRO bit is set in the MODER register (see Ethernet IP Core Specification)), MISS bit tells if a received frame contains a valid address or not.
Additionally following signals are generated in this module:
ReceivedLengthOK reports when the received frame has a valid length
ReceiveEnd reports the end of the reception. This signal is used in the control module for resetting several flip-flops and setting the pause timer.
Registers
This section describes all base, control, and status registers inside the Ethernet IP Core. The Address field indicates a relative address in hexadecimal. Width specifies the number of bits in the register, and Access specifies the valid access types to that register. RW stands for read and write access, RO for read-only access. A C appended to RW or RO indicates that some or all of the bits are cleared after a read.
Operation
This section describes the Ethernet IP Core operation.
The core consists of five modules:
The host interface connects the Ethernet Core to the rest of the system via the WISHBONE (using DMA transfers). Registers are also part of the host interface.
The TX Ethernet MAC performs transmit functions.
The RX Ethernet MAC performs receive functions.
Architecture
The Ethernet IP Core consists of 5 modules:
Host Interface and the BD structure
TX Ethernet MAC (transmit function)
RX Ethernet MAC (receive function)
MAC Control Module
MII Management Module
TIME \@ "MMMM d, yyyy" August 14, 2002 Ethernet IP Core Design Document
http://www.opencores.org Rev 0.1 Preliminary PAGE ii
HYPERLINK "http://www.opencores.org" http://www.opencores.org Rev 0.1 Preliminary PAGE vi
HYPERLINK "http://www.opencores.org" http://www.opencores.org Rev 0.1 Preliminary PAGE 6 of SECTIONPAGES19
+ - T W ` a I J ^ _ ` a | } ~ ƲΨq )5;CJ OJ QJ aJ mH nH sH$tH$uj{ UmH nH u j UmH nH umH nH u 0J aJ` mH nH u&j >*B*UmH nH ph u 0J mH nH uj 0J UmH nH u ; j ;U 5\ 5CJ mH nH u j U6CJ 5CJ4 '
|
+ , - @ T U V W ` $
f!a$ $If ! &
+ I C C C C $If $$If l 4 \ 3
! c
|
+ , - @ T U V W ` $
f!a$ $If ! &
+ I C C C C $If $$If l 4 \ 3
! c
|
|
|
t ( & & & & 0 4
|
t ( & & & & 0 4
|
l `
|
l `
|
al + , - . / 0 K E E E E $If $$If l \ 3
! c
|
al + , - . / 0 K E E E E $If $$If l \ 3
! c
|
|
|
t ( 0 4
|
t ( 0 4
|
l `
|
l `
|
al 0 1 2 3 4 5 6 7 K E E E E K C $If $$If l \ 3
! c
|
al 0 1 2 3 4 5 6 7 K E E E E K C $If $$If l \ 3
! c
|
|
|
t ( 0 4
|
t ( 0 4
|
l `
|
l `
|
al 7 I P Y U U
|
al 7 I P Y U U
|
{
|
{
|
|
|
f \
_
-
!
|
f \
_
-
!
|
!
|
!
|
!
|
!
|
!
|
!
|
/ 0 1 J K L M N O P Q R m ͳߞߖ|rdPߖ &;CJ OJ QJ aJ mH nH sH$tH$u jg UmH nH u 0J aJ$ mH nH u&j >*B*UmH nH ph u mH nH u0J mH nH u)5;CJ OJ QJ aJ mH nH sH$tH$ujq UmH nH u j UmH nH umH nH u 0J aJH mH nH uj 0J UmH nH u &j >*B*UmH nH ph u m n o p 4 5 6 7 ĸĪĸ֖|ĸnĸ֖Z &j >*B*UmH nH ph u jS UmH nH u &j >*B*UmH nH ph u mH nH u&;CJ OJ QJ aJ mH nH sH$tH$u j] UmH nH u j UmH nH umH nH u 0J aJ$ mH nH uj 0J UmH nH u &j >*B*UmH nH ph u 0J mH nH u #7 8 9 : S T U V W X Y Z [ v w x y ƱƩƅwƱƩcY 0J aJ$ mH nH u&j >*B*UmH nH ph u j? UmH nH u 0J aJH mH nH u&j >*B*UmH nH ph u mH nH u0J mH nH u)5;CJ OJ QJ aJ mH nH sH$tH$uj 0J UmH nH u jI UmH nH u j UmH nH umH nH u 0J aJ` mH nH u ! 4 5 6 O P Q R S T U V W r s t u γ쬩 s e j >*B*Uph #5CJ OJ QJ aJ mH nH sH$tH$j+ U j U 0J aJ j >*B*Uph 0J
j 0J Uj 0J UmH nH u j5 UmH nH u j UmH nH umH nH u 0J aJ$ mH nH u&;CJ OJ QJ aJ mH nH sH$tH$u% 4 5 6 O P Q R S T U V W r s t u ҩ ғ j Uj >*B*Uph j
Uj
|
/ 0 1 J K L M N O P Q R m ͳߞߖ|rdPߖ &;CJ OJ QJ aJ mH nH sH$tH$u jg UmH nH u 0J aJ$ mH nH u&j >*B*UmH nH ph u mH nH u0J mH nH u)5;CJ OJ QJ aJ mH nH sH$tH$ujq UmH nH u j UmH nH umH nH u 0J aJH mH nH uj 0J UmH nH u &j >*B*UmH nH ph u m n o p 4 5 6 7 ĸĪĸ֖|ĸnĸ֖Z &j >*B*UmH nH ph u jS UmH nH u &j >*B*UmH nH ph u mH nH u&;CJ OJ QJ aJ mH nH sH$tH$u j] UmH nH u j UmH nH umH nH u 0J aJ$ mH nH uj 0J UmH nH u &j >*B*UmH nH ph u 0J mH nH u #7 8 9 : S T U V W X Y Z [ v w x y ƱƩƅwƱƩcY 0J aJ$ mH nH u&j >*B*UmH nH ph u j? UmH nH u 0J aJH mH nH u&j >*B*UmH nH ph u mH nH u0J mH nH u)5;CJ OJ QJ aJ mH nH sH$tH$uj 0J UmH nH u jI UmH nH u j UmH nH umH nH u 0J aJ` mH nH u ! 4 5 6 O P Q R S T U V W r s t u γ쬩 s e j >*B*Uph #5CJ OJ QJ aJ mH nH sH$tH$j+ U j U 0J aJ j >*B*Uph 0J
j 0J Uj 0J UmH nH u j5 UmH nH u j UmH nH umH nH u 0J aJ$ mH nH u&;CJ OJ QJ aJ mH nH sH$tH$u% 4 5 6 O P Q R S T U V W r s t u ҩ ғ j Uj >*B*Uph j
Uj
|
>*B*Uph j
|
>*B*Uph j
|
U0J aJ j >*B*Uph 0J #5CJ OJ QJ aJ mH nH sH$tH$
j 0J U j U j! U 6
|
U0J aJ j >*B*Uph 0J #5CJ OJ QJ aJ mH nH sH$tH$
j 0J U j U j! U 6
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
7
|
7
|
8
|
8
|
9
|
9
|
:
|
:
|
>
|
>
|
?
|
?
|
Z
|
Z
|
[
|
[
|
\
|
\
|
u
|
u
|
v
|
v
|
w
|
w
|
x
|
x
|
y
|
y
|
z
|
z
|
{
|
{
|
|
|
|
|
}
|
}
|
űũ{űũmfc 0J
j 0J Uj
UmH nH u &jt
>*B*UmH nH ph u j UmH nH u j UmH nH umH nH u &;CJ OJ QJ aJ mH nH sH$tH$u 0J ^J aJ$ mH nH u&j~ >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u&}
|
űũ{űũmfc 0J
j 0J Uj
UmH nH u &jt
>*B*UmH nH ph u j UmH nH u j UmH nH umH nH u &;CJ OJ QJ aJ mH nH sH$tH$u 0J ^J aJ$ mH nH u&j~ >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u&}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D E F _ ` a c d e f g h jL >*B*Uph j UjV >*B*Uph j Uj` >*B*Uph #5CJ OJ QJ aJ mH nH sH$tH$j U j U 0J aJ
j 0J Ujj >*B*Uph 0J 4 ; < = V W X Y Z [ \ ] ^ y z { |
ѫwkw j UmH nH umH nH u 0J aJ` mH nH u&j8 >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u j UjB >*B*Uph 0J #5CJ OJ QJ aJ mH nH sH$tH$
j 0J Uj U j U 0J aJ $
2
3
4
5
>
?
@
Y
Z
[
\
]
^
_
`
a
|
}
~
ѼѴѐނѼѴndV j UmH nH u 0J aJ` mH nH u&j$ >*B*UmH nH ph u j UmH nH u 0J aJH mH nH u&j. >*B*UmH nH ph u mH nH u0J mH nH u)5;CJ OJ QJ aJ mH nH sH$tH$uj 0J UmH nH u mH nH u j UmH nH uj UmH nH u!
|
D E F _ ` a c d e f g h jL >*B*Uph j UjV >*B*Uph j Uj` >*B*Uph #5CJ OJ QJ aJ mH nH sH$tH$j U j U 0J aJ
j 0J Ujj >*B*Uph 0J 4 ; < = V W X Y Z [ \ ] ^ y z { |
ѫwkw j UmH nH umH nH u 0J aJ` mH nH u&j8 >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u j UjB >*B*Uph 0J #5CJ OJ QJ aJ mH nH sH$tH$
j 0J Uj U j U 0J aJ $
2
3
4
5
>
?
@
Y
Z
[
\
]
^
_
`
a
|
}
~
ѼѴѐނѼѴndV j UmH nH u 0J aJ` mH nH u&j$ >*B*UmH nH ph u j UmH nH u 0J aJH mH nH u&j. >*B*UmH nH ph u mH nH u0J mH nH u)5;CJ OJ QJ aJ mH nH sH$tH$uj 0J UmH nH u mH nH u j UmH nH uj UmH nH u!
|
' ( ) * + , - . ޝ{qc j UmH nH u 0J aJ` mH nH u&j >*B*UmH nH ph u j UmH nH u 0J aJH mH nH u&j >*B*UmH nH ph u mH nH u0J mH nH u)5;CJ OJ QJ aJ mH nH sH$tH$uj 0J UmH nH u mH nH u j UmH nH u &. / J K L M Y Z [ t u v w x y z { - . ` n K ƾЏ ~ ~u~ ~ ~u~ d d d d OJ QJ ^J aJ mH$nH$sH$tH$ 5\mH nH u j Uj ;UmH nH u )5;CJ OJ QJ aJ mH nH sH$tH$uj UmH nH u j UmH nH umH nH u 0J aJH mH nH uj 0J UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u $- z | / 0 1 > ` W ) V -
|
' ( ) * + , - . ޝ{qc j UmH nH u 0J aJ` mH nH u&j >*B*UmH nH ph u j UmH nH u 0J aJH mH nH u&j >*B*UmH nH ph u mH nH u0J mH nH u)5;CJ OJ QJ aJ mH nH sH$tH$uj 0J UmH nH u mH nH u j UmH nH u &. / J K L M Y Z [ t u v w x y z { - . ` n K ƾЏ ~ ~u~ ~ ~u~ d d d d OJ QJ ^J aJ mH$nH$sH$tH$ 5\mH nH u j Uj ;UmH nH u )5;CJ OJ QJ aJ mH nH sH$tH$uj UmH nH u j UmH nH umH nH u 0J aJH mH nH uj 0J UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u $- z | / 0 1 > ` W ) V -
|
& Fg C$ ` C Eƀ c
!
|
& Fg C$ ` C Eƀ c
!
|
V m ; O s - K n o p -
|
V m ; O s - K n o p -
|
& F `
-
|
& F `
-
|
& F h^h`-
|
& F h^h`-
|
& Fg
|
& Fg
|
-
|
-
|
& F
C I A ) * ; < = >
-
|
& F
C I A ) * ; < = >
-
|
& F h^h`
|
& F h^h`
|
& Fe 7$ 8$ H$ 7$ 8$ H$ -
|
& Fe 7$ 8$ H$ 7$ 8$ H$ -
|
& F K S I L A D ) * . 6 Y ` ; < c } , B + w Z! o! |! ! `$ $ ' ' ' ' ' ' ' ۽۽ ۸ ۱۱ 5OJ QJ \^J mHsH 5OJ QJ \^J ^J OJ QJ ^J j U B*OJ QJ aJ nH$ph tH$ B*OJ QJ aJ nH$ph tH$ OJ QJ ^J aJ mH$nH$sH$tH$ &5OJ QJ \^J aJ mH$nH$sH$tH$;> ? @ U c | } , - w u s q q o q j o h q & $a$ C Eƀ c D C$Eƀ c - B + v w ~! ! ! ! ! ! ! ! ! " +" M" w" $ 7$ 8$ H$ a$ w" " " " # ,# S# |# # # # !$ H$ p$ $ $ $ % @% h% % % % & .& :& X& & & & & & ' N' \' t' ' ' ' ' ' ' ' ' ( ( ( ( ( ( ( * * + , ], , $
|
& F K S I L A D ) * . 6 Y ` ; < c } , B + w Z! o! |! ! `$ $ ' ' ' ' ' ' ' ۽۽ ۸ ۱۱ 5OJ QJ \^J mHsH 5OJ QJ \^J ^J OJ QJ ^J j U B*OJ QJ aJ nH$ph tH$ B*OJ QJ aJ nH$ph tH$ OJ QJ ^J aJ mH$nH$sH$tH$ &5OJ QJ \^J aJ mH$nH$sH$tH$;> ? @ U c | } , - w u s q q o q j o h q & $a$ C Eƀ c D C$Eƀ c - B + v w ~! ! ! ! ! ! ! ! ! " +" M" w" $ 7$ 8$ H$ a$ w" " " " # ,# S# |# # # # !$ H$ p$ $ $ $ % @% h% % % % & .& :& X& & & & & & ' N' \' t' ' ' ' ' ' ' ' ' ( ( ( ( ( ( ( * * + , ], , $
|
& Fh 7$ 8$ H$ a$
|
& Fh 7$ 8$ H$ a$
|
& Fh & ' ' ' ' (
|
& Fh & ' ' ' ' (
|
( ( ( *( ,( :( <( J( L( [( ( ( ) ) ) ) C* F* V* Y* m* r* 4+ B+ D+ R+ T+ h+ + + + + , , F, H, [, f, p, , - .- =- .
|
( ( ( *( ,( :( <( J( L( [( ( ( ) ) ) ) C* F* V* Y* m* r* 4+ B+ D+ R+ T+ h+ + + + + , , F, H, [, f, p, , - .- =- .
|
. `1 h1 1 1 1
2 S2 V2 q2 v2 2 2 3 3 d3 4 4 J4 4 4 5 5 5 5 m6 p6 6 7 7 7 ]8 ^8 _8 OJ QJ \^J \^J OJ QJ ^J aJ mH sH CJ OJ QJ 5OJ QJ \^J OJ QJ ^J R, - @- A- B- - - j. . / / <0 0 !1 "1 1 1 1 1
2 2 *
@ 7$ 8$ H$ [$ \$
|
. `1 h1 1 1 1
2 S2 V2 q2 v2 2 2 3 3 d3 4 4 J4 4 4 5 5 5 5 m6 p6 6 7 7 7 ]8 ^8 _8 OJ QJ \^J \^J OJ QJ ^J aJ mH sH CJ OJ QJ 5OJ QJ \^J OJ QJ ^J R, - @- A- B- - - j. . / / <0 0 !1 "1 1 1 1 1
2 2 *
@ 7$ 8$ H$ [$ \$
|
& Fk 7$ 8$ H$
|
& Fk 7$ 8$ H$
|
& Fk 7$ 8$ H$ 7$ 8$ H$ $ 7$ 8$ H$ a$ $
|
& Fk 7$ 8$ H$ 7$ 8$ H$ $ 7$ 8$ H$ a$ $
|
& Fh 7$ 8$ H$ a$ 2 /2 X2 2 2 _3 `3 4 4 4 J4 K4 q4 w5 L6 M6 6 6 6 7 7 *7 g7 8 \8 ]8 ^8 _8
|
& Fh 7$ 8$ H$ a$ 2 /2 X2 2 2 _3 `3 4 4 4 J4 K4 q4 w5 L6 M6 6 6 6 7 7 *7 g7 8 \8 ]8 ^8 _8
|
& Fj * h^h
|
& Fj * h^h
|
& Fi _8 8 8 q: r: : : : =; m; n; ; '< f< < ,= -= = = = > ? @ A A A aA
|
& Fi _8 8 8 q: r: : : : =; m; n; ; '< f< < ,= -= = = = > ? @ A A A aA
|
& Fl
|
& Fl
|
& Fn ,
|
& Fn ,
|
& Fm
|
& Fm
|
& Fm & _8 8 N9 X9 9 9 : : : : :
; =; I; ; ; ; ; ]< c< q< z< < < < < < < < = = = > > ? ? @ @ @ @ @ @ A _A 7C XC )D 2D DD D E E qF vF F F G G H H H H :J AJ J J J J K K HK RK K K K K L VL XL YL M M M M M N TN XN N N P \^J 5OJ QJ ^J 5OJ QJ \^J OJ QJ ^J ZaA bA B B yB BD CD DD D D E nF F G H I J J J J J K HK K K K L L *
|
& Fm & _8 8 N9 X9 9 9 : : : : :
; =; I; ; ; ; ; ]< c< q< z< < < < < < < < = = = > > ? ? @ @ @ @ @ @ A _A 7C XC )D 2D DD D E E qF vF F F G G H H H H :J AJ J J J J K K HK RK K K K K L VL XL YL M M M M M N TN XN N N P \^J 5OJ QJ ^J 5OJ QJ \^J OJ QJ ^J ZaA bA B B yB BD CD DD D D E nF F G H I J J J J J K HK K K K L L *
|
& Fo
|
& Fo
|
& Fl & L L XL YL L L M M 'M 6M [M hM uM vM N N O O Q Q YR $T %T FT GT U U W
|
& Fl & L L XL YL L L M M 'M 6M [M hM uM vM N N O O Q Q YR $T %T FT GT U U W
|
& Fq
|
& Fq
|
& Fp ,
|
& Fp ,
|
& Fp P P P Q Q Q Q Q uR R R R S S S T bT kT T T T T U *U ,V :V OV ]V W W WW FX PX mX uX X X Y Y %Z /Z Z Z Z Z 3[ 7[ [ [ [ [ [ [ u\ |\ \ \ \ \ \ ] h] n] ] ] m` y` ` ` a a a a b b b b b b b b !c "c 'c rc d d Ed f OJ QJ \^J 5OJ QJ \^J OJ QJ ^J 5OJ QJ ^J XW W W W WW XW X Y Y Y %Z Z Z Z Z '[ x[ [ \ !\ `\ \ \ \ ] ] :]
|
& Fp P P P Q Q Q Q Q uR R R R S S S T bT kT T T T T U *U ,V :V OV ]V W W WW FX PX mX uX X X Y Y %Z /Z Z Z Z Z 3[ 7[ [ [ [ [ [ [ u\ |\ \ \ \ \ \ ] h] n] ] ] m` y` ` ` a a a a b b b b b b b b !c "c 'c rc d d Ed f OJ QJ \^J 5OJ QJ \^J OJ QJ ^J 5OJ QJ ^J XW W W W WW XW X Y Y Y %Z Z Z Z Z '[ x[ [ \ !\ `\ \ \ \ ] ] :]
|
& Fw
|
& Fw
|
& Fu ,
|
& Fu ,
|
& Fm
|
& Fm
|
& Fm & :] x] ] Q^ ^ ^ ?_ _ ` ` m` ` a b b "c #c $c %c &c 'c tc uc d
d d Fd &
|
& Fm & :] x] ] Q^ ^ ^ ?_ _ ` ` m` ` a b b "c #c $c %c &c 'c tc uc d
d d Fd &
|
& Ft
|
& Ft
|
& Fx
|
& Fx
|
& Fr
|
& Fr
|
& Fr Fd Gd f f f Wf Xf f f g g g g g g g Yh Zh dh rh }h h h h h h h h h
|
& Fr Fd Gd f f f Wf Xf f f g g g g g g g Yh Zh dh rh }h h h h h h h h h
|
& Fy f Vf Xf f f %g +g @g Gg g g g Yh h h Li Ti ri {i j j qk ~k k k l l l l l l [m em /n 7n n n n n n n %o (o ,o 3o ao co o o p )p Rp Zp ~p p p p p p q q -q 0q 4q
|
& Fy f Vf Xf f f %g +g @g Gg g g g Yh h h Li Ti ri {i j j qk ~k k k l l l l l l [m em /n 7n n n n n n n %o (o ,o 3o ao co o o p )p Rp Zp ~p p p p p p q q -q 0q 4q
|
& F{ &
|
& F{ &
|
& Fz h^h s s @t Jt st {t t t t t t t u u Cu Ku Nu Wu u u u u u u u u Bv Jv v v v v w !w Iw Uw Xw _w w w w w w w w w 4x 7x ;x Cx qx tx x x x y )y 2y y Rz ez fz xz z z { { ,} ?} } ~ ~ `~ b~ u~ Q % p OJ QJ \^J 5OJ QJ ^J 5OJ QJ \^J OJ QJ ^J 5 Wb~ T U % r s = > " # ? @ 5 6 7$ 8$ H$ & " ? 6 ` 1 ] ~ % 9 ; A \ i k + C R T 2 J T V 3 B D Y l x z đ ڑ
2 ! 9 : I J t ֚ ך ؚ 0J j$ U0J mH nH u0J
j 0J U B*ph B*ph j U ^J mHsH mHsH ^J OJ QJ ^J K6 ` a 0 1 ] } ~
; @ A k * + T 1 2 V D X Y z & 7$ 8$ H$ @ A B C Ñ đ
|
& Fz h^h s s @t Jt st {t t t t t t t u u Cu Ku Nu Wu u u u u u u u u Bv Jv v v v v w !w Iw Uw Xw _w w w w w w w w w 4x 7x ;x Cx qx tx x x x y )y 2y y Rz ez fz xz z z { { ,} ?} } ~ ~ `~ b~ u~ Q % p OJ QJ \^J 5OJ QJ ^J 5OJ QJ \^J OJ QJ ^J 5 Wb~ T U % r s = > " # ? @ 5 6 7$ 8$ H$ & " ? 6 ` 1 ] ~ % 9 ; A \ i k + C R T 2 J T V 3 B D Y l x z đ ڑ
2 ! 9 : I J t ֚ ך ؚ 0J j$ U0J mH nH u0J
j 0J U B*ph B*ph j U ^J mHsH mHsH ^J OJ QJ ^J K6 ` a 0 1 ] } ~
; @ A k * + T 1 2 V D X Y z & 7$ 8$ H$ @ A B C Ñ đ
|
& 7$ 8$ H$ R + , - . / 0 2 3 = 7$ 8$ H$ C Eƀ c ,
|
& 7$ 8$ H$ R + , - . / 0 2 3 = 7$ 8$ H$ C Eƀ c ,
|
& F
|
& F
|
& F ) M u C- Eƀ c C Eƀ c N O P ] y w 4 2 C Eƀ c C- Eƀ c C- Eƀ c ] ҙ w 4 C- Eƀ c L C- Eƀ c K C- Eƀ c J o p q r s t y t r r r r r p f d
|
& F ) M u C- Eƀ c C Eƀ c N O P ] y w 4 2 C Eƀ c C- Eƀ c C- Eƀ c ] ҙ w 4 C- Eƀ c L C- Eƀ c K C- Eƀ c J o p q r s t y t r r r r r p f d
|
$d N 6 $a$C- Eƀ c N C- Eƀ c M
|
$d N 6 $a$C- Eƀ c N C- Eƀ c M
|
$d N
> ? @ X Y b n o u v w x | } B*ph 0J j% U j U0J mH nH u
j 0J U0J 6 $a$ <
|
$d N
> ? @ X Y b n o u v w x | } B*ph 0J j% U j U0J mH nH u
j 0J U0J 6 $a$ <
|
000&P P /R / =!"#$% X02 0 0&P /R / =!"#$% X/ 0 P /R / =!"#$% v6 0 0 P /R / =!"#$% v P 2 0 0 P /R / =!"#$% v n Rw]SEY2PNG
|
000&P P /R / =!"#$% X02 0 0&P /R / =!"#$% X/ 0 P /R / =!"#$% v6 0 0 P /R / =!"#$% v P 2 0 0 P /R / =!"#$% v n Rw]SEY2PNG
|
|
|
IHDR
L o gAMA pHYs %R yIDATxQLwO[!⇚*exhBVJ:W X'DT&sBEMJ1j %5PQ%ia0J2Hrk(Cp V}2 g0c{ &~3O,7yz7& _{ Y
|
IHDR
L o gAMA pHYs %R yIDATxQLwO[!⇚*exhBVJ:W X'DT&sBEMJ1j %5PQ%ia0J2Hrk(Cp V}2 g0c{ &~3O,7yz7& _{ Y
|
9 @r 2$ eI ʐ !' (CN P 9 @r 2$ eI ʐ !' (CN P @V;g>Tm.r9~mqy#įmE T S^^
-{'Fp^knߐDj_CBMFoe1PN{x48|`c6ڜ Oһn_O~9Wu;vd{a'į=%z]NlRNG_ z(~F{߄C?mm3O|cnG5ߘ[ sZK9i? Y$ٻNb.Boz^'I]>)c)c9h9~MK $HHT17n>TQZxU
|
9 @r 2$ eI ʐ !' (CN P 9 @r 2$ eI ʐ !' (CN P @V;g>Tm.r9~mqy#įmE T S^^
-{'Fp^knߐDj_CBMFoe1PN{x48|`c6ڜ Oһn_O~9Wu;vd{a'į=%z]NlRNG_ z(~F{߄C?mm3O|cnG5ߘ[ sZK9i? Y$ٻNb.Boz^'I]>)c)c9h9~MK $HHT17n>TQZxU
|
SaLyRWUa zY ^&O v7l(-q(ofG]>d(#KÝ k}; T¯o_>g>}C 7Ϊe0qEGꦣ! ~mPO>㨩*7V-` z_:WJ}-ӚMk>"A3ۑ @sQ1f;f; s
>\vRr fTzC ,IZ\X qz|ҜDavzgGŨ j;x 6 F(
|
SaLyRWUa zY ^&O v7l(-q(ofG]>d(#KÝ k}; T¯o_>g>}C 7Ϊe0qEGꦣ! ~mPO>㨩*7V-` z_:WJ}-ӚMk>"A3ۑ @sQ1f;f; s
>\vRr fTzC ,IZ\X qz|ҜDavzgGŨ j;x 6 F(
|
;5S\y{d56YyH/vvq?K0N1weD㺐~H* 9)]u ZjUaeo:mo\ZYZ?̎m[=!9){Ƃ 9M6Y霑\LH\N76U
|
;5S\y{d56YyH/vvq?K0N1weD㺐~H* 9)]u ZjUaeo:mo\ZYZ?̎m[=!9){Ƃ 9M6Y霑\LH\N76U
|
; 29~m_k63SxII8j<`UvdoO_ꜹrPA %$H=>8zdv$B&fryia6k$U]j4KT5 TSG$ @ND/E#GlΐD}s؊ vd/1ӔsyCd^s2yrRYN ҥ�h6hl~ub.Q#mYZR840%k
|
; 29~m_k63SxII8j<`UvdoO_ꜹrPA %$H=>8zdv$B&fryia6k$U]j4KT5 TSG$ @ND/E#GlΐD}s؊ vd/1ӔsyCd^s2yrRYN ҥ�h6hl~ub.Q#mYZR840%k
|
]Vr|7%L,Mrn:jٽɧS,פ]n;Gg'S8 @VANJԆI W9Uag f)BuUeӶFd_IK(.z#V4db.ۗo6X0t&5ftI_PJjʎ> L%_̺֒
|
]Vr|7%L,Mrn:jٽɧS,פ]n;Gg'S8 @VANJԆI W9Uag f)BuUeӶFd_IK(.z#V4db.ۗo6X0t&5ftI_PJjʎ> L%_̺֒
|
pPOMNjYTC+|̂VK6Dc *>zvp^%S|c.B= ߾y }hlo?|.'E͟gu*J 鏍 FUUe%7*$C=)]d]VH (. 3Q+0
|
pPOMNjYTC+|̂VK6Dc *>zvp^%S|c.B= ߾y }hlo?|.'E͟gu*J 鏍 FUUe%7*$C=)]d]VH (. 3Q+0
|
NWL|a!hloy-Av4?bwvVW R @1$3Y?i1 >$U䘈BpIS9M[\` 3g Ʌȗ fj \qv<L2[zd7 vKR$_"P*9NiȞ|uM.G*LL^/g ̻eyKCۏsUUo?jx] mٰd4ɄVYBOSu\B?R?]I^#َ > x2 xГj7tX3#QU
|
NWL|a!hloy-Av4?bwvVW R @1$3Y?i1 >$U䘈BpIS9M[\` 3g Ʌȗ fj \qv<L2[zd7 vKR$_"P*9NiȞ|uM.G*LL^/g ̻eyKCۏsUUo?jx] mٰd4ɄVYBOSu\B?R?]I^#َ > x2 xГj7tX3#QU
|
U~>t^
PO!I SA]:uL
.QIEt\P,ɧۗC!w 7 5 ?hl_),}!d G 9 X!iqy㠥!׀_eITS;.tTo'U[mhcV O2&) z r):̪sݓX ap< b,z *)6$Q
m# Iq˫N{
4*i<%3/Vz7O_d"
hܽ*4G*D'G ,X/= ,U_!俞Ϊ3ǯj85 $*\עA N"̻ (CN P 9 `4q ANJd4 KGv̎/6X=& d-
|
U~>t^
PO!I SA]:uL
.QIEt\P,ɧۗC!w 7 5 ?hl_),}!d G 9 X!iqy㠥!׀_eITS;.tTo'U[mhcV O2&) z r):̪sݓX ap< b,z *)6$Q
m# Iq˫N{
4*i<%3/Vz7O_d"
hܽ*4G*D'G ,X/= ,U_!俞Ϊ3ǯj85 $*\עA N"̻ (CN P 9 `4q ANJd4 KGv̎/6X=& d-
|
>0 }ګk/_hQ[tF۫oEK ुzRfGҐD1Ѡe֚c$ @VA=)91u?FcGvh Z94$[Ϳ/)"me}*
z]yI!diem݇{`)*0B %AnҊ =?!럖j#ag 9-FcP Z*M3{K7JgQpA،xx!ҥoҫA,^@
!'i x]^KfG݄}B߅VgGy(K}bnt-B>Š6:[w]ҦoO]Zcx='s.1m\ N8FB?^Ҿ{Zx! ~tWciEpT; !OJ0IHjv+0Fcޱ. !{p}Q،xfwN# HacgKn46qַ"^,&)#.zF}Đ"GK8zVT6#gx@BCdh! \VoD ͡Oj!< zn4vR/**0
|
>0 }ګk/_hQ[tF۫oEK ुzRfGҐD1Ѡe֚c$ @VA=)91u?FcGvh Z94$[Ϳ/)"me}*
z]yI!diem݇{`)*0B %AnҊ =?!럖j#ag 9-FcP Z*M3{K7JgQpA،xx!ҥoҫA,^@
!'i x]^KfG݄}B߅VgGy(K}bnt-B>Š6:[w]ҦoO]Zcx='s.1m\ N8FB?^Ҿ{Zx! ~tWciEpT; !OJ0IHjv+0Fcޱ. !{p}Q،xfwN# HacgKn46qַ"^,&)#.zF}Đ"GK8zVT6#gx@BCdh! \VoD ͡Oj!< zn4vR/**0
|
=K8ɉ ъTe"{~py:4S0uLH#=K' P,ѿҸfuku_i9=mڜ POJT.Ҋ`o̎ %hv6#N{v]UYJ$vPޱ1X"/, V4䙐do",f['!dF\I~@?9/V4$j#W`4:I)i g̬ {N$ ԓR 'CJRiwf6D]>^
|
=K8ɉ ъTe"{~py:4S0uLH#=K' P,ѿҸfuku_i9=mڜ POJT.Ҋ`o̎ %hv6#N{v]UYJ$vPޱ1X"/, V4䙐do",f['!dF\I~@?9/V4$j#W`4:I)i g̬ {N$ ԓR 'CJRiwf6D]>^
|
K߳mb3S6nqwΣ.M8p5;+ B8t)Lg,&k/OyH-+p_)
|
K߳mb3S6nqwΣ.M8p5;+ B8t)Lg,&k/OyH-+p_)
|
iIڠݟBVl
|
iIڠݟBVl
|
#ꋚ:>t MYW`eZFrT,wfB߅cy goЪv.Hw[?LyF0?K8F^}az&=t q&]ko,7XkwK، =o,F x]_=
|
#ꋚ:>t MYW`eZFrT,wfB߅cy goЪv.Hw[?LyF0?K8F^}az&=t q&]ko,7XkwK، =o,F x]_=
|
ރ=kkfG?k7XF 82II7zf\~Wd`bs_?5%A} eĴ$J_z}T
z N|P6 pFj'%: {
|
ރ=kkfG?k7XF 82II7zf\~Wd`bs_?5%A} eĴ$J_z}T
z N|P6 pFj'%: {
|
u9=G ,6,hlie}iE$|ygK5$B 4$I|
(ݲbGq#obnOλ> {?| ]`b
|
u9=G ,6,hlie}iE$|ygK5$B 4$I|
(ݲbGq#obnOλ> {?| ]`b
|
t A 4>ɐ+dQh*suIk}MfSAc D{ 8[ј͚m# /} X/f[1 @6@ 7 2$ eI ʐ !' (CN P 9 @r 2$ eI ʐ = .x IENDB` { D y K
_ T o c 1 7 0 2 2 7 5 8 { D y K
_ T o c 1 7 0 2 2 7 5 8 { D y K
_ T o c 1 7 0 2 2 7 5 9 { D y K
_ T o c 1 7 0 2 2 7 5 9 { D y K
_ T o c 1 7 0 2 2 7 6 0 { D y K
_ T o c 1 7 0 2 2 7 6 0 { D y K
_ T o c 1 7 0 2 2 7 6 1 { D y K
_ T o c 1 7 0 2 2 7 6 1 { D y K
_ T o c 1 7 0 2 2 7 6 2 { D y K
_ T o c 1 7 0 2 2 7 6 2 { D y K
_ T o c 1 7 0 2 2 7 6 3 { D y K
_ T o c 1 7 0 2 2 7 6 3 { D y K
_ T o c 1 7 0 2 2 7 6 4 { D y K
_ T o c 1 7 0 2 2 7 6 4 { D y K
_ T o c 1 7 0 2 2 7 6 5 { D y K
_ T o c 1 7 0 2 2 7 6 5 { D y K
_ T o c 1 7 0 2 2 7 6 6 { D y K
_ T o c 1 7 0 2 2 7 6 6 { D y K
_ T o c 1 7 0 2 2 7 6 7 { D y K
_ T o c 1 7 0 2 2 7 6 7 { D y K
_ T o c 1 7 0 2 2 7 6 8 { D y K
_ T o c 1 7 0 2 2 7 6 8 { D y K
_ T o c 1 7 0 2 2 7 6 9 { D y K
_ T o c 1 7 0 2 2 7 6 9 { D y K
_ T o c 1 7 0 2 2 7 7 0 { D y K
_ T o c 1 7 0 2 2 7 7 0 { D y K
_ T o c 1 7 0 2 2 7 7 1 { D y K
_ T o c 1 7 0 2 2 7 7 1 { D y K
_ T o c 1 7 0 2 2 7 7 2 { D y K
_ T o c 1 7 0 2 2 7 7 2 { D y K
_ T o c 1 7 0 2 2 7 7 3 { D y K
_ T o c 1 7 0 2 2 7 7 3 { D y K
_ T o c 1 7 0 2 2 7 7 4 { D y K
_ T o c 1 7 0 2 2 7 7 4 { D y K
_ T o c 1 7 0 2 2 7 7 5 { D y K
_ T o c 1 7 0 2 2 7 7 5 { D y K
_ T o c 1 7 0 2 2 7 7 6 { D y K
_ T o c 1 7 0 2 2 7 7 6 { D y K
_ T o c 1 7 0 2 2 7 7 7 { D y K
_ T o c 1 7 0 2 2 7 7 7 { D y K
_ T o c 1 7 0 2 2 7 7 8 { D y K
_ T o c 1 7 0 2 2 7 7 8 { D y K
_ T o c 1 7 0 2 2 7 7 9 { D y K
_ T o c 1 7 0 2 2 7 7 9 { D y K
_ T o c 1 7 0 2 2 7 8 0 { D y K
_ T o c 1 7 0 2 2 7 8 0 { D y K
_ T o c 1 7 0 2 2 7 8 1 { D y K
_ T o c 1 7 0 2 2 7 8 1 { D y K
_ T o c 1 7 0 2 2 7 8 2 { D y K
_ T o c 1 7 0 2 2 7 8 2 { D y K
_ T o c 1 7 0 2 2 7 8 3 { D y K
_ T o c 1 7 0 2 2 7 8 3 D d
|
t A 4>ɐ+dQh*suIk}MfSAc D{ 8[ј͚m# /} X/f[1 @6@ 7 2$ eI ʐ !' (CN P 9 @r 2$ eI ʐ = .x IENDB` { D y K
_ T o c 1 7 0 2 2 7 5 8 { D y K
_ T o c 1 7 0 2 2 7 5 8 { D y K
_ T o c 1 7 0 2 2 7 5 9 { D y K
_ T o c 1 7 0 2 2 7 5 9 { D y K
_ T o c 1 7 0 2 2 7 6 0 { D y K
_ T o c 1 7 0 2 2 7 6 0 { D y K
_ T o c 1 7 0 2 2 7 6 1 { D y K
_ T o c 1 7 0 2 2 7 6 1 { D y K
_ T o c 1 7 0 2 2 7 6 2 { D y K
_ T o c 1 7 0 2 2 7 6 2 { D y K
_ T o c 1 7 0 2 2 7 6 3 { D y K
_ T o c 1 7 0 2 2 7 6 3 { D y K
_ T o c 1 7 0 2 2 7 6 4 { D y K
_ T o c 1 7 0 2 2 7 6 4 { D y K
_ T o c 1 7 0 2 2 7 6 5 { D y K
_ T o c 1 7 0 2 2 7 6 5 { D y K
_ T o c 1 7 0 2 2 7 6 6 { D y K
_ T o c 1 7 0 2 2 7 6 6 { D y K
_ T o c 1 7 0 2 2 7 6 7 { D y K
_ T o c 1 7 0 2 2 7 6 7 { D y K
_ T o c 1 7 0 2 2 7 6 8 { D y K
_ T o c 1 7 0 2 2 7 6 8 { D y K
_ T o c 1 7 0 2 2 7 6 9 { D y K
_ T o c 1 7 0 2 2 7 6 9 { D y K
_ T o c 1 7 0 2 2 7 7 0 { D y K
_ T o c 1 7 0 2 2 7 7 0 { D y K
_ T o c 1 7 0 2 2 7 7 1 { D y K
_ T o c 1 7 0 2 2 7 7 1 { D y K
_ T o c 1 7 0 2 2 7 7 2 { D y K
_ T o c 1 7 0 2 2 7 7 2 { D y K
_ T o c 1 7 0 2 2 7 7 3 { D y K
_ T o c 1 7 0 2 2 7 7 3 { D y K
_ T o c 1 7 0 2 2 7 7 4 { D y K
_ T o c 1 7 0 2 2 7 7 4 { D y K
_ T o c 1 7 0 2 2 7 7 5 { D y K
_ T o c 1 7 0 2 2 7 7 5 { D y K
_ T o c 1 7 0 2 2 7 7 6 { D y K
_ T o c 1 7 0 2 2 7 7 6 { D y K
_ T o c 1 7 0 2 2 7 7 7 { D y K
_ T o c 1 7 0 2 2 7 7 7 { D y K
_ T o c 1 7 0 2 2 7 7 8 { D y K
_ T o c 1 7 0 2 2 7 7 8 { D y K
_ T o c 1 7 0 2 2 7 7 9 { D y K
_ T o c 1 7 0 2 2 7 7 9 { D y K
_ T o c 1 7 0 2 2 7 8 0 { D y K
_ T o c 1 7 0 2 2 7 8 0 { D y K
_ T o c 1 7 0 2 2 7 8 1 { D y K
_ T o c 1 7 0 2 2 7 8 1 { D y K
_ T o c 1 7 0 2 2 7 8 2 { D y K
_ T o c 1 7 0 2 2 7 8 2 { D y K
_ T o c 1 7 0 2 2 7 8 3 { D y K
_ T o c 1 7 0 2 2 7 8 3 D d
|
N
|
N
|
|
|
C * A w i s h l o g o b Kp19Od
|
C * A w i s h l o g o b Kp19Od
|
@ + n
|
@ + n
|
Kp19OdPNG
|
Kp19OdPNG
|
|
|
IHDR _ v A PLTE ʦ 3 f 3 33 3f 3 3 3 f f3 ff f f f 3 f 3 f ̙ 3 f 3 3 33 f3 3 3 33 33333f3333333f 3f33ff3f3f3f3 333f3333 333f3̙333 333f333f f 3f ff f f f3 f33f3ff3f3f3ff ff3ffffffffff f3ffffff f3fff̙fff f3fffff 3 f ̙ 3 333f33̙3f f3ffff̙f 3f̙ 3f̙̙ 3f̙ 3 f 3 333f333f f3fffff̙ ̙3̙f̙̙̙ 3f̙ 3f 3 f 3 333f333f f3fffff 3f 3f̙ 3f ;ٙ bKGD H cmPPJCmp0712 H s sIDATx^횋: Cܙ$@d+tgĎ} ~ϟ_ ٻu?Piʿ+~?z|L `?zb q
7TS;
|
IHDR _ v A PLTE ʦ 3 f 3 33 3f 3 3 3 f f3 ff f f f 3 f 3 f ̙ 3 f 3 3 33 f3 3 3 33 33333f3333333f 3f33ff3f3f3f3 333f3333 333f3̙333 333f333f f 3f ff f f f3 f33f3ff3f3f3ff ff3ffffffffff f3ffffff f3fff̙fff f3fffff 3 f ̙ 3 333f33̙3f f3ffff̙f 3f̙ 3f̙̙ 3f̙ 3 f 3 333f333f f3fffff̙ ̙3̙f̙̙̙ 3f̙ 3f 3 f 3 333f333f f3fffff 3f 3f̙ 3f ;ٙ bKGD H cmPPJCmp0712 H s sIDATx^횋: Cܙ$@d+tgĎ} ~ϟ_ ٻu?Piʿ+~?z|L `?zb q
7TS;
|
|
|
*J }"7zGm^Mn^FHK-A-.VtD:,oJs"Yϒ,Z14n
׃bj?I ˻~,OxbbVb569ˏ4Dn v1ѭ3|4J'#gR ; (w WԐf_4. J -NQu \T@3<,(Kȳ ~~#f'$GxP; ShOxWbWV1r" ]}mb܀Ns Ui
a.Z/e'FC{l;?8+=Z)~ڶ aOpb#{،Ѵķ,\zݱ^*qIhU-vJս&~# U4Zj; ? i㣔WY_g
o.wS1ׅ'"=0jwkR4nj̑(ψ̋GD0 T_{
4)2t9͠02D7?v.z<[Aх؈KKzG\-4̶AP3Srf{Cd4#A)Ǧ_0=kX2sDuLzSrB~ah#'̔ v/[)4?d3Ty|zh@Q'X,bwT햣D]phQ1u`NBؾa =핵HPf{
|
*J }"7zGm^Mn^FHK-A-.VtD:,oJs"Yϒ,Z14n
׃bj?I ˻~,OxbbVb569ˏ4Dn v1ѭ3|4J'#gR ; (w WԐf_4. J -NQu \T@3<,(Kȳ ~~#f'$GxP; ShOxWbWV1r" ]}mb܀Ns Ui
a.Z/e'FC{l;?8+=Z)~ڶ aOpb#{،Ѵķ,\zݱ^*qIhU-vJս&~# U4Zj; ? i㣔WY_g
o.wS1ׅ'"=0jwkR4nj̑(ψ̋GD0 T_{
4)2t9͠02D7?v.z<[Aх؈KKzG\-4̶AP3Srf{Cd4#A)Ǧ_0=kX2sDuLzSrB~ah#'̔ v/[)4?d3Ty|zh@Q'X,bwT햣D]phQ1u`NBؾa =핵HPf{
|
NjHZ{"64nŋ2*.}}AiL_J3Hh3oTT:=t.+NE3p/+hT8+z}!Xe`H|`bKRw؝%/s#/Бb(1m/Ww : =Y+Fz̈S tZXQ:Wbm>xMF fGMv wa_NRC݅bQZ(Bd-.rO3ׂVދxdҞ^}%p]ߏxDvCgnzx7/
eŵtЧ Ww <ڡ3: ތ
|
NjHZ{"64nŋ2*.}}AiL_J3Hh3oTT:=t.+NE3p/+hT8+z}!Xe`H|`bKRw؝%/s#/Бb(1m/Ww : =Y+Fz̈S tZXQ:Wbm>xMF fGMv wa_NRC݅bQZ(Bd-.rO3ׂVދxdҞ^}%p]ߏxDvCgnzx7/
eŵtЧ Ww <ڡ3: ތ
|
pK'<(yy omψ9>E 5; f@dvwU ] xGP X.X{Y" IENDB` D y K h t t p : / / w w w . o p e n c o r e s . o r g y K 4 h t t p : / / w w w . o p e n c o r e s . o r g / D y K h t t p : / / w w w . o p e n c o r e s . o r g y K 4 h t t p : / / w w w . o p e n c o r e s . o r g / f
|
pK'<(yy omψ9>E 5; f@dvwU ] xGP X.X{Y" IENDB` D y K h t t p : / / w w w . o p e n c o r e s . o r g y K 4 h t t p : / / w w w . o p e n c o r e s . o r g / D y K h t t p : / / w w w . o p e n c o r e s . o r g y K 4 h t t p : / / w w w . o p e n c o r e s . o r g / f
|
i > @ > N o r m a l $x a$ CJ _HmH sH tH j @ j
H e a d i n g 1 5 $$$
|
i > @ > N o r m a l $x a$ CJ _HmH sH tH j @ j
H e a d i n g 1 5 $$$
|
& F
f! &d0 @& P 0 a$ 5CJ` OJ QJ J @ J
H e a d i n g 2 $ $h @&a$ 5CJ$ OJ QJ \ @ \ H e a d i n g 3 $ $
f! @&a$ 5CJ OJ QJ mH nH uT ` T
H e a d i n g 4 $ $
f! @&a$ 56CJ OJ QJ D @ D H e a d i n g 5 $$
f!@&a$
|
& F
f! &d0 @& P 0 a$ 5CJ` OJ QJ J @ J
H e a d i n g 2 $ $h @&a$ 5CJ$ OJ QJ \ @ \ H e a d i n g 3 $ $
f! @&a$ 5CJ OJ QJ mH nH uT ` T
H e a d i n g 4 $ $
f! @&a$ 56CJ OJ QJ D @ D H e a d i n g 5 $$
f!@&a$
|
6B*CJ F @ F H e a d i n g 6 $$
3 @&a$ 6CJ F @ F
H e a d i n g 7 $ $ @&a$ 5CJ@ OJ QJ B @ B H e a d i n g 8
< @& 6CJ OJ QJ D @ D H e a d i n g 9
< @& 56CJ OJ QJ < A@ < D e f a u l t P a r a g r a p h F o n t N O N H e a d i n g 1 N a m e $@& a$ 5CJH OJ QJ R @ R H e a d e r
! & 5B*CJ OJ QJ \mH nH ph u< @ <
F o o t e r
! CJ OJ QJ ( U@ !( H y p e r l i n k >*B*& )@ 1& P a g e N u m b e r V >@ V T i t l e $ < a$* CJ` KH OJ QJ \_HmH nH sH tH uF @ F
T O C 1 x -D M
|
6B*CJ F @ F H e a d i n g 6 $$
3 @&a$ 6CJ F @ F
H e a d i n g 7 $ $ @&a$ 5CJ@ OJ QJ B @ B H e a d i n g 8
< @& 6CJ OJ QJ D @ D H e a d i n g 9
< @& 56CJ OJ QJ < A@ < D e f a u l t P a r a g r a p h F o n t N O N H e a d i n g 1 N a m e $@& a$ 5CJH OJ QJ R @ R H e a d e r
! & 5B*CJ OJ QJ \mH nH ph u< @ <
F o o t e r
! CJ OJ QJ ( U@ !( H y p e r l i n k >*B*& )@ 1& P a g e N u m b e r V >@ V T i t l e $ < a$* CJ` KH OJ QJ \_HmH nH sH tH uF @ F
T O C 1 x -D M
|
5;CJ OJ QJ : @ :
T O C 2 , ^, ;CJ OJ QJ D @ bD T O C 3 ^ 5CJ OJ QJ mH nH u. @ .
T O C 4 ^ CJ 8 V@ 8 F o l l o w e d H y p e r l i n k >*B* < "@ < C a p t i o n $x a$ 5CJ OJ QJ < O <
T a b l e $ ( ( a$ CJ OJ QJ \ * O *
I n d e x
|
5;CJ OJ QJ : @ :
T O C 2 , ^, ;CJ OJ QJ D @ bD T O C 3 ^ 5CJ OJ QJ mH nH u. @ .
T O C 4 ^ CJ 8 V@ 8 F o l l o w e d H y p e r l i n k >*B* < "@ < C a p t i o n $x a$ 5CJ OJ QJ < O <
T a b l e $ ( ( a$ CJ OJ QJ \ * O *
I n d e x
|
& F R O R
A p p e n d i x N a m e $a$ 5CJH OJ QJ mH nH u8 T@ 8
|
& F R O R
A p p e n d i x N a m e $a$ 5CJH OJ QJ mH nH u8 T@ 8
|
B l o c k T e x t ]^ & B@ &
B o d y T e x t @ O @
A p p e n d i x
|
B l o c k T e x t ]^ & B@ &
B o d y T e x t @ O @
A p p e n d i x
|
& F &d0 P 0 J P@ J B o d y T e x t 2 ! $d a$ 6B*CJ$ ]ph . Q@ ". B o d y T e x t 3 " CJ H M@2H B o d y T e x t F i r s t I n d e n t
|
& F &d0 P 0 J P@ J B o d y T e x t 2 ! $d a$ 6B*CJ$ ]ph . Q@ ". B o d y T e x t 3 " CJ H M@2H B o d y T e x t F i r s t I n d e n t
|
# ` < C@ B< B o d y T e x t I n d e n t
|
# ` < C@ B< B o d y T e x t I n d e n t
|
$ h^h 0 @ R0 C o m m e n t T e x t % CJ L@ D a t e & 0 +@ r0 E n d n o t e T e x t ' CJ 2 @ 2
F o o t n o t e T e x t ( CJ 2
|
$ h^h 0 @ R0 C o m m e n t T e x t % CJ L@ D a t e & 0 +@ r0 E n d n o t e T e x t ' CJ 2 @ 2
F o o t n o t e T e x t ( CJ 2
|
@ 2
I n d e x 1 ) ^ ` : !@ :
I n d e x H e a d i n g * 5OJ QJ , /@ , L i s t + h^h` 0 2@ 0 L i s t 2 , ^` 2 0@ 2
L i s t B u l l e t -
|
@ 2
I n d e x 1 ) ^ ` : !@ :
I n d e x H e a d i n g * 5OJ QJ , /@ , L i s t + h^h` 0 2@ 0 L i s t 2 , ^` 2 0@ 2
L i s t B u l l e t -
|
& F 6 6@ 6
L i s t B u l l e t 2 .
|
& F 6 6@ 6
L i s t B u l l e t 2 .
|
& F
|
& F
|
2 1@ 2 L i s t N u m b e r /
|
2 1@ 2 L i s t N u m b e r /
|
& F 6 :@ 6
L i s t N u m b e r 2 0
|
& F 6 :@ 6
L i s t N u m b e r 2 0
|
& F 6 @ 6
N o r m a l I n d e n t
|
& F 6 @ 6
N o r m a l I n d e n t
|
1 ^ : J@ ": S u b t i t l e 2 $< @&a$ OJ QJ L ,@ L T a b l e o f A u t h o r i t i e s 3 ^ ` D #@ D T a b l e o f F i g u r e s 4 ^` : .@ : T O A H e a d i n g 5 x 5OJ QJ & O&
C a p t i o n 1 6 D O D H e a d e i n g 1 N a m e 7 $ a$ 5CJH P Y@ P D o c u m e n t M a p 8 $ -D M
|
1 ^ : J@ ": S u b t i t l e 2 $< @&a$ OJ QJ L ,@ L T a b l e o f A u t h o r i t i e s 3 ^ ` D #@ D T a b l e o f F i g u r e s 4 ^` : .@ : T O A H e a d i n g 5 x 5OJ QJ & O&
C a p t i o n 1 6 D O D H e a d e i n g 1 N a m e 7 $ a$ 5CJH P Y@ P D o c u m e n t M a p 8 $ -D M
|
a$ OJ QJ 0 @ 0
T O C 5 9 $ ^a$ 0 @ 0
T O C 6 : $ ^a$ 0 @ 0
T O C 7 ; $ ^a$ 0 @ 0
T O C 8 < $ ^a$ 0 @ 0
T O C 9 = $ ^a$ D R@ D B o d y T e x t I n d e n t 2 > ^ N S@ N B o d y T e x t I n d e n t 3 ? $ ^a$ \ L ^@ L N o r m a l ( W e b ) @ $ d d [$\$a$ aJ mH sH F g@ F H T M L T y p e w r i t e r CJ OJ PJ QJ ^J aJ Z N@A"Z B o d y T e x t F i r s t I n d e n t 2 B $ ^` a$ 4 ?@ 24 C l o s i n g C $ ^a$ > [@ B> E - m a i l S i g n a t u r e D $ a$ n $@ Rn E n v e l o p e A d d r e s s + E $ @ &+D/ ^@ a$ OJ QJ ^J aJ L %@ bL E n v e l o p e R e t u r n F $ a$ CJ OJ QJ ^J < `@ r< H T M L A d d r e s s G $ a$ 6]P e@ P H T M L P r e f o r m a t t e d H $ a$ CJ OJ QJ ^J < @ <
I n d e x 2 I $ ^`a$ < @ <
I n d e x 3 J $ ^`a$ <
@ <
I n d e x 4 K $ ^`a$ < @ <
I n d e x 5 L $ ^`a$ < @ <
I n d e x 6 M $ ^`a$ < @ <
I n d e x 7 N $ ^`a$ < @ <
I n d e x 8 O $ ^`a$ < @ <
I n d e x 9 P $ p ^p`a$ : 3@ : L i s t 3 Q $ Q ^Q`a$ : 4@ ": L i s t 4 R $ l ^l`a$ : 5@ 2: L i s t 5 S $ ^`a$ R 7@ BR
L i s t B u l l e t 3 % T $
|
a$ OJ QJ 0 @ 0
T O C 5 9 $ ^a$ 0 @ 0
T O C 6 : $ ^a$ 0 @ 0
T O C 7 ; $ ^a$ 0 @ 0
T O C 8 < $ ^a$ 0 @ 0
T O C 9 = $ ^a$ D R@ D B o d y T e x t I n d e n t 2 > ^ N S@ N B o d y T e x t I n d e n t 3 ? $ ^a$ \ L ^@ L N o r m a l ( W e b ) @ $ d d [$\$a$ aJ mH sH F g@ F H T M L T y p e w r i t e r CJ OJ PJ QJ ^J aJ Z N@A"Z B o d y T e x t F i r s t I n d e n t 2 B $ ^` a$ 4 ?@ 24 C l o s i n g C $ ^a$ > [@ B> E - m a i l S i g n a t u r e D $ a$ n $@ Rn E n v e l o p e A d d r e s s + E $ @ &+D/ ^@ a$ OJ QJ ^J aJ L %@ bL E n v e l o p e R e t u r n F $ a$ CJ OJ QJ ^J < `@ r< H T M L A d d r e s s G $ a$ 6]P e@ P H T M L P r e f o r m a t t e d H $ a$ CJ OJ QJ ^J < @ <
I n d e x 2 I $ ^`a$ < @ <
I n d e x 3 J $ ^`a$ <
@ <
I n d e x 4 K $ ^`a$ < @ <
I n d e x 5 L $ ^`a$ < @ <
I n d e x 6 M $ ^`a$ < @ <
I n d e x 7 N $ ^`a$ < @ <
I n d e x 8 O $ ^`a$ < @ <
I n d e x 9 P $ p ^p`a$ : 3@ : L i s t 3 Q $ Q ^Q`a$ : 4@ ": L i s t 4 R $ l ^l`a$ : 5@ 2: L i s t 5 S $ ^`a$ R 7@ BR
L i s t B u l l e t 3 % T $
|
& F
8 ^a$ R 8@ RR
L i s t B u l l e t 4 % U $
|
& F
8 ^a$ R 8@ RR
L i s t B u l l e t 4 % U $
|
& F
^a$ R 9@ bR
L i s t B u l l e t 5 % V $
|
& F
^a$ R 9@ bR
L i s t B u l l e t 5 % V $
|
& F
^a$ < D@ r<
L i s t C o n t i n u e W $ ^a$ @ E@ @ L i s t C o n t i n u e 2 X $ 6^6a$ @ F@ @ L i s t C o n t i n u e 3 Y $ Q^Qa$ @ G@ @ L i s t C o n t i n u e 4 Z $ l^la$ @ H@ @ L i s t C o n t i n u e 5 [ $ ^a$ R ;@ R
L i s t N u m b e r 3 % \ $
|
& F
^a$ < D@ r<
L i s t C o n t i n u e W $ ^a$ @ E@ @ L i s t C o n t i n u e 2 X $ 6^6a$ @ F@ @ L i s t C o n t i n u e 3 Y $ Q^Qa$ @ G@ @ L i s t C o n t i n u e 4 Z $ l^la$ @ H@ @ L i s t C o n t i n u e 5 [ $ ^a$ R ;@ R
L i s t N u m b e r 3 % \ $
|
& F
8 ^a$ R <@ R
L i s t N u m b e r 4 % ] $
|
& F
8 ^a$ R <@ R
L i s t N u m b e r 4 % ] $
|
& F
^a$ R =@ R
L i s t N u m b e r 5 % ^ $
|
& F
^a$ R =@ R
L i s t N u m b e r 5 % ^ $
|
& F
^a$ d -@d
|
& F
^a$ d -@d
|
M a c r o T e x t " _
` @
OJ QJ ^J _HmH sH tH I@ M e s s a g e H e a d e r q ` $ n $d %d &d 'd -D M
|
M a c r o T e x t " _
` @
OJ QJ ^J _HmH sH tH I@ M e s s a g e H e a d e r q ` $ n $d %d &d 'd -D M
|
N O P Q ^n`a$ OJ QJ ^J aJ 6 O@ 6 N o t e H e a d i n g a $ a$ B Z@ "B
|
N O P Q ^n`a$ OJ QJ ^J aJ 6 O@ 6 N o t e H e a d i n g a $ a$ B Z@ "B
|
P l a i n T e x t b $ a$ CJ OJ QJ ^J 2 K@ 2
|
P l a i n T e x t b $ a$ CJ OJ QJ ^J 2 K@ 2
|
S a l u t a t i o n c $ a$ 8 @@ B8 S i g n a t u r e d $ ^a$ : '@ Q: C o m m e n t R e f e r e n c e CJ aJ
|
S a l u t a t i o n c $ a$ 8 @@ B8 S i g n a t u r e d $ ^a$ : '@ Q: C o m m e n t R e f e r e n c e CJ aJ
|
|
|
|
|
|
|
|
|
0 Zd d > r % ! z # z z z z z ! z z z z ! z z z z z
|
0 Zd d > r % ! z # z z z z z ! z z z z ! z z z z z
|
z z z
z z z z z z " z z z z z z z z z
|
z z z
z z z z z z " z z z z z z z z z
|
z z z
z 8 }
|
z z z
z 8 }
|
|
|
0 ? - X" % - 3 f8 ? F K S Y %_ c Zd d d =m Wu { | 1 2 - 1 2 O H
|
0 ? - X" % - 3 f8 ? F K S Y %_ c Zd d d =m Wu { | 1 2 - 1 2 O H
|
(
w - 2
|
(
w - 2
|
: x ; 7 , $ ! " # $
|
: x ; 7 , $ ! " # $
|
+ , - @ T U V W ` + , - . / 0 1 2 3 4 5 6 7 I P Y U U { f \ _ -
|
+ , - @ T U V W ` + , - . / 0 1 2 3 4 5 6 7 I P Y U U { f \ _ -
|
z
|
z
|
|
|
|
|
|
|
|
|
|
|
/ 0 1 > ` W
) V m ; O s - K n o p
|
/ 0 1 > ` W
) V m ; O s - K n o p
|
C I A ) * ; < = > ? @ U c | } , - B + v w ~ + M w , S | ! H p ! @! h! ! ! ! " ." :" X" " " " " # N# \# t# # # # # # # # # $ $ $ $ $ $ $ & & ' ( ]( ( ) @) A) B) ) ) j* * + + <, , !- "- - - - -
. . /. X. . . _/ `/ 0 0 0 J0 K0 q0 w1 L2 M2 2 2 2 3 3 *3 g3 4 \4 ]4 ^4 _4 4 4 q6 r6 6 6 6 =7 m7 n7 7 '8 f8 8 ,9 -9 9 9 9 : ; < = = = a= b= > > y> B@ C@ D@ @ @ A nB B C D E F F F F F G HG G G G H H H XH YH H H I I 'I 6I [I hI uI vI J J K K M M YN $P %P FP GP Q Q S S S S WS XS T U U U %V V V V V 'W xW W X !X `X X X X Y Y :Y xY Y QZ Z Z ?[ [ \ \ m\ \ ] ^ ^ "_ #_ $_ %_ &_ '_ t_ u_ `
` ` F` G` b b b Wb Xb b b c c c c c c c Yd Zd dd rd }d d d d d d d d d d e e uj j l In p Bs Su Tu Uu Vu u u v Rv fv yv zv v v y y az bz T{ U{ { { { { { { { %| r| s| | | | =~ >~ " # ? @ 5 6 ` a 0 1 ] } ~
; @ A k * + T 1 2 V D X Y z @ A B C Í č
|
C I A ) * ; < = > ? @ U c | } , - B + v w ~ + M w , S | ! H p ! @! h! ! ! ! " ." :" X" " " " " # N# \# t# # # # # # # # # $ $ $ $ $ $ $ & & ' ( ]( ( ) @) A) B) ) ) j* * + + <, , !- "- - - - -
. . /. X. . . _/ `/ 0 0 0 J0 K0 q0 w1 L2 M2 2 2 2 3 3 *3 g3 4 \4 ]4 ^4 _4 4 4 q6 r6 6 6 6 =7 m7 n7 7 '8 f8 8 ,9 -9 9 9 9 : ; < = = = a= b= > > y> B@ C@ D@ @ @ A nB B C D E F F F F F G HG G G G H H H XH YH H H I I 'I 6I [I hI uI vI J J K K M M YN $P %P FP GP Q Q S S S S WS XS T U U U %V V V V V 'W xW W X !X `X X X X Y Y :Y xY Y QZ Z Z ?[ [ \ \ m\ \ ] ^ ^ "_ #_ $_ %_ &_ '_ t_ u_ `
` ` F` G` b b b Wb Xb b b c c c c c c c Yd Zd dd rd }d d d d d d d d d d e e uj j l In p Bs Su Tu Uu Vu u u v Rv fv yv zv v v y y az bz T{ U{ { { { { { { { %| r| s| | | | =~ >~ " # ? @ 5 6 ` a 0 1 ] } ~
; @ A k * + T 1 2 V D X Y z @ A B C Í č
|
R + , - . / 0 2 3 = ) M N O P ] ҕ o p q r 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 x 0 0 @ 0 @ 0 @ x 0 x 0 0 ` ` 0 ` 0 ` 0 ` 0 ` 0 ` 0 ` 0 ` 0 ` 0 ` &0 ` 0 ` 0 ` 0 ` H 0 !0 h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 h 0 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 h 0 0 |
|
R + , - . / 0 2 3 = ) M N O P ] ҕ o p q r 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 x 0 0 @ 0 @ 0 @ x 0 x 0 0 ` ` 0 ` 0 ` 0 ` 0 ` 0 ` 0 ` 0 ` 0 ` 0 ` &0 ` 0 ` 0 ` 0 ` H 0 !0 h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 h 0 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 h 0 0 |
|
h 0 0
|
h 0 0
|
`0
|
`0
|
0 0 0 1 0 > 0 > 0 > 0 > 0 1 0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
|
0 0 0 1 0 > 0 > 0 > 0 > 0 1 0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
g -0
|
g -0
g -0
g -0
g -0
g -0
g -0
-0
-0
0 1 0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p e 0 p e 0 p e 0 p e 0 p 0 p 0 p 0 p 0 p -0 p -0 p 0 p 0 0 0 @ 0 U 0 U ( 0 U 0 } 0 } ( 0 U &0 0 ( 0 U 0 - 0 - ( 0 U 0 0 ( 0 U 0 0 ( 0 U 0 w 0 w 0 w 0 @ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 &0 &0 0 0 0 0 0 @ 0 # 0 # 0 # 0 # 0 # 0 # ( 0 # &0 $ 0 $ 0 $ 0 $ h 0 $ h 0 $ h 0 $ h 0 $ h 0 $ 0 $ 0 $ 0 $ k 0 $ k 0 ) $ k 0 ) $ k 0 ) $ k 0 $ k 0 $ k 0 $ k 0 $ 0 $ 0 $ @0 $ 0 $ 0 $ *0 $ 0 $ 0 $ i 0 $ i 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ *0 $ 0 $ 0 $ i 0 $ i 0 $ 0 $ 0 $ 0 $ 0 $ *0 $ 0 $ 0 $ j 0 $ j 0 $ j 0 $ 0 $ 0 $ 0 $ ( 0 # &0 _4 0 _4 0 _4 0 _4 m 0 _4 m 0 _4 m 0 _4 m ,0 _4 0 _4 0 _4 n 0 _4 n 0 _4 n 0 _4 n 0 _4 0 _4 0 _4 0 _4 0 _4 l 0 _4 l 0 _4 l 0 _4 l 0 _4 0 _4 0 _4 0 _4 &0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 &0 _4 0 _4 l 0 _4 l 0 _4 l 0 _4 l 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 o 0 _4 o 0 _4 o 0 _4 *0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 p ,0 _4 p 0 _4 p 0 _4 p 0 _4 p 0 _4 p 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 q 0 _4 0 _4 0 _4 0 _4 q 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 ( 0 # &0 S 0 S 0 S 0 S 0 S m 0 S m 0 S m 0 S m ,0 S 0 S 0 S u 0 S u 0 S u 0 S 0 S 0 S w 0 S u 0 S u 0 S u 0 S 0 S 0 S r 0 S r 0 S r 0 S r 0 Y S r 0 Y S r 0 Y S r 0 Y S r 0 Y S 0 S 0 S x 0 S t 0 S t 0 S t 0 S t 0 S 0 S 0 S 0 S 0 S 0 S 0 S &0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S y` 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y@ 0
|
g -0
g -0
g -0
g -0
g -0
g -0
-0
-0
0 1 0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p -0 p 0 p 0 p 0 p 0 p 0 p 0 p 0 p e 0 p e 0 p e 0 p e 0 p 0 p 0 p 0 p 0 p -0 p -0 p 0 p 0 0 0 @ 0 U 0 U ( 0 U 0 } 0 } ( 0 U &0 0 ( 0 U 0 - 0 - ( 0 U 0 0 ( 0 U 0 0 ( 0 U 0 w 0 w 0 w 0 @ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 &0 &0 0 0 0 0 0 @ 0 # 0 # 0 # 0 # 0 # 0 # ( 0 # &0 $ 0 $ 0 $ 0 $ h 0 $ h 0 $ h 0 $ h 0 $ h 0 $ 0 $ 0 $ 0 $ k 0 $ k 0 ) $ k 0 ) $ k 0 ) $ k 0 $ k 0 $ k 0 $ k 0 $ 0 $ 0 $ @0 $ 0 $ 0 $ *0 $ 0 $ 0 $ i 0 $ i 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ *0 $ 0 $ 0 $ i 0 $ i 0 $ 0 $ 0 $ 0 $ 0 $ *0 $ 0 $ 0 $ j 0 $ j 0 $ j 0 $ 0 $ 0 $ 0 $ ( 0 # &0 _4 0 _4 0 _4 0 _4 m 0 _4 m 0 _4 m 0 _4 m ,0 _4 0 _4 0 _4 n 0 _4 n 0 _4 n 0 _4 n 0 _4 0 _4 0 _4 0 _4 0 _4 l 0 _4 l 0 _4 l 0 _4 l 0 _4 0 _4 0 _4 0 _4 &0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 &0 _4 0 _4 l 0 _4 l 0 _4 l 0 _4 l 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 o 0 _4 o 0 _4 o 0 _4 *0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 p ,0 _4 p 0 _4 p 0 _4 p 0 _4 p 0 _4 p 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 q 0 _4 0 _4 0 _4 0 _4 q 0 _4 0 _4 0 _4 0 _4 0 _4 0 _4 ( 0 # &0 S 0 S 0 S 0 S 0 S m 0 S m 0 S m 0 S m ,0 S 0 S 0 S u 0 S u 0 S u 0 S 0 S 0 S w 0 S u 0 S u 0 S u 0 S 0 S 0 S r 0 S r 0 S r 0 S r 0 Y S r 0 Y S r 0 Y S r 0 Y S r 0 Y S 0 S 0 S x 0 S t 0 S t 0 S t 0 S t 0 S 0 S 0 S 0 S 0 S 0 S 0 S &0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S 0 S y` 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y 0 S y@ 0
|
S 0 S 0 S 0 S 0 S 0 S z 0 S z 0 S z 0 S z 0 S z 0 S 0 S 0 S 0 S ( 0 # &0 Vu 0 Vu 0 Vu { 0 Vu { 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu &0 Vu 0 Vu ( 0 # &0 | 0 | 0 | 0 | 0 | 0 0 | 0 0 0 0 0 | 0 0 &0 0 0 | 0 6 0 6 &0 6 0 0 | 0 1 0 1 0 0 | 0 ~ 0 ~ 0 0 | 0 0 0 0 | 0 A 0 A 0 0 | 0 + @ 0 + 0 0 | 0 2 @ 0 2 0 0 | 0 0 0 0 | 0 Y 0 Y 0 0 | 0 0 0 0 0 0 0 0 0 | 0 č @ 0 č 0 0 | 0 @ 0 0 0 | 0 0 0 0 0 @ 0 0 0 &0 &0 &0 &0 0 0 0 0 0 0 0 0 ,0 ,0 0 0 0 0 0 0 0 0 3 0 3 0 0 0 0 -0 -0 -0 0 0 0 0 P -0 P -0 P -0 P -0 P -0 P 60 P 0 0 0 0 0 0 0 0 0 0 0 T T q q q q q q q q q q q q q q q t m 7 }
|
S 0 S 0 S 0 S 0 S 0 S z 0 S z 0 S z 0 S z 0 S z 0 S 0 S 0 S 0 S ( 0 # &0 Vu 0 Vu 0 Vu { 0 Vu { 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu 0 Vu &0 Vu 0 Vu ( 0 # &0 | 0 | 0 | 0 | 0 | 0 0 | 0 0 0 0 0 | 0 0 &0 0 0 | 0 6 0 6 &0 6 0 0 | 0 1 0 1 0 0 | 0 ~ 0 ~ 0 0 | 0 0 0 0 | 0 A 0 A 0 0 | 0 + @ 0 + 0 0 | 0 2 @ 0 2 0 0 | 0 0 0 0 | 0 Y 0 Y 0 0 | 0 0 0 0 0 0 0 0 0 | 0 č @ 0 č 0 0 | 0 @ 0 0 0 | 0 0 0 0 0 @ 0 0 0 &0 &0 &0 &0 0 0 0 0 0 0 0 0 ,0 ,0 0 0 0 0 0 0 0 0 3 0 3 0 0 0 0 -0 -0 -0 0 0 0 0 P -0 P -0 P -0 P -0 P -0 P 60 P 0 0 0 0 0 0 0 0 0 0 0 T T q q q q q q q q q q q q q q q t m 7 }
|
. K ' _8 P f s U ] ^ _ ` a b c d e f g l q u x | ~ + 0 7 - V > - w" & , 2 _8 aA L W :] Fd h b~ 6 ] V X Y Z [ \ h i j k m n o p r s t v w y z { } W ` I ^ _ ~
0 K M N P o 6 9 T V W Y x 5 P R S U t 5 P R S U t 9 [ v x y { E ` c d f < W Y Z \ { 4 ? Z \ ] _ ~
|
. K ' _8 P f s U ] ^ _ ` a b c d e f g l q u x | ~ + 0 7 - V > - w" & , 2 _8 aA L W :] Fd h b~ 6 ] V X Y Z [ \ h i j k m n o p r s t v w y z { } W ` I ^ _ ~
0 K M N P o 6 9 T V W Y x 5 P R S U t 5 P R S U t 9 [ v x y { E ` c d f < W Y Z \ { 4 ? Z \ ] _ ~
|
|
|
|
|
(
|
(
|
*
|
*
|
+
|
+
|
-
|
-
|
L
|
L
|
Z
|
Z
|
u
|
u
|
w
|
w
|
x
|
x
|
z
|
z
|
|
|
|
|
|
|
|
|
-
tX%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%̕
* 9 O V X ] k n t !tX!tX!tBt P 2 o R $ Ny
U Cs3 +2 $ 2)fD"yuT $ +b $ Rw]SEY2 +2 $ Yn8]' 3 +R $ ~kSX._" z +b $ &4` M +@ 0 ( H0
|
-
tX%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%X%̕
* 9 O V X ] k n t !tX!tX!tBt P 2 o R $ Ny
U Cs3 +2 $ 2)fD"yuT $ +b $ Rw]SEY2 +2 $ Yn8]' 3 +R $ ~kSX._" z +b $ &4` M +@ 0 ( H0
|
B
|
B
|
S ? (
|
S ? (
|
|
|
|
|
|
|
S L A . ` R `T R `T t & _ T o c 6 6 5 0 0 9 7 _ T o c 1 7 0 2 2 7 5 8 I n t r o d u c t i o n _ T o c 1 7 0 2 2 7 5 9 _ T o c 1 7 0 2 2 7 6 0 _ T o c 1 7 0 2 2 7 6 1 _ T o c 1 7 0 2 2 7 6 2 _ T o c 6 6 5 0 0 9 9 _ T o c 1 7 0 2 2 7 6 3 _ T o c 1 7 0 2 2 7 6 4 _ T o c 3 9 7 0 6 7 0 _ T o c 1 7 0 2 2 7 6 5 _ T o c 1 7 0 2 2 7 6 6 _ T o c 1 7 0 2 2 7 6 7 _ T o c 1 7 0 2 2 7 6 8 _ T o c 1 7 0 2 2 7 6 9 _ T o c 1 7 0 2 2 7 7 0 _ T o c 1 7 0 2 2 7 7 1 _ T o c 1 7 0 2 2 7 7 2 _ T o c 1 7 0 2 2 7 7 3 _ T o c 1 7 0 2 2 7 7 4 _ T o c 1 7 0 2 2 7 7 5 _ T o c 1 7 0 2 2 7 7 6 _ T o c 1 7 0 2 2 7 7 7 _ R e f 4 3 8 7 0 3 3 _ T o c 6 6 5 0 1 0 7 _ T o c 1 7 0 2 2 7 7 8 C l o c k s _ T o c 1 7 0 2 2 7 7 9 _ T o c 6 6 5 0 1 2 9 _ T o c 1 7 0 2 2 7 8 0 _ T o c 1 7 0 2 2 7 8 1 _ T o c 6 6 5 0 1 5 1 _ T o c 1 7 0 2 2 7 8 2 _ T o c 1 7 0 2 2 7 8 3
_ H l t 5 1 9 4 1 3 6 1 6
_ T o c 5 1 3 5 3 2 4 9 4
_ T o c 5 1 4 3 8 6 8 5 9 0 0 1 1 >
p ? ? @ U U } - # $ _4 S Wu | 2 2 2 3 3 O O P
|
S L A . ` R `T R `T t & _ T o c 6 6 5 0 0 9 7 _ T o c 1 7 0 2 2 7 5 8 I n t r o d u c t i o n _ T o c 1 7 0 2 2 7 5 9 _ T o c 1 7 0 2 2 7 6 0 _ T o c 1 7 0 2 2 7 6 1 _ T o c 1 7 0 2 2 7 6 2 _ T o c 6 6 5 0 0 9 9 _ T o c 1 7 0 2 2 7 6 3 _ T o c 1 7 0 2 2 7 6 4 _ T o c 3 9 7 0 6 7 0 _ T o c 1 7 0 2 2 7 6 5 _ T o c 1 7 0 2 2 7 6 6 _ T o c 1 7 0 2 2 7 6 7 _ T o c 1 7 0 2 2 7 6 8 _ T o c 1 7 0 2 2 7 6 9 _ T o c 1 7 0 2 2 7 7 0 _ T o c 1 7 0 2 2 7 7 1 _ T o c 1 7 0 2 2 7 7 2 _ T o c 1 7 0 2 2 7 7 3 _ T o c 1 7 0 2 2 7 7 4 _ T o c 1 7 0 2 2 7 7 5 _ T o c 1 7 0 2 2 7 7 6 _ T o c 1 7 0 2 2 7 7 7 _ R e f 4 3 8 7 0 3 3 _ T o c 6 6 5 0 1 0 7 _ T o c 1 7 0 2 2 7 7 8 C l o c k s _ T o c 1 7 0 2 2 7 7 9 _ T o c 6 6 5 0 1 2 9 _ T o c 1 7 0 2 2 7 8 0 _ T o c 1 7 0 2 2 7 8 1 _ T o c 6 6 5 0 1 5 1 _ T o c 1 7 0 2 2 7 8 2 _ T o c 1 7 0 2 2 7 8 3
_ H l t 5 1 9 4 1 3 6 1 6
_ T o c 5 1 3 5 3 2 4 9 4
_ T o c 5 1 4 3 8 6 8 5 9 0 0 1 1 >
p ? ? @ U U } - # $ _4 S Wu | 2 2 2 3 3 O O P
|
! " # $ % 0 0 = = _
? ? T Y b A * # $ 4 VS u | 2 2 3 < O O \ K S T L O D G ) * 6 7 ` b 9 | ! * C L e v ! + D R k { 9 G ` p ! ! +! ?! X! g! ! ! ! ! ! ! ! " " -" J" W" h" " " " " " " " D# G# l# s# # # # # # # # $
|
! " # $ % 0 0 = = _
? ? T Y b A * # $ 4 VS u | 2 2 3 < O O \ K S T L O D G ) * 6 7 ` b 9 | ! * C L e v ! + D R k { 9 G ` p ! ! +! ?! X! g! ! ! ! ! ! ! ! " " -" J" W" h" " " " " " " " D# G# l# s# # # # # # # # $
|
$ $ $ *$ ,$ :$ <$ J$ L$ [$ h% m% C& F& V& Y& m& r& 4' B' D' R' T' g' ' ' ' ' ( ( H( [( f( p( ( ( .) 7) *
|
$ $ $ *$ ,$ :$ <$ J$ L$ [$ h% m% C& F& V& Y& m& r& 4' B' D' R' T' g' ' ' ' ' ( ( H( [( f( p( ( ( .) 7) *
|
* [* ^* `- h- - - - . S. V. q. v. . . / / d/ u/ 60 B0 O0 [0 0 0 :1 =1 1 1 1 1 2 "2 =2 B2 M2 P2 m2 p2 2 2 3 3 b3 e3 g3 r3 3 3 3 3 4 4 N5 R5 5 5 6 6 6 6 6
7 =7 I7 7 7 7 7 7 7 ]8 c8 8 8 8 8 8 9 9 9 ?: D: s: x: : : : : : : : : ; ; V< [< < < < < < < U= ^= )@ 1@ {@ @ eA tA A A 4B 9B qB vB B B ]C bC C C :F AF F F F F G G HG RG G G 6H >H GH UH H H I I I I I J BJ GJ TJ XJ J J L M M M O O O P bP kP P P P P FT PT mT uT T T U U %V /V V V V V 3W 7W W W W W W W uX {X X X X X X Y hY nY Y Y Z Z m\ y\ \ \ ] ] ] ] ^ ^ ^ ^ ^ ^ ^ ^ h_ q_ 8` D` ` ` da na a a Eb Ub xb b b b %c +c @c Gc c c d )d Zd cd dd qd d d d d d d d d d d d d d d d d Le Te re {e f f qg ~g g g h h h h h h /j 7j k k l )l Rl Zl ~l l m m m m n 'n [o co o o @p Jp sp {p p p Br Jr r r r r s !s t t t u )u 2u Rv ev fv xv ,y ?y _y ry z z 5z Gz { { { *{ ,{ 5{ 7{ B{ D{ Q{ { { { { { { | | |
| | | | | | | f| o| ~ ~ ~ ~ 3 D C K ޅ Ć Ն lj - / W ҋ F { nj ߌ č ̍ ͍ ؍ ڍ
s v w _ M C G I A ' * : } ! $ C F e h ! $ D G k n 9 < ` o p ! ! +! .! X! [! ! ! ! ! ! ! ! ! " !" 6" 9" J" M" h" k" " " " " " " # # I# M# V# [# l# s# # # $ $ 6 6 6 6 6 7 =7 @7 ; ; < < J K M M %P )P U U %V (V V V V V j j q q /t 7t Rv Uv fv iv zv v | "| ~ ~ č q s : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ` 7 I 0 3 i g o r m 3 C : \ c v s r o o t \ e t h e r n e t \ d o c \ s r c \ e t h _ d e s i g n _ d o c u m e n t . d o c i g o r m 3 C : \ c v s r o o t \ e t h e r n e t \ d o c \ s r c \ e t h _ d e s i g n _ d o c u m e n t . d o c i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m 3 C : \ c v s r o o t \ e t h e r n e t \ d o c \ s r c \ e t h _ d e s i g n _ d o c u m e n t . d o c i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d r | ,^ }>_] ~\ Q|0 >qhV (U 4
|
* [* ^* `- h- - - - . S. V. q. v. . . / / d/ u/ 60 B0 O0 [0 0 0 :1 =1 1 1 1 1 2 "2 =2 B2 M2 P2 m2 p2 2 2 3 3 b3 e3 g3 r3 3 3 3 3 4 4 N5 R5 5 5 6 6 6 6 6
7 =7 I7 7 7 7 7 7 7 ]8 c8 8 8 8 8 8 9 9 9 ?: D: s: x: : : : : : : : : ; ; V< [< < < < < < < U= ^= )@ 1@ {@ @ eA tA A A 4B 9B qB vB B B ]C bC C C :F AF F F F F G G HG RG G G 6H >H GH UH H H I I I I I J BJ GJ TJ XJ J J L M M M O O O P bP kP P P P P FT PT mT uT T T U U %V /V V V V V 3W 7W W W W W W W uX {X X X X X X Y hY nY Y Y Z Z m\ y\ \ \ ] ] ] ] ^ ^ ^ ^ ^ ^ ^ ^ h_ q_ 8` D` ` ` da na a a Eb Ub xb b b b %c +c @c Gc c c d )d Zd cd dd qd d d d d d d d d d d d d d d d d Le Te re {e f f qg ~g g g h h h h h h /j 7j k k l )l Rl Zl ~l l m m m m n 'n [o co o o @p Jp sp {p p p Br Jr r r r r s !s t t t u )u 2u Rv ev fv xv ,y ?y _y ry z z 5z Gz { { { *{ ,{ 5{ 7{ B{ D{ Q{ { { { { { { | | |
| | | | | | | f| o| ~ ~ ~ ~ 3 D C K ޅ Ć Ն lj - / W ҋ F { nj ߌ č ̍ ͍ ؍ ڍ
s v w _ M C G I A ' * : } ! $ C F e h ! $ D G k n 9 < ` o p ! ! +! .! X! [! ! ! ! ! ! ! ! ! " !" 6" 9" J" M" h" k" " " " " " " # # I# M# V# [# l# s# # # $ $ 6 6 6 6 6 7 =7 @7 ; ; < < J K M M %P )P U U %V (V V V V V j j q q /t 7t Rv Uv fv iv zv v | "| ~ ~ č q s : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ` 7 I 0 3 i g o r m 3 C : \ c v s r o o t \ e t h e r n e t \ d o c \ s r c \ e t h _ d e s i g n _ d o c u m e n t . d o c i g o r m 3 C : \ c v s r o o t \ e t h e r n e t \ d o c \ s r c \ e t h _ d e s i g n _ d o c u m e n t . d o c i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m 3 C : \ c v s r o o t \ e t h e r n e t \ d o c \ s r c \ e t h _ d e s i g n _ d o c u m e n t . d o c i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d i g o r m l C : \ D o c u m e n t s a n d S e t t i n g s \ i g o r m \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ W o r d \ A u t o R e c o v e r y s a v e o f e t h _ d e s i g n _ d o c u m e n t . a s d r | ,^ }>_] ~\ Q|0 >qhV (U 4
|
T . *t/ - C>r iOJe f3zB "_ 7w< z
|
T . *t/ - C>r iOJe f3zB "_ 7w< z
|
,]P\ %,r3 1Z 3(6,V b ~ "N ! p6
|
,]P\ %,r3 1Z 3(6,V b ~ "N ! p6
|
rBJb _Q
V e/
x 98d s <3l V Cr[ )"
|
rBJb _Q
V e/
x 98d s <3l V Cr[ )"
|
: xU f F 1p BR #Zj ,n$ƺ *%vF ,% H F&*4U v|'.
|
: xU f F 1p BR #Zj ,n$ƺ *%vF ,% H F&*4U v|'.
|
r'p "Q ' 3K )V { +)J|e Ow/) *W 0x=PO /C0 w50l ^A3X7 ,l5\C kE8*4U 9A
|
r'p "Q ' 3K )V { +)J|e Ow/) *W 0x=PO /C0 w50l ^A3X7 ,l5\C kE8*4U 9A
|
;Ð t>, >>> V?P$3 ?@TJ P@f .EU R@F s4F 4?F Gֱ ,/GwJ RjH2. 4qYJ}L9 wM: ?gLOoT 4ROVVl c&EP|mXx }Rz Z$TH| g !UI &|VP TV&#L VYE S Z' 9x\Z8 :_N 2``" Hak 2b}n :bfl? eV dF ~W od&SN Q5pe}D gj8hNjo e_h& ia %k8^ l:J< y 6mf& m !G?n\2 #/oƺ 0&o~҈ 9? q% jst~ CCv GBx} eGxƖ? Vy! -y;z
|
;Ð t>, >>> V?P$3 ?@TJ P@f .EU R@F s4F 4?F Gֱ ,/GwJ RjH2. 4qYJ}L9 wM: ?gLOoT 4ROVVl c&EP|mXx }Rz Z$TH| g !UI &|VP TV&#L VYE S Z' 9x\Z8 :_N 2``" Hak 2b}n :bfl? eV dF ~W od&SN Q5pe}D gj8hNjo e_h& ia %k8^ l:J< y 6mf& m !G?n\2 #/oƺ 0&o~҈ 9? q% jst~ CCv GBx} eGxƖ? Vy! -y;z
|
U2@z- 9^z 7ezl$ yF{hL E { |xFu p\|B B%} > 9~& zh3 ^` . ^` . 8 8^8` . ^` . ^`OJ QJ o( ^`OJ QJ o( 8 8^8`OJ QJ o( 8 ^`CJ OJ QJ o( h h^h` . h h h^h`CJ OJ QJ o( * h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( @ ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^`OJ PJ QJ ^J o( - ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h h^h`OJ QJ o( h 8 8^8`OJ QJ o( o h ^`OJ QJ o( h ^ `OJ QJ o( h ^ `OJ QJ o( o h x x^x`OJ QJ o( h H H^H`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( ^ ` 56 CJ` OJ QJ o( A p p e n d i x A h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h h^h`OJ QJ o( h 8 8^8`OJ QJ o( o h ^`OJ QJ o( h ^ `OJ QJ o( h ^ `OJ QJ o( o h x x^x`OJ QJ o( h H H^H`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H
0 ^`0o( ^` . L ^ `L . ^ ` . x x^x` . HL H^H`L . ^` . ^` . L ^`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( @ ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h T T^T`OJ QJ o( o h $ $ ^$ `OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h d d^d`OJ QJ o( h 4 4^4`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h h h^h`OJ QJ o( h 8 8^8`OJ QJ o( o h ^`OJ QJ o( h ^ `OJ QJ o( h ^ `OJ QJ o( o h x x^x`OJ QJ o( h H H^H`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h` . P ^`P . . ^` . . . x ^`x . . . . ^`
|
U2@z- 9^z 7ezl$ yF{hL E { |xFu p\|B B%} > 9~& zh3 ^` . ^` . 8 8^8` . ^` . ^`OJ QJ o( ^`OJ QJ o( 8 8^8`OJ QJ o( 8 ^`CJ OJ QJ o( h h^h` . h h h^h`CJ OJ QJ o( * h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( @ ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^`OJ PJ QJ ^J o( - ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h h^h`OJ QJ o( h 8 8^8`OJ QJ o( o h ^`OJ QJ o( h ^ `OJ QJ o( h ^ `OJ QJ o( o h x x^x`OJ QJ o( h H H^H`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( ^ ` 56 CJ` OJ QJ o( A p p e n d i x A h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h h^h`OJ QJ o( h 8 8^8`OJ QJ o( o h ^`OJ QJ o( h ^ `OJ QJ o( h ^ `OJ QJ o( o h x x^x`OJ QJ o( h H H^H`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H
0 ^`0o( ^` . L ^ `L . ^ ` . x x^x` . HL H^H`L . ^` . ^` . L ^`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( @ ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h T T^T`OJ QJ o( o h $ $ ^$ `OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h d d^d`OJ QJ o( h 4 4^4`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h h h^h`OJ QJ o( h 8 8^8`OJ QJ o( o h ^`OJ QJ o( h ^ `OJ QJ o( h ^ `OJ QJ o( o h x x^x`OJ QJ o( h H H^H`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h` . P ^`P . . ^` . . . x ^`x . . . . ^`
|
. . . . .
|
. . . . .
|
X ^
|
X ^
|
`X . . . . . .
^ ` . . . . . . .
8 ^`8 . . . . . . . .
` ^`` . . . . . . . . . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h` h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( @ ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 0 ^`0o( ^` . L ^ `L . ^ ` . x x^x` . HL H^H`L . ^` . ^` . L ^`L . h 8 8^8`OJ QJ o( h ^`OJ QJ o( o h ^ `OJ QJ o( h ^ `OJ QJ o( h x x^x`OJ QJ o( o h H H^H`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h^ ` 56 CJ` OJ QJ o( I n d e x h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h h^h` . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( ^ ` 56 CJ` OJ QJ o( A p p e n d i x B h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h^ ` 56 CJ` OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 0 ^`0o( ^` . L ^ `L . ^ ` . x x^x` . HL H^H`L . ^` . ^` . L ^`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h` . h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 0 ^`0o( ^` . L ^ `L . ^ ` . x x^x` . HL H^H`L . ^` . ^` . L ^`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h 8 8^8`OJ QJ o( h ^`OJ QJ o( o h ^ `OJ QJ o( h ^ `OJ QJ o( h x x^x`OJ QJ o( o h H H^H`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h h^h`OJ QJ o( h ~ ~^~`OJ QJ o( h H h N N^N`OJ QJ ^J o( h H o h
|
`X . . . . . .
^ ` . . . . . . .
8 ^`8 . . . . . . . .
` ^`` . . . . . . . . . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h` h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( @ ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 0 ^`0o( ^` . L ^ `L . ^ ` . x x^x` . HL H^H`L . ^` . ^` . L ^`L . h 8 8^8`OJ QJ o( h ^`OJ QJ o( o h ^ `OJ QJ o( h ^ `OJ QJ o( h x x^x`OJ QJ o( o h H H^H`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h^ ` 56 CJ` OJ QJ o( I n d e x h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h h^h` . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( ^ ` 56 CJ` OJ QJ o( A p p e n d i x B h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h^ ` 56 CJ` OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 0 ^`0o( ^` . L ^ `L . ^ ` . x x^x` . HL H^H`L . ^` . ^` . L ^`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h` . h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h | | ^| `OJ QJ o( h L L^L`OJ QJ o( o h ^ `OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 0 ^`0o( ^` . L ^ `L . ^ ` . x x^x` . HL H^H`L . ^` . ^` . L ^`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h 8 8^8`OJ QJ o( h ^`OJ QJ o( o h ^ `OJ QJ o( h ^ `OJ QJ o( h x x^x`OJ QJ o( o h H H^H`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h h^h`OJ QJ o( h ~ ~^~`OJ QJ o( h H h N N^N`OJ QJ ^J o( h H o h
|
|
|
^
|
^
|
`OJ QJ o( h H h ^ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^ ^^^`OJ QJ o( h H h . .^.`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h` . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( > ,l5 c&EP 9^z E { :_ e/
wM ~ } | wM e/
gj8h TV :_ 4qYJ V? i %k RjH R@F tD: H: ?@ "_ P@ ,n$ #/o 0&o { +) eGx 9 t> 2` 1p l p6
|
`OJ QJ o( h H h ^ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^ ^^^`OJ QJ o( h H h . .^.`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h` . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h p p^p`OJ QJ o( h H h @ @ ^@ `OJ QJ o( h H h ^`OJ QJ ^J o( h H o h ^`OJ QJ o( h H h ^`OJ QJ o( h H h ^`OJ QJ ^J o( h H o h P P^P`OJ QJ o( h H h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( > ,l5 c&EP 9^z E { :_ e/
wM ~ } | wM e/
gj8h TV :_ 4qYJ V? i %k RjH R@F tD: H: ?@ "_ P@ ,n$ #/o 0&o { +) eGx 9 t> 2` 1p l p6
|
B%} js y 6m Q5pe CCv "N Vy ,% f3 b _Q
3K ) 7w Z$T x g !U .E s
|
B%} js y 6m Q5pe CCv "N Vy ,% f3 b _Q
3K ) 7w Z$T x g !U .E s
|
; !G?n z # -y;z 9x\ ^A3 1 ,] |H: U2@z %, iO H: 9~ eV d f }R od Ow/ F& kE8 Ha 3(6 zh s4F 2b )" 9? q ?gLO :b w50 <3 *W 0 Z 4?F yF{ G 9
|
; !G?n z # -y;z 9x\ ^A3 1 ,] |H: U2@z %, iO H: 9~ eV d f }R od Ow/ F& kE8 Ha 3(6 zh s4F 2b )" 9? q ?gLO :b w50 <3 *W 0 Z 4?F yF{ G 9
|
r' &|V | v|' m p\| GBx /C0 7ez 4RO e_h ' Cr[ 9 PI: /C0 I: 4RO I: m 4J: e_h J: GBx J: *% ,/G VY D: @ ^`OJ QJ o( E:! ^`OJ QJ o( o xE:" p p^p`OJ QJ o( E:# @ @ ^@ `OJ QJ o( 8F:$ ^`OJ QJ o( o F:% ^`OJ QJ o( F:& ^`OJ QJ o( XG:' ^`OJ QJ o( o G:( P P^P`OJ QJ o( $H: @ ^`OJ QJ o( H: @ ^`5 6 >* CJ OJ QJ o( H: @ @ ^`OJ QJ o( 0 Qf 1 11 61 M 0 0 Qf 1 11 61 M 0 0 j S0 M 0 0 j S0 M 0 0 ɛ S0 M 0 0 ֛ S0 M 0 r r *^2NpVX!fF46@B C>r D|1:H2*` )@̖ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ . $ $ $ $ $ $ $ $ C>r $ $ $ $ $ $ $ $ $ nRdXh\&b4fҸ /$6I $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ C>r < $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ h $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ Zx $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ ` + , - . / 0 1 2 3 4 5 6 c Yd Zd dd rd }d d d d d d d d d d e e j -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} @ @ U n k n o w n J e a n n e W i e g e l m a n n
|
r' &|V | v|' m p\| GBx /C0 7ez 4RO e_h ' Cr[ 9 PI: /C0 I: 4RO I: m 4J: e_h J: GBx J: *% ,/G VY D: @ ^`OJ QJ o( E:! ^`OJ QJ o( o xE:" p p^p`OJ QJ o( E:# @ @ ^@ `OJ QJ o( 8F:$ ^`OJ QJ o( o F:% ^`OJ QJ o( F:& ^`OJ QJ o( XG:' ^`OJ QJ o( o G:( P P^P`OJ QJ o( $H: @ ^`OJ QJ o( H: @ ^`5 6 >* CJ OJ QJ o( H: @ @ ^`OJ QJ o( 0 Qf 1 11 61 M 0 0 Qf 1 11 61 M 0 0 j S0 M 0 0 j S0 M 0 0 ɛ S0 M 0 0 ֛ S0 M 0 r r *^2NpVX!fF46@B C>r D|1:H2*` )@̖ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ . $ $ $ $ $ $ $ $ C>r $ $ $ $ $ $ $ $ $ nRdXh\&b4fҸ /$6I $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ C>r < $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ h $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ Zx $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ ` + , - . / 0 1 2 3 4 5 6 c Yd Zd dd rd }d d d d d d d d d d e e j -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} -O} @ @ U n k n o w n J e a n n e W i e g e l m a n n
|
G z T i m e s N e w R o m a n 5 S y m b o l 3& z A r i a l U T i m e s N e w R o m a n P S - B o l d M T K T i m e s N e w R o m a n P S M T 7 A r i a l M T 9 G a r a m o n d A" G e n e v a A r i a l ?5 z C o u r i e r N e w ; W i n g d i n g s " p h cCthfSWF8* 6{ % ? e % G ( >0 d O w +
2Q H C : \ D o c u m e n t s a n d S e t t i n g s \ j e a n n e \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ T e m p l a t e s \ F l e x t r o n i c s T e m p l a t e s \ S p e c i f i c a t i o n s T e m p l a t e F l e x D e s i g n . d o t S p e c i f i c a t i o n s T e m p l a t e " T e m p l a t e f o r C o r e ' s S p e c i f i c a t i o n s I g o r M o h o r i g o r m Oh +'0 4 D P
|
G z T i m e s N e w R o m a n 5 S y m b o l 3& z A r i a l U T i m e s N e w R o m a n P S - B o l d M T K T i m e s N e w R o m a n P S M T 7 A r i a l M T 9 G a r a m o n d A" G e n e v a A r i a l ?5 z C o u r i e r N e w ; W i n g d i n g s " p h cCthfSWF8* 6{ % ? e % G ( >0 d O w +
2Q H C : \ D o c u m e n t s a n d S e t t i n g s \ j e a n n e \ A p p l i c a t i o n D a t a \ M i c r o s o f t \ T e m p l a t e s \ F l e x t r o n i c s T e m p l a t e s \ S p e c i f i c a t i o n s T e m p l a t e F l e x D e s i g n . d o t S p e c i f i c a t i o n s T e m p l a t e " T e m p l a t e f o r C o r e ' s S p e c i f i c a t i o n s I g o r M o h o r i g o r m Oh +'0 4 D P
|
l x
Specifications Template # Template for Core's Specifications s
|
l x
Specifications Template # Template for Core's Specifications s
|
IgorMohor or gor ( Specifications Template Flex Design.dot igorm ic 427 Microsoft Word 9.0 l@ P3 @ Z]@ @ ^<@ *"C % 6{ ՜. +,D ՜. +,\
p x
|
IgorMohor or gor ( Specifications Template Flex Design.dot igorm ic 427 Microsoft Word 9.0 l@ P3 @ Z]@ @ ^<@ *"C % 6{ ՜. +,D ՜. +,\
p x
|
Opencores wi ? O
|
Opencores wi ? O
|
Specifications Template Title 8 @ _PID_HLINKS A < ;
_ T o c 1 7 0 2 2 7 8 3 ;
_ T o c 1 7 0 2 2 7 8 2 ;
_ T o c 1 7 0 2 2 7 8 1 ;
_ T o c 1 7 0 2 2 7 8 0 4
_ T o c 1 7 0 2 2 7 7 9 4 }
_ T o c 1 7 0 2 2 7 7 8 4 w
_ T o c 1 7 0 2 2 7 7 7 4 q
_ T o c 1 7 0 2 2 7 7 6 4 k
_ T o c 1 7 0 2 2 7 7 5 4 e
_ T o c 1 7 0 2 2 7 7 4 4 _
_ T o c 1 7 0 2 2 7 7 3 4 Y
_ T o c 1 7 0 2 2 7 7 2 4 S
_ T o c 1 7 0 2 2 7 7 1 4 M
_ T o c 1 7 0 2 2 7 7 0 5 G
_ T o c 1 7 0 2 2 7 6 9 5 A
_ T o c 1 7 0 2 2 7 6 8 5 ;
_ T o c 1 7 0 2 2 7 6 7 5 5
_ T o c 1 7 0 2 2 7 6 6 5 /
_ T o c 1 7 0 2 2 7 6 5 5 )
_ T o c 1 7 0 2 2 7 6 4 5 #
_ T o c 1 7 0 2 2 7 6 3 5
_ T o c 1 7 0 2 2 7 6 2 5
_ T o c 1 7 0 2 2 7 6 1 5
_ T o c 1 7 0 2 2 7 6 0 6
_ T o c 1 7 0 2 2 7 5 9 6
_ T o c 1 7 0 2 2 7 5 8 K h t t p : / / w w w . o p e n c o r e s . o r g / K h t t p : / / w w w . o p e n c o r e s . o r g / w i s h l o g o
|
Specifications Template Title 8 @ _PID_HLINKS A < ;
_ T o c 1 7 0 2 2 7 8 3 ;
_ T o c 1 7 0 2 2 7 8 2 ;
_ T o c 1 7 0 2 2 7 8 1 ;
_ T o c 1 7 0 2 2 7 8 0 4
_ T o c 1 7 0 2 2 7 7 9 4 }
_ T o c 1 7 0 2 2 7 7 8 4 w
_ T o c 1 7 0 2 2 7 7 7 4 q
_ T o c 1 7 0 2 2 7 7 6 4 k
_ T o c 1 7 0 2 2 7 7 5 4 e
_ T o c 1 7 0 2 2 7 7 4 4 _
_ T o c 1 7 0 2 2 7 7 3 4 Y
_ T o c 1 7 0 2 2 7 7 2 4 S
_ T o c 1 7 0 2 2 7 7 1 4 M
_ T o c 1 7 0 2 2 7 7 0 5 G
_ T o c 1 7 0 2 2 7 6 9 5 A
_ T o c 1 7 0 2 2 7 6 8 5 ;
_ T o c 1 7 0 2 2 7 6 7 5 5
_ T o c 1 7 0 2 2 7 6 6 5 /
_ T o c 1 7 0 2 2 7 6 5 5 )
_ T o c 1 7 0 2 2 7 6 4 5 #
_ T o c 1 7 0 2 2 7 6 3 5
_ T o c 1 7 0 2 2 7 6 2 5
_ T o c 1 7 0 2 2 7 6 1 5
_ T o c 1 7 0 2 2 7 6 0 6
_ T o c 1 7 0 2 2 7 5 9 6
_ T o c 1 7 0 2 2 7 5 8 K h t t p : / / w w w . o p e n c o r e s . o r g / K h t t p : / / w w w . o p e n c o r e s . o r g / w i s h l o g o
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u w x y z { | } R o o t E n t r y F RC D a t a
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u w x y z { | } R o o t E n t r y F RC D a t a
|
n& 1 T a b l e W o r d D o c u m e n t ( S u m m a r y I n f o r m a t i o n ( v D o c u m e n t S u m m a r y I n f o r m a t i o n 8 ~ C o m p O b j j O b j e c t P o o l RCRC
|
n& 1 T a b l e W o r d D o c u m e n t ( S u m m a r y I n f o r m a t i o n ( v D o c u m e n t S u m m a r y I n f o r m a t i o n 8 ~ C o m p O b j j O b j e c t P o o l RCRC
|
F Microsoft Word Document
|
F Microsoft Word Document
|
|
|
