//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// eth_macstatus.v ////
|
//// eth_macstatus.v ////
|
//// ////
|
//// ////
|
//// This file is part of the Ethernet IP core project ////
|
//// This file is part of the Ethernet IP core project ////
|
//// http://www.opencores.org/projects/ethmac/ ////
|
//// http://www.opencores.org/projects/ethmac/ ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Igor Mohor (igorM@opencores.org) ////
|
//// - Igor Mohor (igorM@opencores.org) ////
|
//// ////
|
//// ////
|
//// All additional information is avaliable in the Readme.txt ////
|
//// All additional information is avaliable in the Readme.txt ////
|
//// file. ////
|
//// file. ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2001 Authors ////
|
//// Copyright (C) 2001 Authors ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.5 2002/02/08 16:21:54 mohor
|
|
// Rx status is written back to the BD.
|
|
//
|
// Revision 1.4 2002/01/23 10:28:16 mohor
|
// Revision 1.4 2002/01/23 10:28:16 mohor
|
// Link in the header changed.
|
// Link in the header changed.
|
//
|
//
|
// Revision 1.3 2001/10/19 08:43:51 mohor
|
// Revision 1.3 2001/10/19 08:43:51 mohor
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// eth_timescale.v changed to timescale.v This is done because of the
|
// simulation of the few cores in a one joined project.
|
// simulation of the few cores in a one joined project.
|
//
|
//
|
// Revision 1.2 2001/09/11 14:17:00 mohor
|
// Revision 1.2 2001/09/11 14:17:00 mohor
|
// Few little NCSIM warnings fixed.
|
// Few little NCSIM warnings fixed.
|
//
|
//
|
// Revision 1.1 2001/08/06 14:44:29 mohor
|
// Revision 1.1 2001/08/06 14:44:29 mohor
|
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
|
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
|
// Include files fixed to contain no path.
|
// Include files fixed to contain no path.
|
// File names and module names changed ta have a eth_ prologue in the name.
|
// File names and module names changed ta have a eth_ prologue in the name.
|
// File eth_timescale.v is used to define timescale
|
// File eth_timescale.v is used to define timescale
|
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
|
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
|
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
|
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
|
// and Mdo_OE. The bidirectional signal must be created on the top level. This
|
// and Mdo_OE. The bidirectional signal must be created on the top level. This
|
// is done due to the ASIC tools.
|
// is done due to the ASIC tools.
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//
|
//
|
// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
|
// Directory structure changed. Files checked and joind together.
|
// Directory structure changed. Files checked and joind together.
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
//
|
|
|
`include "timescale.v"
|
`include "timescale.v"
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|
|
|
|
module eth_macstatus(
|
module eth_macstatus(
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MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
|
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
|
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
|
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
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RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,
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RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,
|
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
|
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
|
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
|
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
|
LoadRxStatus
|
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
|
|
RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,
|
|
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData
|
);
|
);
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|
|
|
|
|
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parameter Tp = 1;
|
parameter Tp = 1;
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|
|
|
|
input MRxClk;
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input MRxClk;
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input Reset;
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input Reset;
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input RxCrcError;
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input RxCrcError;
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input MRxErr;
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input MRxErr;
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input MRxDV;
|
input MRxDV;
|
|
|
input RxStateSFD;
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input RxStateSFD;
|
input [1:0] RxStateData;
|
input [1:0] RxStateData;
|
input RxStatePreamble;
|
input RxStatePreamble;
|
input RxStateIdle;
|
input RxStateIdle;
|
input Transmitting;
|
input Transmitting;
|
input [15:0] RxByteCnt;
|
input [15:0] RxByteCnt;
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input RxByteCntEq0;
|
input RxByteCntEq0;
|
input RxByteCntGreat2;
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input RxByteCntGreat2;
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input RxByteCntMaxFrame;
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input RxByteCntMaxFrame;
|
input ReceivedPauseFrm;
|
input ReceivedPauseFrm;
|
input [3:0] MRxD;
|
input [3:0] MRxD;
|
input Collision;
|
input Collision;
|
input [5:0] CollValid;
|
input [5:0] CollValid;
|
input r_RecSmall;
|
input r_RecSmall;
|
input [15:0] r_MinFL;
|
input [15:0] r_MinFL;
|
input [15:0] r_MaxFL;
|
input [15:0] r_MaxFL;
|
input r_HugEn;
|
input r_HugEn;
|
|
input StartTxDone;
|
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input StartTxAbort;
|
|
input [3:0] RetryCnt;
|
|
input MTxClk;
|
|
input MaxCollisionOccured;
|
|
input LateCollision;
|
|
input StartDefer;
|
|
input TxStartFrm;
|
|
input StatePreamble;
|
|
input [1:0] StateData;
|
|
input CarrierSense;
|
|
input TxUsedData;
|
|
|
|
|
output ReceivedLengthOK;
|
output ReceivedLengthOK;
|
output ReceiveEnd;
|
output ReceiveEnd;
|
output ReceivedPacketGood;
|
output ReceivedPacketGood;
|
output InvalidSymbol;
|
output InvalidSymbol;
|
output LatchedCrcError;
|
output LatchedCrcError;
|
output RxLateCollision;
|
output RxLateCollision;
|
output ShortFrame;
|
output ShortFrame;
|
output DribbleNibble;
|
output DribbleNibble;
|
output ReceivedPacketTooBig;
|
output ReceivedPacketTooBig;
|
output LoadRxStatus;
|
output LoadRxStatus;
|
|
output [3:0] RetryCntLatched;
|
|
output RetryLimit;
|
|
output LateCollLatched;
|
|
output DeferLatched;
|
|
output CarrierSenseLost;
|
|
|
|
|
reg ReceiveEnd;
|
reg ReceiveEnd;
|
|
|
reg LatchedCrcError;
|
reg LatchedCrcError;
|
reg LatchedMRxErr;
|
reg LatchedMRxErr;
|
reg LoadRxStatus;
|
reg LoadRxStatus;
|
reg InvalidSymbol;
|
reg InvalidSymbol;
|
|
reg [3:0] RetryCntLatched;
|
|
reg RetryLimit;
|
|
reg LateCollLatched;
|
|
reg DeferLatched;
|
|
reg CarrierSenseLost;
|
|
|
wire TakeSample;
|
wire TakeSample;
|
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
|
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
|
|
|
// Crc error
|
// Crc error
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedCrcError <=#Tp 1'b0;
|
LatchedCrcError <=#Tp 1'b0;
|
else
|
else
|
if(RxStateSFD)
|
if(RxStateSFD)
|
LatchedCrcError <=#Tp 1'b0;
|
LatchedCrcError <=#Tp 1'b0;
|
else
|
else
|
if(RxStateData[0])
|
if(RxStateData[0])
|
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
|
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
|
end
|
end
|
|
|
|
|
// LatchedMRxErr
|
// LatchedMRxErr
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LatchedMRxErr <=#Tp 1'b0;
|
LatchedMRxErr <=#Tp 1'b0;
|
else
|
else
|
if(~MRxErr & MRxDV & RxStateIdle & ~Transmitting)
|
if(~MRxErr & MRxDV & RxStateIdle & ~Transmitting)
|
LatchedMRxErr <=#Tp 1'b0;
|
LatchedMRxErr <=#Tp 1'b0;
|
else
|
else
|
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
|
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
|
LatchedMRxErr <=#Tp 1'b1;
|
LatchedMRxErr <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// ReceivedPacketGood
|
// ReceivedPacketGood
|
assign ReceivedPacketGood = ~LatchedCrcError & ~LatchedMRxErr;
|
assign ReceivedPacketGood = ~LatchedCrcError & ~LatchedMRxErr;
|
|
|
|
|
// ReceivedLengthOK
|
// ReceivedLengthOK
|
assign ReceivedLengthOK = RxByteCnt[15:0] > 63 & RxByteCnt[15:0] < 1519;
|
assign ReceivedLengthOK = RxByteCnt[15:0] > 63 & RxByteCnt[15:0] < 1519;
|
|
|
|
|
|
|
|
|
|
|
// Time to take a sample
|
// Time to take a sample
|
assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
|
assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
|
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
|
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
|
|
|
|
|
// LoadRxStatus
|
// LoadRxStatus
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
LoadRxStatus <=#Tp 1'b0;
|
LoadRxStatus <=#Tp 1'b0;
|
else
|
else
|
LoadRxStatus <=#Tp TakeSample;
|
LoadRxStatus <=#Tp TakeSample;
|
end
|
end
|
|
|
|
|
|
|
// ReceiveEnd
|
// ReceiveEnd
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReceiveEnd <=#Tp 1'b0;
|
ReceiveEnd <=#Tp 1'b0;
|
else
|
else
|
ReceiveEnd <=#Tp LoadRxStatus;
|
ReceiveEnd <=#Tp LoadRxStatus;
|
end
|
end
|
|
|
|
|
// Invalid Symbol received during 100Mbps mode
|
// Invalid Symbol received during 100Mbps mode
|
assign SetInvalidSymbol = MRxDV & MRxErr & ~LatchedMRxErr & MRxD[3:0] == 4'he;
|
assign SetInvalidSymbol = MRxDV & MRxErr & ~LatchedMRxErr & MRxD[3:0] == 4'he;
|
|
|
|
|
// InvalidSymbol
|
// InvalidSymbol
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
InvalidSymbol <=#Tp 1'b0;
|
InvalidSymbol <=#Tp 1'b0;
|
else
|
else
|
if(LoadRxStatus & ~SetInvalidSymbol)
|
if(LoadRxStatus & ~SetInvalidSymbol)
|
InvalidSymbol <=#Tp 1'b0;
|
InvalidSymbol <=#Tp 1'b0;
|
else
|
else
|
if(SetInvalidSymbol)
|
if(SetInvalidSymbol)
|
InvalidSymbol <=#Tp 1'b1;
|
InvalidSymbol <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// Late Collision
|
// Late Collision
|
|
|
reg RxLateCollision;
|
reg RxLateCollision;
|
reg RxColWindow;
|
reg RxColWindow;
|
// Collision Window
|
// Collision Window
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxLateCollision <=#Tp 1'b0;
|
RxLateCollision <=#Tp 1'b0;
|
else
|
else
|
if(LoadRxStatus)
|
if(LoadRxStatus)
|
RxLateCollision <=#Tp 1'b0;
|
RxLateCollision <=#Tp 1'b0;
|
else
|
else
|
if(Collision & (~RxColWindow | r_RecSmall))
|
if(Collision & (~RxColWindow | r_RecSmall))
|
RxLateCollision <=#Tp 1'b1;
|
RxLateCollision <=#Tp 1'b1;
|
end
|
end
|
|
|
// Collision Window
|
// Collision Window
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
RxColWindow <=#Tp 1'b1;
|
RxColWindow <=#Tp 1'b1;
|
else
|
else
|
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
|
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
|
RxColWindow <=#Tp 1'b0;
|
RxColWindow <=#Tp 1'b0;
|
else
|
else
|
if(RxStateIdle)
|
if(RxStateIdle)
|
RxColWindow <=#Tp 1'b1;
|
RxColWindow <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
// ShortFrame
|
// ShortFrame
|
reg ShortFrame;
|
reg ShortFrame;
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ShortFrame <=#Tp 1'b0;
|
ShortFrame <=#Tp 1'b0;
|
else
|
else
|
if(LoadRxStatus)
|
if(LoadRxStatus)
|
ShortFrame <=#Tp 1'b0;
|
ShortFrame <=#Tp 1'b0;
|
else
|
else
|
if(TakeSample)
|
if(TakeSample)
|
ShortFrame <=#Tp r_RecSmall & RxByteCnt[15:0] < r_MinFL[15:0];
|
ShortFrame <=#Tp r_RecSmall & RxByteCnt[15:0] < r_MinFL[15:0];
|
end
|
end
|
|
|
|
|
// DribbleNibble
|
// DribbleNibble
|
reg DribbleNibble;
|
reg DribbleNibble;
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
DribbleNibble <=#Tp 1'b0;
|
DribbleNibble <=#Tp 1'b0;
|
else
|
else
|
if(RxStateSFD)
|
if(RxStateSFD)
|
DribbleNibble <=#Tp 1'b0;
|
DribbleNibble <=#Tp 1'b0;
|
else
|
else
|
if(~MRxDV & RxStateData[1])
|
if(~MRxDV & RxStateData[1])
|
DribbleNibble <=#Tp 1'b1;
|
DribbleNibble <=#Tp 1'b1;
|
end
|
end
|
|
|
|
|
reg ReceivedPacketTooBig;
|
reg ReceivedPacketTooBig;
|
assign ReceivedLengthOK = RxByteCnt[15:0] > 63 & RxByteCnt[15:0] < 1519;
|
assign ReceivedLengthOK = RxByteCnt[15:0] > 63 & RxByteCnt[15:0] < 1519;
|
always @ (posedge MRxClk or posedge Reset)
|
always @ (posedge MRxClk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
ReceivedPacketTooBig <=#Tp 1'b0;
|
ReceivedPacketTooBig <=#Tp 1'b0;
|
else
|
else
|
if(LoadRxStatus)
|
if(LoadRxStatus)
|
ReceivedPacketTooBig <=#Tp 1'b0;
|
ReceivedPacketTooBig <=#Tp 1'b0;
|
else
|
else
|
if(TakeSample)
|
if(TakeSample)
|
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
|
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
|
end
|
end
|
|
|
|
|
|
|
|
// Latched Retry counter for tx status
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RetryCntLatched <=#Tp 4'h0;
|
|
else
|
|
if(StartTxDone | StartTxAbort)
|
|
RetryCntLatched <=#Tp RetryCnt;
|
|
end
|
|
|
|
|
|
// Latched Retransmission limit
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
RetryLimit <=#Tp 4'h0;
|
|
else
|
|
if(StartTxDone | StartTxAbort)
|
|
RetryLimit <=#Tp MaxCollisionOccured;
|
|
end
|
|
|
|
|
|
// Latched Late Collision
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
LateCollLatched <=#Tp 1'b0;
|
|
else
|
|
if(StartTxDone | StartTxAbort)
|
|
LateCollLatched <=#Tp LateCollision;
|
|
end
|
|
|
|
|
|
|
|
// Latched Defer state
|
|
always @ (posedge MTxClk or posedge Reset)
|
|
begin
|
|
if(Reset)
|
|
DeferLatched <=#Tp 1'b0;
|
|
else
|
|
if(StartDefer & TxUsedData)
|
|
DeferLatched <=#Tp 1'b1;
|
|
else
|
|
if(TxStartFrm)
|
|
DeferLatched <=#Tp 1'b0;
|
|
end
|
|
|
|
|
|
// CarrierSenseLost
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always @ (posedge MTxClk or posedge Reset)
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begin
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if(Reset)
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CarrierSenseLost <=#Tp 1'b0;
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else
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if((StatePreamble | (|StateData)) & ~CarrierSense)
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CarrierSenseLost <=#Tp 1'b1;
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else
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if(TxStartFrm)
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CarrierSenseLost <=#Tp 1'b0;
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end
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|
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endmodule
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endmodule
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