//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// eth_registers.v ////
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//// eth_registers.v ////
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//// ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// http://www.opencores.org/projects/ethmac/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// - Igor Mohor (igorM@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/02/14 20:19:41 billditt
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// Modified for Address Checking,
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// addition of eth_addrcheck.v
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//
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// Revision 1.8 2002/02/12 17:01:19 mohor
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// HASH0 and HASH1 registers added.
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// Revision 1.7 2002/01/23 10:28:16 mohor
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// Revision 1.7 2002/01/23 10:28:16 mohor
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// Link in the header changed.
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// Link in the header changed.
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//
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//
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// Revision 1.6 2001/12/05 15:00:16 mohor
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// Revision 1.6 2001/12/05 15:00:16 mohor
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
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// instead of the number of RX descriptors).
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// instead of the number of RX descriptors).
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//
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//
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// Revision 1.5 2001/12/05 10:22:19 mohor
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// Revision 1.5 2001/12/05 10:22:19 mohor
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// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
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// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
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//
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//
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// Revision 1.4 2001/10/19 08:43:51 mohor
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// Revision 1.4 2001/10/19 08:43:51 mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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// simulation of the few cores in a one joined project.
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//
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//
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Revision 1.3 2001/10/18 12:07:11 mohor
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// Status signals changed, Adress decoding changed, interrupt controller
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// Status signals changed, Adress decoding changed, interrupt controller
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// added.
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// added.
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//
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//
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Revision 1.2 2001/09/24 15:02:56 mohor
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// Defines changed (All precede with ETH_). Small changes because some
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// Defines changed (All precede with ETH_). Small changes because some
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// tools generate warnings when two operands are together. Synchronization
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// tools generate warnings when two operands are together. Synchronization
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
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// demands).
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// demands).
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//
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//
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// Revision 1.1 2001/08/06 14:44:29 mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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// is done due to the ASIC tools.
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//
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//
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Revision 1.2 2001/08/02 09:25:31 mohor
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// Unconnected signals are now connected.
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// Unconnected signals are now connected.
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//
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//
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Revision 1.1 2001/07/30 21:23:42 mohor
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// Directory structure changed. Files checked and joind together.
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// Directory structure changed. Files checked and joind together.
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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//
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`include "eth_defines.v"
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`include "eth_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, r_DmaEn,
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module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, r_DmaEn,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
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r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
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TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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LinkFail, r_MAC, WCtrlDataStart, RStatStart,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
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UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
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r_HASH0, r_HASH1
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r_HASH0, r_HASH1
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);
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);
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parameter Tp = 1;
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parameter Tp = 1;
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input [31:0] DataIn;
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input [31:0] DataIn;
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input [7:0] Address;
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input [7:0] Address;
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input Rw;
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input Rw;
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input Cs;
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input Cs;
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input Clk;
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input Clk;
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input Reset;
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input Reset;
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input WCtrlDataStart;
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input WCtrlDataStart;
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input RStatStart;
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input RStatStart;
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input UpdateMIIRX_DATAReg;
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input UpdateMIIRX_DATAReg;
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input [15:0] Prsd;
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input [15:0] Prsd;
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output [31:0] DataOut;
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output [31:0] DataOut;
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reg [31:0] DataOut;
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reg [31:0] DataOut;
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output r_DmaEn;
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output r_DmaEn;
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output r_RecSmall;
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output r_RecSmall;
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output r_Pad;
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output r_Pad;
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output r_HugEn;
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output r_HugEn;
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output r_CrcEn;
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output r_CrcEn;
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output r_DlyCrcEn;
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output r_DlyCrcEn;
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output r_Rst;
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output r_Rst;
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output r_FullD;
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output r_FullD;
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output r_ExDfrEn;
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output r_ExDfrEn;
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output r_NoBckof;
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output r_NoBckof;
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output r_LoopBck;
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output r_LoopBck;
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output r_IFG;
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output r_IFG;
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output r_Pro;
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output r_Pro;
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output r_Iam;
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output r_Iam;
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output r_Bro;
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output r_Bro;
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output r_NoPre;
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output r_NoPre;
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output r_TxEn;
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output r_TxEn;
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output r_RxEn;
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output r_RxEn;
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output [31:0] r_HASH0;
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output [31:0] r_HASH0;
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output [31:0] r_HASH1;
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output [31:0] r_HASH1;
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input TxB_IRQ;
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input TxB_IRQ;
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input TxE_IRQ;
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input TxE_IRQ;
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input RxB_IRQ;
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input RxB_IRQ;
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input RxF_IRQ;
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input RxF_IRQ;
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input Busy_IRQ;
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input Busy_IRQ;
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output [6:0] r_IPGT;
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output [6:0] r_IPGT;
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output [6:0] r_IPGR1;
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output [6:0] r_IPGR1;
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output [6:0] r_IPGR2;
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output [6:0] r_IPGR2;
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output [15:0] r_MinFL;
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output [15:0] r_MinFL;
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output [15:0] r_MaxFL;
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output [15:0] r_MaxFL;
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output [3:0] r_MaxRet;
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output [3:0] r_MaxRet;
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output [5:0] r_CollValid;
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output [5:0] r_CollValid;
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output r_TxFlow;
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output r_TxFlow;
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output r_RxFlow;
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output r_RxFlow;
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output r_PassAll;
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output r_PassAll;
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output r_MiiMRst;
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output r_MiiMRst;
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output r_MiiNoPre;
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output r_MiiNoPre;
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output [7:0] r_ClkDiv;
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output [7:0] r_ClkDiv;
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output r_WCtrlData;
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output r_WCtrlData;
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output r_RStat;
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output r_RStat;
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output r_ScanStat;
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output r_ScanStat;
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output [4:0] r_RGAD;
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output [4:0] r_RGAD;
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output [4:0] r_FIAD;
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output [4:0] r_FIAD;
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output [15:0]r_CtrlData;
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output [15:0]r_CtrlData;
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input NValid_stat;
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input NValid_stat;
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input Busy_stat;
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input Busy_stat;
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input LinkFail;
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input LinkFail;
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output [47:0]r_MAC;
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output [47:0]r_MAC;
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output [7:0] r_TxBDNum;
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output [7:0] r_TxBDNum;
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output TX_BD_NUM_Wr;
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output TX_BD_NUM_Wr;
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output int_o;
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output int_o;
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reg irq_txb;
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reg irq_txb;
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reg irq_txe;
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reg irq_txe;
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reg irq_rxb;
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reg irq_rxb;
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reg irq_rxf;
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reg irq_rxf;
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reg irq_busy;
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reg irq_busy;
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wire Write = Cs & Rw;
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wire Write = Cs & Rw;
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wire Read = Cs & ~Rw;
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wire Read = Cs & ~Rw;
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wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
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wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write;
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wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR ) & Write;
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wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR ) & Write;
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wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR ) & Write;
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wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR ) & Write;
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wire IPGT_Wr = (Address == `ETH_IPGT_ADR ) & Write;
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wire IPGT_Wr = (Address == `ETH_IPGT_ADR ) & Write;
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wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR ) & Write;
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wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR ) & Write;
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wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR ) & Write;
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wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR ) & Write;
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wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR ) & Write;
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wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR ) & Write;
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wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR ) & Write;
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wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR ) & Write;
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wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR ) & Write;
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wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR ) & Write;
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wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR ) & Write;
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wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR ) & Write;
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wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR ) & Write;
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wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR ) & Write;
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wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR ) & Write;
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wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR ) & Write;
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wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
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wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write;
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wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
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wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
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wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write;
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wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write;
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wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
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wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write;
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wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
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wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write;
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wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
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wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write;
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wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
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wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write;
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assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write;
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assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write;
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wire [31:0] MODEROut;
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wire [31:0] MODEROut;
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wire [31:0] INT_SOURCEOut;
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wire [31:0] INT_SOURCEOut;
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wire [31:0] INT_MASKOut;
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wire [31:0] INT_MASKOut;
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wire [31:0] IPGTOut;
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wire [31:0] IPGTOut;
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wire [31:0] IPGR1Out;
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wire [31:0] IPGR1Out;
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wire [31:0] IPGR2Out;
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wire [31:0] IPGR2Out;
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wire [31:0] PACKETLENOut;
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wire [31:0] PACKETLENOut;
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wire [31:0] COLLCONFOut;
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wire [31:0] COLLCONFOut;
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wire [31:0] CTRLMODEROut;
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wire [31:0] CTRLMODEROut;
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wire [31:0] MIIMODEROut;
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wire [31:0] MIIMODEROut;
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wire [31:0] MIICOMMANDOut;
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wire [31:0] MIICOMMANDOut;
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wire [31:0] MIIADDRESSOut;
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wire [31:0] MIIADDRESSOut;
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wire [31:0] MIITX_DATAOut;
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wire [31:0] MIITX_DATAOut;
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wire [31:0] MIIRX_DATAOut;
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wire [31:0] MIIRX_DATAOut;
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wire [31:0] MIISTATUSOut;
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wire [31:0] MIISTATUSOut;
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wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR0Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] MAC_ADDR1Out;
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wire [31:0] TX_BD_NUMOut;
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wire [31:0] TX_BD_NUMOut;
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wire [31:0] HASH0Out;
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wire [31:0] HASH0Out;
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wire [31:0] HASH1Out;
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wire [31:0] HASH1Out;
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
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eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
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eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
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eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
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eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
|
eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF));
|
eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF));
|
eth_register #(32) RXHASH0 (.DataIn(DataIn), .DataOut(HASH0Out), .Write(HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
|
eth_register #(32) RXHASH0 (.DataIn(DataIn), .DataOut(HASH0Out), .Write(HASH0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH0_DEF));
|
eth_register #(32) RXHASH1 (.DataIn(DataIn), .DataOut(HASH1Out), .Write(HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
|
eth_register #(32) RXHASH1 (.DataIn(DataIn), .DataOut(HASH1Out), .Write(HASH1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_HASH1_DEF));
|
|
|
|
|
|
|
// CTRLMODER registers
|
// CTRLMODER registers
|
wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF;
|
wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF;
|
assign CTRLMODEROut[31:3] = 29'h0;
|
assign CTRLMODEROut[31:3] = 29'h0;
|
eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0]));
|
eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0]));
|
// End: CTRLMODER registers
|
// End: CTRLMODER registers
|
|
|
|
|
|
|
|
|
|
|
eth_register #(32) MIIMODER (.DataIn(DataIn), .DataOut(MIIMODEROut), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF));
|
eth_register #(32) MIIMODER (.DataIn(DataIn), .DataOut(MIIMODEROut), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF));
|
|
|
assign MIICOMMANDOut[31:3] = 29'h0;
|
assign MIICOMMANDOut[31:3] = 29'h0;
|
eth_register #(1) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
|
eth_register #(1) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
|
eth_register #(1) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0));
|
eth_register #(1) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0));
|
eth_register #(1) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
|
eth_register #(1) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
|
|
|
eth_register #(32) MIIADDRESS (.DataIn(DataIn), .DataOut(MIIADDRESSOut), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF));
|
eth_register #(32) MIIADDRESS (.DataIn(DataIn), .DataOut(MIIADDRESSOut), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF));
|
eth_register #(32) MIITX_DATA (.DataIn(DataIn), .DataOut(MIITX_DATAOut), .Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF));
|
eth_register #(32) MIITX_DATA (.DataIn(DataIn), .DataOut(MIITX_DATAOut), .Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF));
|
eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
|
eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
|
//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIISTATUS_DEF));
|
//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIISTATUS_DEF));
|
eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
|
eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
|
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
|
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
|
|
|
assign TX_BD_NUMOut[31:8] = 24'h0;
|
assign TX_BD_NUMOut[31:8] = 24'h0;
|
eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
|
eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
|
|
|
|
|
reg LinkFailRegister;
|
reg LinkFailRegister;
|
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
|
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
|
reg ResetLinkFailRegister_q1;
|
reg ResetLinkFailRegister_q1;
|
reg ResetLinkFailRegister_q2;
|
reg ResetLinkFailRegister_q2;
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
begin
|
begin
|
LinkFailRegister <= #Tp 0;
|
LinkFailRegister <= #Tp 0;
|
ResetLinkFailRegister_q1 <= #Tp 0;
|
ResetLinkFailRegister_q1 <= #Tp 0;
|
ResetLinkFailRegister_q2 <= #Tp 0;
|
ResetLinkFailRegister_q2 <= #Tp 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
ResetLinkFailRegister_q1 <= #Tp ResetLinkFailRegister;
|
ResetLinkFailRegister_q1 <= #Tp ResetLinkFailRegister;
|
ResetLinkFailRegister_q2 <= #Tp ResetLinkFailRegister_q1;
|
ResetLinkFailRegister_q2 <= #Tp ResetLinkFailRegister_q1;
|
if(LinkFail)
|
if(LinkFail)
|
LinkFailRegister <= #Tp 1;
|
LinkFailRegister <= #Tp 1;
|
if(~ResetLinkFailRegister_q1 & ResetLinkFailRegister_q2)
|
if(~ResetLinkFailRegister_q1 & ResetLinkFailRegister_q2)
|
LinkFailRegister <= #Tp 0;
|
LinkFailRegister <= #Tp 0;
|
end
|
end
|
end
|
end
|
|
|
|
|
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
|
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
|
IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
|
IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
|
MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
|
MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
|
MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
|
MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
|
TX_BD_NUMOut or HASH0Out or HASH1Out)
|
TX_BD_NUMOut or HASH0Out or HASH1Out)
|
begin
|
begin
|
if(Read) // read
|
if(Read) // read
|
begin
|
begin
|
case(Address)
|
case(Address)
|
`ETH_MODER_ADR : DataOut<=MODEROut;
|
`ETH_MODER_ADR : DataOut<=MODEROut;
|
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
|
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
|
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
|
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
|
`ETH_IPGT_ADR : DataOut<=IPGTOut;
|
`ETH_IPGT_ADR : DataOut<=IPGTOut;
|
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
|
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
|
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
|
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
|
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
|
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
|
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
|
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
|
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
|
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
|
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
|
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
|
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
|
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
|
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
|
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
|
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
|
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
|
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
|
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
|
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
|
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
|
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
|
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
|
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
|
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
|
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
|
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
|
`ETH_HASH0_ADR : DataOut<=HASH0Out;
|
`ETH_HASH0_ADR : DataOut<=HASH0Out;
|
`ETH_HASH1_ADR : DataOut<=HASH1Out;
|
`ETH_HASH1_ADR : DataOut<=HASH1Out;
|
default: DataOut<=32'h0;
|
default: DataOut<=32'h0;
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
DataOut<=32'h0;
|
DataOut<=32'h0;
|
end
|
end
|
|
|
|
|
assign r_DmaEn = MODEROut[17];
|
assign r_DmaEn = MODEROut[17];
|
assign r_RecSmall = MODEROut[16];
|
assign r_RecSmall = MODEROut[16];
|
assign r_Pad = MODEROut[15];
|
assign r_Pad = MODEROut[15];
|
assign r_HugEn = MODEROut[14];
|
assign r_HugEn = MODEROut[14];
|
assign r_CrcEn = MODEROut[13];
|
assign r_CrcEn = MODEROut[13];
|
assign r_DlyCrcEn = MODEROut[12];
|
assign r_DlyCrcEn = MODEROut[12];
|
assign r_Rst = MODEROut[11];
|
assign r_Rst = MODEROut[11];
|
assign r_FullD = MODEROut[10];
|
assign r_FullD = MODEROut[10];
|
assign r_ExDfrEn = MODEROut[9];
|
assign r_ExDfrEn = MODEROut[9];
|
assign r_NoBckof = MODEROut[8];
|
assign r_NoBckof = MODEROut[8];
|
assign r_LoopBck = MODEROut[7];
|
assign r_LoopBck = MODEROut[7];
|
assign r_IFG = MODEROut[6];
|
assign r_IFG = MODEROut[6];
|
assign r_Pro = MODEROut[5];
|
assign r_Pro = MODEROut[5];
|
assign r_Iam = MODEROut[4];
|
assign r_Iam = MODEROut[4];
|
assign r_Bro = MODEROut[3];
|
assign r_Bro = MODEROut[3];
|
assign r_NoPre = MODEROut[2];
|
assign r_NoPre = MODEROut[2];
|
assign r_TxEn = MODEROut[1];
|
assign r_TxEn = MODEROut[1];
|
assign r_RxEn = MODEROut[0];
|
assign r_RxEn = MODEROut[0];
|
|
|
assign r_IPGT[6:0] = IPGTOut[6:0];
|
assign r_IPGT[6:0] = IPGTOut[6:0];
|
|
|
assign r_IPGR1[6:0] = IPGR1Out[6:0];
|
assign r_IPGR1[6:0] = IPGR1Out[6:0];
|
|
|
assign r_IPGR2[6:0] = IPGR2Out[6:0];
|
assign r_IPGR2[6:0] = IPGR2Out[6:0];
|
|
|
assign r_MinFL[15:0] = PACKETLENOut[31:16];
|
assign r_MinFL[15:0] = PACKETLENOut[31:16];
|
assign r_MaxFL[15:0] = PACKETLENOut[15:0];
|
assign r_MaxFL[15:0] = PACKETLENOut[15:0];
|
|
|
assign r_MaxRet[3:0] = COLLCONFOut[19:16];
|
assign r_MaxRet[3:0] = COLLCONFOut[19:16];
|
assign r_CollValid[5:0] = COLLCONFOut[5:0];
|
assign r_CollValid[5:0] = COLLCONFOut[5:0];
|
|
|
assign r_TxFlow = CTRLMODEROut[2];
|
assign r_TxFlow = CTRLMODEROut[2];
|
assign r_RxFlow = CTRLMODEROut[1];
|
assign r_RxFlow = CTRLMODEROut[1];
|
assign r_PassAll = CTRLMODEROut[0];
|
assign r_PassAll = CTRLMODEROut[0];
|
|
|
assign r_MiiMRst = MIIMODEROut[10];
|
assign r_MiiMRst = MIIMODEROut[10];
|
assign r_MiiNoPre = MIIMODEROut[8];
|
assign r_MiiNoPre = MIIMODEROut[8];
|
assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
|
assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
|
|
|
assign r_WCtrlData = MIICOMMANDOut[2];
|
assign r_WCtrlData = MIICOMMANDOut[2];
|
assign r_RStat = MIICOMMANDOut[1];
|
assign r_RStat = MIICOMMANDOut[1];
|
assign r_ScanStat = MIICOMMANDOut[0];
|
assign r_ScanStat = MIICOMMANDOut[0];
|
|
|
assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
|
assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
|
assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
|
assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
|
|
|
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
|
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
|
|
|
assign MIISTATUSOut[31:10] = 22'h0 ;
|
assign MIISTATUSOut[31:10] = 22'h0 ;
|
assign MIISTATUSOut[9] = NValid_stat ;
|
assign MIISTATUSOut[9] = NValid_stat ;
|
assign MIISTATUSOut[8] = Busy_stat ;
|
assign MIISTATUSOut[8] = Busy_stat ;
|
assign MIISTATUSOut[7:3]= 5'h0 ;
|
assign MIISTATUSOut[7:3]= 5'h0 ;
|
assign MIISTATUSOut[2] = 1'b0;
|
assign MIISTATUSOut[2] = 1'b0;
|
assign MIISTATUSOut[1] = 1'b0;
|
assign MIISTATUSOut[1] = 1'b0;
|
assign MIISTATUSOut[0] = LinkFailRegister ;
|
assign MIISTATUSOut[0] = LinkFailRegister ;
|
|
|
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
|
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
|
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
|
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
|
assign r_HASH1[31:0] = HASH1Out;
|
assign r_HASH1[31:0] = HASH1Out;
|
assign r_HASH0[31:0] = HASH0Out;
|
assign r_HASH0[31:0] = HASH0Out;
|
|
|
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
|
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
|
|
|
|
|
// Interrupt generation
|
// Interrupt generation
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_txb <= 1'b0;
|
irq_txb <= 1'b0;
|
else
|
else
|
if(TxB_IRQ & INT_MASKOut[0])
|
if(TxB_IRQ & INT_MASKOut[0])
|
irq_txb <= #Tp 1'b1;
|
irq_txb <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[0])
|
if(INT_SOURCE_Wr & DataIn[0])
|
irq_txb <= #Tp 1'b0;
|
irq_txb <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_txe <= 1'b0;
|
irq_txe <= 1'b0;
|
else
|
else
|
if(TxE_IRQ & INT_MASKOut[1])
|
if(TxE_IRQ & INT_MASKOut[1])
|
irq_txe <= #Tp 1'b1;
|
irq_txe <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[1])
|
if(INT_SOURCE_Wr & DataIn[1])
|
irq_txe <= #Tp 1'b0;
|
irq_txe <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_rxb <= 1'b0;
|
irq_rxb <= 1'b0;
|
else
|
else
|
if(RxB_IRQ & INT_MASKOut[2])
|
if(RxB_IRQ & INT_MASKOut[2])
|
irq_rxb <= #Tp 1'b1;
|
irq_rxb <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[2])
|
if(INT_SOURCE_Wr & DataIn[2])
|
irq_rxb <= #Tp 1'b0;
|
irq_rxb <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_rxf <= 1'b0;
|
irq_rxf <= 1'b0;
|
else
|
else
|
if(RxF_IRQ & INT_MASKOut[3])
|
if(RxF_IRQ & INT_MASKOut[3])
|
irq_rxf <= #Tp 1'b1;
|
irq_rxf <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[3])
|
if(INT_SOURCE_Wr & DataIn[3])
|
irq_rxf <= #Tp 1'b0;
|
irq_rxf <= #Tp 1'b0;
|
end
|
end
|
|
|
always @ (posedge Clk or posedge Reset)
|
always @ (posedge Clk or posedge Reset)
|
begin
|
begin
|
if(Reset)
|
if(Reset)
|
irq_busy <= 1'b0;
|
irq_busy <= 1'b0;
|
else
|
else
|
if(Busy_IRQ & INT_MASKOut[4])
|
if(Busy_IRQ & INT_MASKOut[4])
|
irq_busy <= #Tp 1'b1;
|
irq_busy <= #Tp 1'b1;
|
else
|
else
|
if(INT_SOURCE_Wr & DataIn[4])
|
if(INT_SOURCE_Wr & DataIn[4])
|
irq_busy <= #Tp 1'b0;
|
irq_busy <= #Tp 1'b0;
|
end
|
end
|
|
|
// Generating interrupt signal
|
// Generating interrupt signal
|
assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxf | irq_busy;
|
assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxf | irq_busy;
|
|
|
// For reading interrupt status
|
// For reading interrupt status
|
assign INT_SOURCEOut = {28'h0, irq_busy, irq_rxf, irq_rxb, irq_txe, irq_txb};
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assign INT_SOURCEOut = {28'h0, irq_busy, irq_rxf, irq_rxb, irq_txe, irq_txb};
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endmodule
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endmodule
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