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```5M5MMj!t`5``Tv=<^L250&t#Ot#d5t#`5M1t[[=ttt$5GtttGtttHHHHHH10G Ethernet MAC System Design
System description 
10-Gigabit Ethernet MAC contains features list below:
Designed to 10 Gigabit Ethernet specification IEEE 802.3ae-2002
Choice of external XGMII or internal FPGA interface to PHY layer(RocketIO)
Support flow-control in both directions
Automatically pad short frames on transmit.
MDIO STA master interface to manage PHY layers
Supports VLAN, jumbo frames, and WAN mode
Only support full duplex.
Figure 1.1 shows the system of our verify board.
 SHAPE  \* MERGEFORMAT 
Figure 1.1: 10-Gigabit Ethernet MAC Core Connected to PHY with XGMII interface
System design
10-Gigabit Ethernet MAC core include the following functions:
Interface with user logic (not determined, discuss later, use Xilinx defined interface first)
Transmitter
Receiver
Flow Control block-implement both Receive Flow Control and Transmit Flow Control
Reconciliation Sublayer (RS)-processes XGMII Local Fault and Remote Fault messages and handles DDR conversion
Management interface and MDIO
Statistics counters
XGMII interface-connection to the physical layer device or logic
Figure 1.2 shows a block diagram of the implementation of the 10-Gigabit Ethernet MAC core (Here I use the figure provided by xilinx to save time).

Figure 1.2 implement of the 10-Gigabit Ethernet MAC Core
Figure 1.3 shows the dataflow in 10-Gigabit Ethernet MAC Core. 


Figure 1.3 Dataflow of 10-Gigabit MAC
Data flow can be divided into transmit process and receive process.
Transmit process: 
a) Data Frame
Get data_from_userlogic (contains DA, SA, and DATA) from user logic.
Transmit Engine module computes PAD, adds SFD and PRE characters, and append FCS (if it is not provided by user logic), then package the data into packaged_mac_frame.
        b) Control Frame
To get pause_data (time to pause receivers transmit process) from user logic.
Flow Control module put trans_mac_control_frame (contains broadcast address, SA, L/T, and pause_data) to Transmit Engine Module.
Transmit Engine module computes PAD, adds SFD and PRE characters, and appends FCS (if it is not provided by user logic), then package the data into packaged_mac_frame.
Receive process
DATA Frame
 To get recvd_mac_frame (DA, SA, L/T, DATA and FCS) from RS module.
 To check FCS and DA fields, send data_to_logic (DA, SA, L/T, DATA and FCS) to user logic and indicate if data_to_logic is good or bad. 
Control Frame
 To get recvd_mac_frame (DA, SA, L/T, DATA and FCS) from RS module and recognize it as a MAC Control Frame. 
 Flow Control module sends corresponding pause operation to Transmit Engine.
Figure 1.4 shows the control flow of 10-Gigabit MAC Core.
            
         Figure 1.4 Control Flow of 10-Gigabit MAC Core
As shown in figure 1.4, the configure register, statistics register, MDIO and Management Interface belong to one module. User logic accesses configure registers, statistics registers and MDIO via management interface.
Sub modules
3.1 Transmit Engine (See 802.3-2002, 802.3ae-2002 Clause4)
 SHAPE  \* MERGEFORMAT 
Figure 3-1 Transmit Engine interfaces
3.1.1 Description
   Transmit Engine module has three main functions: transmitting data, transmitting control frame, and using counters to get information of transmit condition. It contains interfaces with User Logic, RS, Statistic, Configure, and Flow Control sub module.
3.1.2 Function
Data encapsulation.(see 802.3 Clause 4 and 802.3ae Clause 4)
Append SFD, PRE, Termination Character
Data encapsulation, including compute PAD
Generate CRC(optional)
Map frame into PLS signals. (see 802.3ae-2002 Clause 4, 46)
Statistics. (see Xilinx 10-Gigabit MAC User Guide)
3.1.3 Interface
With user logic
tx_data [63:0]: Frame data to be transmitted is supplied on this port.
tx_data_valid: Control signals for tx_data port. Each asserted signal on tx_data_valid signifies which bytes of tx_data are valid; i.e., if tx_data_valid [0] is 1, the signals tx_data [7:0] are valid.
tx_start: Handshaking signal. Asserted by the client to make data available for transmission.
tx_underrun: Assert this pin to forcibly corrupt the current frame.
tx_ifg_delay [7:0]: Control signal for configurable inter-frame gap adjustment.
tx_ack: Output Handshaking signal. Asserted when the first column of data on TX_DATA has been accepted.
With Flow Control
pause_frame_data [15:0]: MAC Control Frame data to be transferred.
trans_pause_valid: when it is assert, it indicates pause_frame_data is valid.
pause_tx_data [15:0]: Cycles for Transmit Engine state machine to pause.
 pause_tx_valid: when it is assert, it indicates that transmit state machine should pause for cycles indicated by pause_frame_data.
With Reconciliation Sublayer 
mac_frame [7:0]: encapsulated data (with SFD, PRE, PAD, etc), which can be 8 bit width, due to our implement. Termination Character which appears in mac_frame indicates the end of one frame. 
With Management Submodule
tx_cfg_reg_value [31:0]: The value from configuration registers.
tx_cfg_reg_valid: When it is asserted, it indicates tx_cfg_reg_value is valid.
tx_stat_reg_plus [n-1:0]: n presents the number of statistic registers. Each bit presents add operation to a statistic register. These signals should only last for one cycle. For example, when tx_stat_reg_plus [0] is asserted for one cycle, the counter of Control Frames Transmitted OK register in Management Module will plus one.
3.2. Flow control (see 802.3-2002 Clause 31, 31A, 31B)
 SHAPE  \* MERGEFORMAT 
3.2.1 Description
(Hasnt written yet)
3.2.2 Function
 Generate MAC Control Frame
Pause value comes from user logic.
Process MAC Control Frame
Identify MAC Control Frame and process it. Translate the MAC Control Frame into pause request to Transmit Engine.
3.2.3 Interface
a) With User Logic
pause_req: Request that a flow control frame is emitted from the MAC core.
pause_val [15:0]: Input Pause value field for flow control frame to be sent when pause_req asserted.
b) With Reconciliation Sublayer
mac_frame_in [7: 0]: Content of MAC Frame, which may be a MAC Control Frame. 
mac_frame_valid: When it is asserted, it indicates that data carried by mac_frame_in is valid. 
c) With Transmit Engine
pause_frame_data [15:0]: MAC Control Frame data to be transferred.
trans_pause_valid: when it is assert, it indicates pause_frame_data is valid.
pause_tx_data [15:0]: Cycles for Transmit Engine state machine to pause.
pause_tx_valid: when it is assert, it indicates that transmit state machine should pause for cycles indicated by pause_frame_data.
d) With Management Submodule
fc_cfg_reg_value [31:0]: The value from configuration registers.
 fc_cfg_reg_valid: When it is asserted, it indicates fc_cfg_reg_value is valid.
3.3 Receive Engine (see 802.3 and 802.3ae Clause 4)
 SHAPE  \* MERGEFORMAT 
3.3.1 Description
3.3.2 Function
1. Data decapsulation. (See 802.3 and 802.3ae Clause 4)
a) Address recognition
b) Frame check sequence validation
c) Frame disassembly
   2. Receive media access management
     a) Indicate ill-framed data
     b) Discard frames that are less than minFrameSize bits.
   3. Statistics (See 802.3 and 802.3ae Clause 30)
3.3.3 Interface
  a) With User Logic
rx_data [63:0]: Output Received data, eight bytes wide.
rx_data_valid [7:0]: Output Received control bits, one bit per receive lane.
rx_good_frame: Output Asserted at the end of frame to indicate the frame was successfully received and should be processed by the user logic.
rx_bad_frame: Output Asserted at the end of frame to indicate the frame was not successfully received and should be discarded by the user logic.
b) With Reconciliation Sublayer
 mac_frame_in [7: 0]: Content of MAC Frame, which may be a MAC Control Frame. 
mac_frame_valid: When it is asserted, it indicates that data carried by mac_frame_in is valid.
c) With Management Submodule
rx_cfg_reg_value [31:0]: The value from configuration registers.
rx_cfg_reg_valid: When it is asserted, it indicates rx_cfg_reg_value is valid.
rx_stat_reg_plus [m-1:0]: m presents the number of statistic registers. Each bit presents an add operation to a statistic register. These signals should only last for one cycle. For example, when rx_stat_reg_plus [0] is asserted for one cycle, the counter of Control Frames Received OK register in Management Module will plus one.
3.4 Management Submodule (see 802.3 Clause 30 and 802.3ae Clause 45, xilinx spec is more useful)
 SHAPE  \* MERGEFORMAT 
3.4.1 Description
3.4.2 Function
 1. Implement MDIO 
Access PHY registers
 2. Configure registers
   Contain configure information for Transmit Engine, Receive Engine, Flow Control, Reconciliation Sublayer and MDIO.
 3. Statistic registers
   Statistic information of transmit and receive status.
 4. Provide the interface for user logic.
 Configure MAC and read statistic data. 
3.4.3 Interface
a) With User Logic
host_clk: Input clock for management interface. Range between 10 MHz and 133 MHz.
host_opcode [1:0]: Input. Defines operation to be performed over management interface.
host_addr [9:0]: Input. Address of register to be accessed.
host_wr_data [31:0]: Input. Data to write to register.
host_rd_data [31:0]: Output. Data read from register.
host_miim_sel: Input. When asserted, the MDIO interface is accessed.
host_req: Input. Used to request a transaction on the MDIO interface or read from the statistic registers.
host_miim_rdy: Output. When asserted, the MDIO interface has completed any pending transaction and is ready for a new transaction.
With Transmit Engine
tx_cfg_reg_value [31:0]: Output. The value from configuration registers.
tx_cfg_reg_valid: Output. When it is asserted, it indicates tx_cfg_reg_value is valid.
tx_stat_reg_plus [n-1:0]: Input. n presents the number of statistic registers. Each bit presents add operation to a statistic register. These signals should only last for one cycle. For example, when tx_stat_reg_plus [0] is asserted for one cycle, the counter of Control Frames Transmitted OK register in Management Module will plus one.
With Receive Engine
rx_cfg_reg_value [31:0]: Output. The value from configuration registers.
rx_cfg_reg_valid: Output.When it is asserted, it indicates rx_cfg_reg_value is valid.
rx_stat_reg_plus [m-1:0]: Input. m presents the number of statistic registers. Each bit presents an add operation to a statistic register. These signals should only last for one cycle. For example, when rx_stat_reg_plus [0] is asserted for one cycle, the counter of Control Frames Received OK register in Management Module will plus one.
With Reconciliation Sublayer
With Flow Control
fc_cfg_reg_value [31:0]: Output. The value from configuration registers.
fc_cfg_reg_valid: Output. When it is asserted, it indicates fc_cfg_reg_value is valid.
With PHY
mdc: Output. MDIO Clock.
mdio_in: Input. MDIO Input.
mdio_out: Output. MDIO Output.
mdio_tri: Output. MDIO Tristate. 1 disconnects the output driver from the MDIO bus.
3.5 Reconciliation Sublayer (see 802.3 Clause 22 and 802.3ae Clause 46)
 SHAPE  \* MERGEFORMAT 
3.5.1 Description
3.5.2 Function
1. Implement XGMII
3.5.3 Interface
a) With PHY
txd_out [63:0]: Output. Transmit data to PHY.
txc_out [7:0]: Output. Transmit control to PHY.
rxd_out [63:0]: Input. Received data from PHY.
rxc_out [7:0]: Input. Received control from PHY.
 b) With Transmit Engine
mac_frame [7:0]: Input. Encapsulated data (with SFD, PRE, PAD, etc), which can be 8 bit width, due to our implement. Termination Character which appears in mac_frame indicates the end of one frame.
 c) With Receive Engine and Flow Control
mac_frame_in [7: 0]: Output. Content of MAC Frame, which may be a MAC Control Frame. 
mac_frame_valid: Output. When it is asserted, it indicates that data carried by mac_frame_in is valid.


get_rx_cfg_val

rx_stat_reg_plus

m

rx_cfg_reg_valid

get_tx_cfg_val

32

rx_cfg_reg_value

MDIO

32

tx_cfg_reg_value

8

fc_cfg_reg_valid

fc_cfg_reg_value

pause_frame_data

mac_frame 


Transmit Engine

tx_data

64

8

tx_data_valid

tx_start

tx_ack

tx_underrun

From Client

To RS

8 

From Flow Control

16

16

tx_ifg_delay

8


trans_pause_valid

pause_tx_valid

pause_tx_data

From Management

pause_tx_data

tx_stat_reg_plus

n

3216

16

pause_frame_data

trans_pause_valid

pause_tx_valid

mac_frame_valid

mac_frame_in

To Transmit Engine

From RS

From Client

16

pause_val

pause_req






Flow Control


tx_cfg_reg_valid

get_fc_cfg_val

mod_rx_stat_regs
(write operation)


Management
Interface


Config
Registers


To Management

get_rs_cfg_val

mod_tx_stat_regs
(write operation)

8 

mac_frame_in 

To RS

From Client


Statistics
Registers


rx_good_frame

8

rx_data_valid

64

rx_data

rx_bad_frame


Receive Engine

Reconciliation Sub layer

Flow Control
(MAC Control)


Receive Engine


Transmit Engine

Reconciliation Sub layer

8 

mac_frame_in 

mac_frame_valid

mac_frame_valid

8 

mac_frame 

DDRREG

DDRREG

8 

64

txd_out

txc_out

64

8

rxd_out

rxc_out



10-Gigabit
Ethernet PHY
(PCS)
Tlk3114sagnt




DDR
Regs




10-Gigabit Ethernet
MAC Core




User
Logic

       FPGA-Virtex4 FX20

XGMII



3567=>Fij           H                                                       
 
```5M5MMj!t`5``Tv=<^L250&t#Ot#d5t#`5M1t[[=ttt$5GtttGtttHHHHHH10G Ethernet MAC System Design
System description 
10-Gigabit Ethernet MAC contains features list below:
Designed to 10 Gigabit Ethernet specification IEEE 802.3ae-2002
Choice of external XGMII or internal FPGA interface to PHY layer(RocketIO)
Support flow-control in both directions
Automatically pad short frames on transmit.
MDIO STA master interface to manage PHY layers
Supports VLAN, jumbo frames, and WAN mode
Only support full duplex.
Figure 1.1 shows the system of our verify board.
 SHAPE  \* MERGEFORMAT 
Figure 1.1: 10-Gigabit Ethernet MAC Core Connected to PHY with XGMII interface
System design
10-Gigabit Ethernet MAC core include the following functions:
Interface with user logic (not determined, discuss later, use Xilinx defined interface first)
Transmitter
Receiver
Flow Control block-implement both Receive Flow Control and Transmit Flow Control
Reconciliation Sublayer (RS)-processes XGMII Local Fault and Remote Fault messages and handles DDR conversion
Management interface and MDIO
Statistics counters
XGMII interface-connection to the physical layer device or logic
Figure 1.2 shows a block diagram of the implementation of the 10-Gigabit Ethernet MAC core (Here I use the figure provided by xilinx to save time).

Figure 1.2 implement of the 10-Gigabit Ethernet MAC Core
Figure 1.3 shows the dataflow in 10-Gigabit Ethernet MAC Core. 


Figure 1.3 Dataflow of 10-Gigabit MAC
Data flow can be divided into transmit process and receive process.
Transmit process: 
a) Data Frame
Get data_from_userlogic (contains DA, SA, and DATA) from user logic.
Transmit Engine module computes PAD, adds SFD and PRE characters, and append FCS (if it is not provided by user logic), then package the data into packaged_mac_frame.
        b) Control Frame
To get pause_data (time to pause receivers transmit process) from user logic.
Flow Control module put trans_mac_control_frame (contains broadcast address, SA, L/T, and pause_data) to Transmit Engine Module.
Transmit Engine module computes PAD, adds SFD and PRE characters, and appends FCS (if it is not provided by user logic), then package the data into packaged_mac_frame.
Receive process
DATA Frame
 To get recvd_mac_frame (DA, SA, L/T, DATA and FCS) from RS module.
 To check FCS and DA fields, send data_to_logic (DA, SA, L/T, DATA and FCS) to user logic and indicate if data_to_logic is good or bad. 
Control Frame
 To get recvd_mac_frame (DA, SA, L/T, DATA and FCS) from RS module and recognize it as a MAC Control Frame. 
 Flow Control module sends corresponding pause operation to Transmit Engine.
Figure 1.4 shows the control flow of 10-Gigabit MAC Core.
            
         Figure 1.4 Control Flow of 10-Gigabit MAC Core
As shown in figure 1.4, the configure register, statistics register, MDIO and Management Interface belong to one module. User logic accesses configure registers, statistics registers and MDIO via management interface.
Sub modules
3.1 Transmit Engine (See 802.3-2002, 802.3ae-2002 Clause4)
 SHAPE  \* MERGEFORMAT 
Figure 3-1 Transmit Engine interfaces
3.1.1 Description
   Transmit Engine module has three main functions: transmitting data, transmitting control frame, and using counters to get information of transmit condition. It contains interfaces with User Logic, RS, Statistic, Configure, and Flow Control sub module.
3.1.2 Function
Data encapsulation.(see 802.3 Clause 4 and 802.3ae Clause 4)
Append SFD, PRE, Termination Character
Data encapsulation, including compute PAD
Generate CRC(optional)
Map frame into PLS signals. (see 802.3ae-2002 Clause 4, 46)
Statistics. (see Xilinx 10-Gigabit MAC User Guide)
3.1.3 Interface
With user logic
tx_data [63:0]: Frame data to be transmitted is supplied on this port.
tx_data_valid: Control signals for tx_data port. Each asserted signal on tx_data_valid signifies which bytes of tx_data are valid; i.e., if tx_data_valid [0] is 1, the signals tx_data [7:0] are valid.
tx_start: Handshaking signal. Asserted by the client to make data available for transmission.
tx_underrun: Assert this pin to forcibly corrupt the current frame.
tx_ifg_delay [7:0]: Control signal for configurable inter-frame gap adjustment.
tx_ack: Output Handshaking signal. Asserted when the first column of data on TX_DATA has been accepted.
With Flow Control
pause_frame_data [15:0]: MAC Control Frame data to be transferred.
trans_pause_valid: when it is assert, it indicates pause_frame_data is valid.
pause_tx_data [15:0]: Cycles for Transmit Engine state machine to pause.
 pause_tx_valid: when it is assert, it indicates that transmit state machine should pause for cycles indicated by pause_frame_data.
With Reconciliation Sublayer 
mac_frame [7:0]: encapsulated data (with SFD, PRE, PAD, etc), which can be 8 bit width, due to our implement. Termination Character which appears in mac_frame indicates the end of one frame. 
With Management Submodule
tx_cfg_reg_value [31:0]: The value from configuration registers.
tx_cfg_reg_valid: When it is asserted, it indicates tx_cfg_reg_value is valid.
tx_stat_reg_plus [n-1:0]: n presents the number of statistic registers. Each bit presents add operation to a statistic register. These signals should only last for one cycle. For example, when tx_stat_reg_plus [0] is asserted for one cycle, the counter of Control Frames Transmitted OK register in Management Module will plus one.
3.2. Flow control (see 802.3-2002 Clause 31, 31A, 31B)
 SHAPE  \* MERGEFORMAT 
3.2.1 Description
(Hasnt written yet)
3.2.2 Function
 Generate MAC Control Frame
Pause value comes from user logic.
Process MAC Control Frame
Identify MAC Control Frame and process it. Translate the MAC Control Frame into pause request to Transmit Engine.
3.2.3 Interface
a) With User Logic
pause_req: Request that a flow control frame is emitted from the MAC core.
pause_val [15:0]: Input Pause value field for flow control frame to be sent when pause_req asserted.
b) With Reconciliation Sublayer
mac_frame_in [7: 0]: Content of MAC Frame, which may be a MAC Control Frame. 
mac_frame_valid: When it is asserted, it indicates that data carried by mac_frame_in is valid. 
c) With Transmit Engine
pause_frame_data [15:0]: MAC Control Frame data to be transferred.
trans_pause_valid: when it is assert, it indicates pause_frame_data is valid.
pause_tx_data [15:0]: Cycles for Transmit Engine state machine to pause.
pause_tx_valid: when it is assert, it indicates that transmit state machine should pause for cycles indicated by pause_frame_data.
d) With Management Submodule
fc_cfg_reg_value [31:0]: The value from configuration registers.
 fc_cfg_reg_valid: When it is asserted, it indicates fc_cfg_reg_value is valid.
3.3 Receive Engine (see 802.3 and 802.3ae Clause 4)
 SHAPE  \* MERGEFORMAT 
3.3.1 Description
3.3.2 Function
1. Data decapsulation. (See 802.3 and 802.3ae Clause 4)
a) Address recognition
b) Frame check sequence validation
c) Frame disassembly
   2. Receive media access management
     a) Indicate ill-framed data
     b) Discard frames that are less than minFrameSize bits.
   3. Statistics (See 802.3 and 802.3ae Clause 30)
3.3.3 Interface
  a) With User Logic
rx_data [63:0]: Output Received data, eight bytes wide.
rx_data_valid [7:0]: Output Received control bits, one bit per receive lane.
rx_good_frame: Output Asserted at the end of frame to indicate the frame was successfully received and should be processed by the user logic.
rx_bad_frame: Output Asserted at the end of frame to indicate the frame was not successfully received and should be discarded by the user logic.
b) With Reconciliation Sublayer
 mac_frame_in [7: 0]: Content of MAC Frame, which may be a MAC Control Frame. 
mac_frame_valid: When it is asserted, it indicates that data carried by mac_frame_in is valid.
c) With Management Submodule
rx_cfg_reg_value [31:0]: The value from configuration registers.
rx_cfg_reg_valid: When it is asserted, it indicates rx_cfg_reg_value is valid.
rx_stat_reg_plus [m-1:0]: m presents the number of statistic registers. Each bit presents an add operation to a statistic register. These signals should only last for one cycle. For example, when rx_stat_reg_plus [0] is asserted for one cycle, the counter of Control Frames Received OK register in Management Module will plus one.
3.4 Management Submodule (see 802.3 Clause 30 and 802.3ae Clause 45, xilinx spec is more useful)
 SHAPE  \* MERGEFORMAT 
3.4.1 Description
3.4.2 Function
 1. Implement MDIO 
Access PHY registers
 2. Configure registers
   Contain configure information for Transmit Engine, Receive Engine, Flow Control, Reconciliation Sublayer and MDIO.
 3. Statistic registers
   Statistic information of transmit and receive status.
 4. Provide the interface for user logic.
 Configure MAC and read statistic data. 
3.4.3 Interface
a) With User Logic
host_clk: Input clock for management interface. Range between 10 MHz and 133 MHz.
host_opcode [1:0]: Input. Defines operation to be performed over management interface.
host_addr [9:0]: Input. Address of register to be accessed.
host_wr_data [31:0]: Input. Data to write to register.
host_rd_data [31:0]: Output. Data read from register.
host_miim_sel: Input. When asserted, the MDIO interface is accessed.
host_req: Input. Used to request a transaction on the MDIO interface or read from the statistic registers.
host_miim_rdy: Output. When asserted, the MDIO interface has completed any pending transaction and is ready for a new transaction.
With Transmit Engine
tx_cfg_reg_value [31:0]: Output. The value from configuration registers.
tx_cfg_reg_valid: Output. When it is asserted, it indicates tx_cfg_reg_value is valid.
tx_stat_reg_plus [n-1:0]: Input. n presents the number of statistic registers. Each bit presents add operation to a statistic register. These signals should only last for one cycle. For example, when tx_stat_reg_plus [0] is asserted for one cycle, the counter of Control Frames Transmitted OK register in Management Module will plus one.
With Receive Engine
rx_cfg_reg_value [31:0]: Output. The value from configuration registers.
rx_cfg_reg_valid: Output.When it is asserted, it indicates rx_cfg_reg_value is valid.
rx_stat_reg_plus [m-1:0]: Input. m presents the number of statistic registers. Each bit presents an add operation to a statistic register. These signals should only last for one cycle. For example, when rx_stat_reg_plus [0] is asserted for one cycle, the counter of Control Frames Received OK register in Management Module will plus one.
With Reconciliation Sublayer
With Flow Control
fc_cfg_reg_value [31:0]: Output. The value from configuration registers.
fc_cfg_reg_valid: Output. When it is asserted, it indicates fc_cfg_reg_value is valid.
With PHY
mdc: Output. MDIO Clock.
mdio_in: Input. MDIO Input.
mdio_out: Output. MDIO Output.
mdio_tri: Output. MDIO Tristate. 1 disconnects the output driver from the MDIO bus.
3.5 Reconciliation Sublayer (see 802.3 Clause 22 and 802.3ae Clause 46)
 SHAPE  \* MERGEFORMAT 
3.5.1 Description
3.5.2 Function
1. Implement XGMII
3.5.3 Interface
a) With PHY
txd_out [63:0]: Output. Transmit data to PHY.
txc_out [7:0]: Output. Transmit control to PHY.
rxd_out [63:0]: Input. Received data from PHY.
rxc_out [7:0]: Input. Received control from PHY.
 b) With Transmit Engine
mac_frame [7:0]: Input. Encapsulated data (with SFD, PRE, PAD, etc), which can be 8 bit width, due to our implement. Termination Character which appears in mac_frame indicates the end of one frame.
 c) With Receive Engine and Flow Control
mac_frame_in [7: 0]: Output. Content of MAC Frame, which may be a MAC Control Frame. 
mac_frame_valid: Output. When it is asserted, it indicates that data carried by mac_frame_in is valid.


get_rx_cfg_val

rx_stat_reg_plus

m

rx_cfg_reg_valid

get_tx_cfg_val

32

rx_cfg_reg_value

MDIO

32

tx_cfg_reg_value

8

fc_cfg_reg_valid

fc_cfg_reg_value

pause_frame_data

mac_frame 


Transmit Engine

tx_data

64

8

tx_data_valid

tx_start

tx_ack

tx_underrun

From Client

To RS

8 

From Flow Control

16

16

tx_ifg_delay

8


trans_pause_valid

pause_tx_valid

pause_tx_data

From Management

pause_tx_data

tx_stat_reg_plus

n

3216

16

pause_frame_data

trans_pause_valid

pause_tx_valid

mac_frame_valid

mac_frame_in

To Transmit Engine

From RS

From Client

16

pause_val

pause_req






Flow Control


tx_cfg_reg_valid

get_fc_cfg_val

mod_rx_stat_regs
(write operation)


Management
Interface


Config
Registers


To Management

get_rs_cfg_val

mod_tx_stat_regs
(write operation)

8 

mac_frame_in 

To RS

From Client


Statistics
Registers


rx_good_frame

8

rx_data_valid

64

rx_data

rx_bad_frame


Receive Engine

Reconciliation Sub layer

Flow Control
(MAC Control)


Receive Engine


Transmit Engine

Reconciliation Sub layer

8 

mac_frame_in 

mac_frame_valid

mac_frame_valid

8 

mac_frame 

DDRREG

DDRREG

8 

64

txd_out

txc_out

64

8

rxd_out

rxc_out



10-Gigabit
Ethernet PHY
(PCS)
Tlk3114sagnt




DDR
Regs




10-Gigabit Ethernet
MAC Core




User
Logic

       FPGA-Virtex4 FX20

XGMII



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