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https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk
[/] [ethmac10g/] [tags/] [V10/] [counter.v] - Diff between revs 40 and 72
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| Rev 40 |
Rev 72 |
`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 15:53:19 11/22/05
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// Create Date: 15:53:19 11/22/05
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// Design Name:
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// Design Name:
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// Module Name: counter
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// Module Name: counter
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// Project Name:
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// Project Name:
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// Target Device:
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// Target Device:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module counter(clk, reset, load, en, value);
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module counter(clk, reset, load, en, value);
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input clk;
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input clk;
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input reset;
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input reset;
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input load;
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input load;
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input en;
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input en;
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parameter WIDTH = 8;
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parameter WIDTH = 8;
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output[WIDTH-1:0] value;
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output[WIDTH-1:0] value;
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reg [WIDTH-1:0] value;
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reg [WIDTH-1:0] value;
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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value <= 0;
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value <= 0;
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else begin
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else begin
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if (load)
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if (load)
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value <= 0;
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value <= 0;
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else if (en)
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else if (en)
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value <= value + 1;
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value <= value + 1;
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end
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end
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endmodule
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endmodule
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