////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
// Copyright (c) 1995-2003 Xilinx, Inc.
|
// Copyright (c) 1995-2003 Xilinx, Inc.
|
// All Right Reserved.
|
// All Right Reserved.
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
// ____ ____
|
// ____ ____
|
// / /\/ /
|
// / /\/ /
|
// /___/ \ / Vendor: Xilinx
|
// /___/ \ / Vendor: Xilinx
|
// \ \ \/ Version : 7.1i
|
// \ \ \/ Version : 7.1i
|
// \ \ Application :
|
// \ \ Application :
|
// / / Filename : dcm0.v
|
// / / Filename : dcm0.v
|
// /___/ /\ Timestamp : 12/22/2005 09:25:19
|
// /___/ /\ Timestamp : 12/22/2005 09:25:19
|
// \ \ / \
|
// \ \ / \
|
// \___\/\___\
|
// \___\/\___\
|
//
|
//
|
//Command:
|
//Command:
|
//Design Name: dcm0
|
//Design Name: dcm0
|
//
|
//
|
// Module dcm0
|
// Module dcm0
|
// Generated by Xilinx Architecture Wizard
|
// Generated by Xilinx Architecture Wizard
|
// Written for synthesis tool: XST
|
// Written for synthesis tool: XST
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
|
|
module dcm0(CLKIN_IN,
|
module dcm0(CLKIN_IN,
|
RST_IN,
|
RST_IN,
|
CLKIN_IBUFG_OUT,
|
CLKIN_IBUFG_OUT,
|
CLK0_OUT,
|
CLK0_OUT,
|
CLK2X_OUT,
|
CLK2X_OUT,
|
CLK180_OUT,
|
CLK180_OUT,
|
LOCKED_OUT);
|
LOCKED_OUT);
|
|
|
input CLKIN_IN;
|
input CLKIN_IN;
|
input RST_IN;
|
input RST_IN;
|
output CLKIN_IBUFG_OUT;
|
output CLKIN_IBUFG_OUT;
|
output CLK0_OUT;
|
output CLK0_OUT;
|
output CLK2X_OUT;
|
output CLK2X_OUT;
|
output CLK180_OUT;
|
output CLK180_OUT;
|
output LOCKED_OUT;
|
output LOCKED_OUT;
|
|
|
wire CLKFB_IN;
|
wire CLKFB_IN;
|
wire CLKIN_IBUFG;
|
wire CLKIN_IBUFG;
|
wire CLK0_BUF;
|
wire CLK0_BUF;
|
wire CLK2X_BUF;
|
wire CLK2X_BUF;
|
wire CLK180_BUF;
|
wire CLK180_BUF;
|
wire GND;
|
wire GND;
|
|
|
assign GND = 0;
|
assign GND = 0;
|
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
|
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
|
assign CLK0_OUT = CLKFB_IN;
|
assign CLK0_OUT = CLKFB_IN;
|
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
|
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
|
.O(CLKIN_IBUFG));
|
.O(CLKIN_IBUFG));
|
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
|
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
|
.O(CLKFB_IN));
|
.O(CLKFB_IN));
|
BUFG CLK2X_BUFG_INST (.I(CLK2X_BUF),
|
BUFG CLK2X_BUFG_INST (.I(CLK2X_BUF),
|
.O(CLK2X_OUT));
|
.O(CLK2X_OUT));
|
BUFG CLK180_BUFG_INST (.I(CLK180_BUF),
|
BUFG CLK180_BUFG_INST (.I(CLK180_BUF),
|
.O(CLK180_OUT));
|
.O(CLK180_OUT));
|
DCM DCM_INST (.CLKFB(CLKFB_IN),
|
DCM DCM_INST (.CLKFB(CLKFB_IN),
|
.CLKIN(CLKIN_IBUFG),
|
.CLKIN(CLKIN_IBUFG),
|
.DSSEN(GND),
|
.DSSEN(GND),
|
.PSCLK(GND),
|
.PSCLK(GND),
|
.PSEN(GND),
|
.PSEN(GND),
|
.PSINCDEC(GND),
|
.PSINCDEC(GND),
|
.RST(RST_IN),
|
.RST(RST_IN),
|
.CLKDV(),
|
.CLKDV(),
|
.CLKFX(),
|
.CLKFX(),
|
.CLKFX180(),
|
.CLKFX180(),
|
.CLK0(CLK0_BUF),
|
.CLK0(CLK0_BUF),
|
.CLK2X(CLK2X_BUF),
|
.CLK2X(CLK2X_BUF),
|
.CLK2X180(),
|
.CLK2X180(),
|
.CLK90(),
|
.CLK90(),
|
.CLK180(CLK180_BUF),
|
.CLK180(CLK180_BUF),
|
.CLK270(),
|
.CLK270(),
|
.LOCKED(LOCKED_OUT),
|
.LOCKED(LOCKED_OUT),
|
.PSDONE(),
|
.PSDONE(),
|
.STATUS());
|
.STATUS());
|
// synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
|
// synthesis attribute CLK_FEEDBACK of DCM_INST is "1X"
|
// synthesis attribute CLKDV_DIVIDE of DCM_INST is "2.000000"
|
// synthesis attribute CLKDV_DIVIDE of DCM_INST is "2.000000"
|
// synthesis attribute CLKFX_DIVIDE of DCM_INST is "1"
|
// synthesis attribute CLKFX_DIVIDE of DCM_INST is "1"
|
// synthesis attribute CLKFX_MULTIPLY of DCM_INST is "4"
|
// synthesis attribute CLKFX_MULTIPLY of DCM_INST is "4"
|
// synthesis attribute CLKIN_DIVIDE_BY_2 of DCM_INST is "FALSE"
|
// synthesis attribute CLKIN_DIVIDE_BY_2 of DCM_INST is "FALSE"
|
// synthesis attribute CLKIN_PERIOD of DCM_INST is "6.400000"
|
// synthesis attribute CLKIN_PERIOD of DCM_INST is "6.400000"
|
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
|
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM_INST is "NONE"
|
// synthesis attribute DESKEW_ADJUST of DCM_INST is "SYSTEM_SYNCHRONOUS"
|
// synthesis attribute DESKEW_ADJUST of DCM_INST is "SYSTEM_SYNCHRONOUS"
|
// synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
|
// synthesis attribute DFS_FREQUENCY_MODE of DCM_INST is "LOW"
|
// synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
|
// synthesis attribute DLL_FREQUENCY_MODE of DCM_INST is "LOW"
|
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
|
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM_INST is "TRUE"
|
// synthesis attribute FACTORY_JF of DCM_INST is "C080"
|
// synthesis attribute FACTORY_JF of DCM_INST is "C080"
|
// synthesis attribute PHASE_SHIFT of DCM_INST is "0"
|
// synthesis attribute PHASE_SHIFT of DCM_INST is "0"
|
// synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
|
// synthesis attribute STARTUP_WAIT of DCM_INST is "FALSE"
|
// synopsys translate_off
|
// synopsys translate_off
|
defparam DCM_INST.CLK_FEEDBACK = "1X";
|
defparam DCM_INST.CLK_FEEDBACK = "1X";
|
defparam DCM_INST.CLKDV_DIVIDE = 2.000000;
|
defparam DCM_INST.CLKDV_DIVIDE = 2.000000;
|
defparam DCM_INST.CLKFX_DIVIDE = 1;
|
defparam DCM_INST.CLKFX_DIVIDE = 1;
|
defparam DCM_INST.CLKFX_MULTIPLY = 4;
|
defparam DCM_INST.CLKFX_MULTIPLY = 4;
|
defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
|
defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
|
defparam DCM_INST.CLKIN_PERIOD = 6.400000;
|
defparam DCM_INST.CLKIN_PERIOD = 6.400000;
|
defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
|
defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
|
defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
|
defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
|
defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
|
defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
|
defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
|
defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
|
defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
|
defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
|
defparam DCM_INST.FACTORY_JF = 16'hC080;
|
defparam DCM_INST.FACTORY_JF = 16'hC080;
|
defparam DCM_INST.PHASE_SHIFT = 0;
|
defparam DCM_INST.PHASE_SHIFT = 0;
|
defparam DCM_INST.STARTUP_WAIT = "FALSE";
|
defparam DCM_INST.STARTUP_WAIT = "FALSE";
|
// synopsys translate_on
|
// synopsys translate_on
|
endmodule
|
endmodule
|
|
|