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Rev 40 |
module byte_count_module(CLK, RESET, START, BYTE_COUNTER);
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module byte_count_module(CLK, RESET, START, BYTE_COUNTER);
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// Ports declaration
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// Ports declaration
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input CLK;
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input CLK;
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input RESET;
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input RESET;
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input START;
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input START;
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output [15:0] BYTE_COUNTER;
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output [15:0] BYTE_COUNTER;
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reg [15:0] BYTE_COUNTER;
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reg [15:0] BYTE_COUNTER;
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reg [15:0] counter;
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reg [15:0] counter;
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always @(posedge CLK or posedge RESET)
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always @(posedge CLK or posedge RESET)
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begin
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begin
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if (RESET == 1) begin
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if (RESET == 1) begin
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counter = 16'h0000;
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counter = 16'h0000;
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end
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end
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// the ack is delayed which starts the counter
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// the ack is delayed which starts the counter
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else if (START == 1) begin
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else if (START == 1) begin
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counter = counter + 8;
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counter = counter + 8;
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end
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end
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BYTE_COUNTER = counter;
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BYTE_COUNTER = counter;
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end
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end
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endmodule // End of Module
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endmodule // End of Module
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