`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 17:11:43 12/19/05
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// Create Date: 17:11:43 12/19/05
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// Design Name:
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// Design Name:
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// Module Name: rxLinkFaultState
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// Module Name: rxLinkFaultState
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// Project Name:
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// Project Name:
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// Target Device:
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// Target Device:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module rxLinkFaultState(rxclk_2x, reset, local_fault, remote_fault, link_fault);
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module rxLinkFaultState(rxclk_2x, reset, local_fault, remote_fault, link_fault);
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input rxclk_2x;
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input rxclk_2x;
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input reset;
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input reset;
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input local_fault;
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input local_fault;
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input remote_fault;
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input remote_fault;
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output[1:0] link_fault;
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output[1:0] link_fault;
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parameter TP =1;
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parameter TP =1;
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parameter IDLE = 0, LinkFaultDetect = 1, NewFaultType = 2, GetFault = 3;
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parameter IDLE = 0, LinkFaultDetect = 1, NewFaultType = 2, GetFault = 3;
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//------------------------------------------------
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//------------------------------------------------
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// Link Fault Signalling Statemachine
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// Link Fault Signalling Statemachine
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//------------------------------------------------
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//------------------------------------------------
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wire fault_type;
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wire fault_type;
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wire get_one_fault;
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wire get_one_fault;
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wire no_new_type;
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wire no_new_type;
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reg[2:0] linkstate;
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reg[2:0] linkstate;
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reg[7:0] col_cnt;
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reg[7:0] col_cnt;
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reg[1:0] seq_cnt;
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reg[1:0] seq_cnt;
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reg[1:0] seq_type;
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reg[1:0] seq_type;
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reg[1:0] last_seq_type;
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reg[1:0] last_seq_type;
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reg[1:0] link_fault;
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reg[1:0] link_fault;
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reg reset_col_cnt;
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reg reset_col_cnt;
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assign fault_type = {local_fault, remote_fault};
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assign fault_type = {local_fault, remote_fault};
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assign get_one_fault = local_fault | remote_fault;
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assign get_one_fault = local_fault | remote_fault;
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assign no_new_type = (seq_type == last_seq_type);
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assign no_new_type = (seq_type == last_seq_type);
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assign col_cnt_128 = (col_cnt == 127);
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assign col_cnt_128 = (col_cnt == 127);
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always@(posedge rxclk_2x or posedge reset)begin
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always@(posedge rxclk_2x or posedge reset)begin
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if (reset) begin
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if (reset) begin
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seq_type <=#TP 0;
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seq_type <=#TP 0;
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seq_cnt <=#TP 0;
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seq_cnt <=#TP 0;
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last_seq_type <=#TP 0;
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last_seq_type <=#TP 0;
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reset_col_cnt<= #TP 1;
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reset_col_cnt<= #TP 1;
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link_fault <=#TP 2'b00;
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link_fault <=#TP 2'b00;
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linkstate<= #TP IDLE;
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linkstate<= #TP IDLE;
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end
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end
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else begin
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else begin
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seq_type <= #TP fault_type;
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seq_type <= #TP fault_type;
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last_seq_type <=#TP seq_type;
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last_seq_type <=#TP seq_type;
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case (linkstate)
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case (linkstate)
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IDLE: begin
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IDLE: begin
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linkstate <=#TP IDLE;
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linkstate <=#TP IDLE;
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reset_col_cnt <= #TP 1;
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reset_col_cnt <= #TP 1;
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seq_cnt <= #TP 0;
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seq_cnt <= #TP 0;
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link_fault <= #TP 2'b00;
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link_fault <= #TP 2'b00;
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if (get_one_fault)
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if (get_one_fault)
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linkstate<=#TP LinkFaultDetect;
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linkstate<=#TP LinkFaultDetect;
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end
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end
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LinkFaultDetect: begin
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LinkFaultDetect: begin
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linkstate <=#TP LinkFaultDetect;
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linkstate <=#TP LinkFaultDetect;
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reset_col_cnt <=#TP 1;
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reset_col_cnt <=#TP 1;
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if (get_one_fault & no_new_type)
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if (get_one_fault & no_new_type)
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if (seq_cnt < 3)
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if (seq_cnt < 3)
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seq_cnt <=#TP seq_cnt + 1;
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seq_cnt <=#TP seq_cnt + 1;
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else linkstate <=#TP GetFault;
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else linkstate <=#TP GetFault;
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else if(~get_one_fault)
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else if(~get_one_fault)
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if(col_cnt_128) begin
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if(col_cnt_128) begin
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linkstate <=#TP IDLE;
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linkstate <=#TP IDLE;
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reset_col_cnt <=#TP 1;
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reset_col_cnt <=#TP 1;
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end
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end
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else reset_col_cnt <=#TP 0;
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else reset_col_cnt <=#TP 0;
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else if(get_one_fault & ~no_new_type)
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else if(get_one_fault & ~no_new_type)
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linkstate <=#TP NewFaultType;
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linkstate <=#TP NewFaultType;
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end
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end
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NewFaultType: begin
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NewFaultType: begin
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seq_cnt <=#TP 0;
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seq_cnt <=#TP 0;
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linkstate <=#TP LinkFaultDetect;
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linkstate <=#TP LinkFaultDetect;
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reset_col_cnt<=#TP 1;
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reset_col_cnt<=#TP 1;
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end
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end
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GetFault: begin
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GetFault: begin
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linkstate <=#TP GetFault;
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linkstate <=#TP GetFault;
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reset_col_cnt <=#TP 1;
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reset_col_cnt <=#TP 1;
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if (get_one_fault & no_new_type)
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if (get_one_fault & no_new_type)
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link_fault <=#TP seq_type;
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link_fault <=#TP seq_type;
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else if (~get_one_fault) begin
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else if (~get_one_fault) begin
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reset_col_cnt<=#TP 0;
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reset_col_cnt<=#TP 0;
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if(col_cnt_128)
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if(col_cnt_128)
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linkstate <=#TP IDLE;
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linkstate <=#TP IDLE;
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end
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end
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else if (get_one_fault & ~no_new_type)
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else if (get_one_fault & ~no_new_type)
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linkstate <=#TP NewFaultType;
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linkstate <=#TP NewFaultType;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always@(posedge rxclk_2x or posedge reset) begin
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always@(posedge rxclk_2x or posedge reset) begin
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if (reset)
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if (reset)
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col_cnt <=#TP 0;
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col_cnt <=#TP 0;
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else if (reset_col_cnt)
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else if (reset_col_cnt)
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col_cnt <=#TP 0;
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col_cnt <=#TP 0;
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else
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else
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col_cnt <=#TP col_cnt + 1;
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col_cnt <=#TP col_cnt + 1;
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end
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end
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endmodule
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endmodule
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