`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 16:35:47 11/21/05
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// Create Date: 16:35:47 11/21/05
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// Design Name:
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// Design Name:
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// Module Name: rxReceiveEngine
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// Module Name: rxReceiveEngine
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// Project Name:
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// Project Name:
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// Target Device:
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// Target Device:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module rxReceiveEngine(rxclk_in, reset_in, rxd64, rxc8, rxStatRegPlus,reset_out,
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module rxReceiveEngine(rxclk_in, reset_in, rxd64, rxc8, rxStatRegPlus,reset_out,
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cfgRxRegData, rx_data, rx_data_valid, rx_good_frame, link_fault,
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cfgRxRegData, rx_data, rx_data_valid, rx_good_frame, link_fault,
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rx_bad_frame, rxCfgofRS, rxTxLinkFaul);
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rx_bad_frame, rxCfgofRS, rxTxLinkFaul);
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input rxclk_in;
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input rxclk_in;
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input reset_in;
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input reset_in;
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input [63:0] rxd64;
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input [63:0] rxd64;
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input [7:0] rxc8;
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input [7:0] rxc8;
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output reset_out;
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output reset_out;
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output [12:0] rxStatRegPlus;
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output [12:0] rxStatRegPlus;
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input [52:0] cfgRxRegData;
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input [52:0] cfgRxRegData;
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output [63:0] rx_data;
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output [63:0] rx_data;
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output [7:0] rx_data_valid;
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output [7:0] rx_data_valid;
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output rx_good_frame;
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output rx_good_frame;
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output rx_bad_frame;
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output rx_bad_frame;
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input [1:0] link_fault;
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input [1:0] link_fault;
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output[2:0] rxCfgofRS;
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output[2:0] rxCfgofRS;
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output [1:0] rxTxLinkFaul;
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output [1:0] rxTxLinkFaul;
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wire rxclk;
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wire rxclk;
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wire rxclk_180;
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wire rxclk_180;
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wire rxclk_2x;
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wire rxclk_2x;
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wire locked;
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wire locked;
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wire reset_dcm;
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wire reset_dcm;
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wire reset;
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wire reset;
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wire [47:0]MAC_Addr; //MAC Address used in receiving control frame.
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wire [47:0]MAC_Addr; //MAC Address used in receiving control frame.
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wire vlan_enable; //VLAN Enable
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wire vlan_enable; //VLAN Enable
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wire recv_enable; //Receiver Enable
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wire recv_enable; //Receiver Enable
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wire inband_fcs; //In-band FCS Enable, when this bit is '1', the MAC will pass FCS up to client
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wire inband_fcs; //In-band FCS Enable, when this bit is '1', the MAC will pass FCS up to client
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wire jumbo_enable;//Jumbo Frame Enable
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wire jumbo_enable;//Jumbo Frame Enable
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wire recv_rst; //Receiver reset
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wire recv_rst; //Receiver reset
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wire start_da, start_lt;
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wire start_da, start_lt;
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wire tagged_frame, small_frame;
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wire tagged_frame, small_frame;
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wire [15:0] tagged_len;
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wire [15:0] tagged_len;
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wire end_data_cnt, end_small_cnt, end_tagged_cnt, end_fcs;
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wire end_data_cnt, end_small_cnt, end_tagged_cnt, end_fcs;
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wire pause_frame;
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wire pause_frame;
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wire [47:0] da_addr;
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wire [47:0] da_addr;
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wire [15:0] lt_data;
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wire [15:0] lt_data;
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wire [31:0] crc_code;
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wire [31:0] crc_code;
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wire [7:0] crc_valid;
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wire [7:0] crc_valid;
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wire [7:0] rxc_fifo;
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wire [7:0] rxc_fifo;
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wire length_error;
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wire length_error;
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wire get_sfd, get_efd, get_error_code;
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wire get_sfd, get_efd, get_error_code;
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wire receiving;
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wire receiving;
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wire receiving_frame;
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wire receiving_frame;
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wire local_invalid;
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wire local_invalid;
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wire broad_valid;
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wire broad_valid;
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wire multi_valid;
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wire multi_valid;
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wire len_invalid;
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wire len_invalid;
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wire [12:0] integer_cnt, small_integer_cnt;
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wire [12:0] integer_cnt, small_integer_cnt;
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wire [2:0] bits_more, small_bits_more;
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wire [2:0] bits_more, small_bits_more;
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wire good_frame_get, bad_frame_get;
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wire good_frame_get, bad_frame_get;
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wire crc_check_valid=0;
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wire crc_check_valid=0;
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wire crc_check_invalid=0;
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wire crc_check_invalid=0;
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//////////////////////////////////////////
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//////////////////////////////////////////
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// Read Receiver Configuration Word
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// Read Receiver Configuration Word
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//////////////////////////////////////////
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//////////////////////////////////////////
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assign MAC_Addr = {cfgRxRegData[52:37], cfgRxRegData[31:0]};
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assign MAC_Addr = {cfgRxRegData[52:37], cfgRxRegData[31:0]};
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assign vlan_enable = cfgRxRegData[36];
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assign vlan_enable = cfgRxRegData[36];
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assign recv_enable = cfgRxRegData[35];
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assign recv_enable = cfgRxRegData[35];
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assign inband_fcs = cfgRxRegData[34];
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assign inband_fcs = cfgRxRegData[34];
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assign jumbo_enable = cfgRxRegData[33];
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assign jumbo_enable = cfgRxRegData[33];
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assign recv_rst = cfgRxRegData[32];
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assign recv_rst = cfgRxRegData[32];
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assign reset_dcm = reset_in | recv_rst;
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assign reset_dcm = reset_in | recv_rst;
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assign reset = ~locked;
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assign reset = ~locked;
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assign reset_out = reset;
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assign reset_out = reset;
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/////////////////////////////////////////
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/////////////////////////////////////////
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// Write Configuration Words of RS
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// Write Configuration Words of RS
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/////////////////////////////////////////
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/////////////////////////////////////////
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assign rxCfgofRS[0] = ~link_fault[0] & link_fault[1]; //get local fault
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assign rxCfgofRS[0] = ~link_fault[0] & link_fault[1]; //get local fault
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assign rxCfgofRS[1] = link_fault[0] & link_fault[1]; //get remote fault
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assign rxCfgofRS[1] = link_fault[0] & link_fault[1]; //get remote fault
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assign rxCfgofRS[2] = locked; //Receive DCM locked
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assign rxCfgofRS[2] = locked; //Receive DCM locked
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////////////////////////////////////////
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////////////////////////////////////////
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// Receive Clock Generator
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// Receive Clock Generator
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////////////////////////////////////////
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////////////////////////////////////////
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rxClkgen rxclk_gen(.rxclk_in(rxclk_in),
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rxClkgen rxclk_gen(.rxclk_in(rxclk_in),
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.reset(reset_dcm),
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.reset(reset_dcm),
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.rxclk(rxclk),
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.rxclk(rxclk),
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.rxclk_180(rxclk_180),
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.rxclk_180(rxclk_180),
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.rxclk_2x(rxclk_2x),
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.rxclk_2x(rxclk_2x),
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.locked(locked)
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.locked(locked)
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);
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);
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///////////////////////////////////////
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///////////////////////////////////////
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// Upper Interface with client
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// Upper Interface with client
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///////////////////////////////////////
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///////////////////////////////////////
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rxFIFOMgnt upperinterface(.rxclk_180(rxclk_180), .reset(reset), .rxd64(rxd64), .rxc_fifo(rxc_fifo), .receiving(receiving),
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rxFIFOMgnt upperinterface(.rxclk_180(rxclk_180), .reset(reset), .rxd64(rxd64), .rxc_fifo(rxc_fifo), .receiving(receiving),
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.recv_end(recv_end), .rx_data_valid(rx_data_valid), .inband_fcs(inband_fcs),
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.recv_end(recv_end), .rx_data_valid(rx_data_valid), .inband_fcs(inband_fcs),
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.rx_data(rx_data));
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.rx_data(rx_data));
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///////////////////////////////////////
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///////////////////////////////////////
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// Reception Frame Spliter
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// Reception Frame Spliter
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///////////////////////////////////////
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///////////////////////////////////////
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rxFrameDepart frame_spliter(.rxclk(rxclk), .reset(reset), .rxclk_180(rxclk_180), .rxd64(rxd64), .rxc8(rxc8),.inband_fcs(inband_fcs),
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rxFrameDepart frame_spliter(.rxclk(rxclk), .reset(reset), .rxclk_180(rxclk_180), .rxd64(rxd64), .rxc8(rxc8),.inband_fcs(inband_fcs),
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.start_da(start_da), .start_lt(start_lt), .tagged_frame(tagged_frame),.bits_more(bits_more),
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.start_da(start_da), .start_lt(start_lt), .tagged_frame(tagged_frame),.bits_more(bits_more),
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.small_bits_more(small_bits_more), .tagged_len(tagged_len), .small_frame(small_frame),
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.small_bits_more(small_bits_more), .tagged_len(tagged_len), .small_frame(small_frame),
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.end_data_cnt(end_data_cnt), .end_small_cnt(end_small_cnt),.da_addr(da_addr),.lt_data(lt_data),
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.end_data_cnt(end_data_cnt), .end_small_cnt(end_small_cnt),.da_addr(da_addr),.lt_data(lt_data),
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.crc_code(crc_code),.end_fcs(end_fcs), .crc_valid(crc_valid), .length_error(length_error),
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.crc_code(crc_code),.end_fcs(end_fcs), .crc_valid(crc_valid), .length_error(length_error),
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.get_sfd(get_sfd), .get_efd(get_efd), .get_error_code(get_error_code),.receiving(receiving),
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.get_sfd(get_sfd), .get_efd(get_efd), .get_error_code(get_error_code),.receiving(receiving),
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.rxc_fifo(rxc_fifo),.receiving_frame(receiving_frame)
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.rxc_fifo(rxc_fifo),.receiving_frame(receiving_frame)
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);
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);
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//////////////////////////////////////
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//////////////////////////////////////
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// Destination Address Checker
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// Destination Address Checker
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//////////////////////////////////////
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//////////////////////////////////////
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rxDAchecker dachecker(.local_invalid(local_invalid), .broad_valid(broad_valid), .multi_valid(multi_valid), .MAC_Addr(MAC_Addr),
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rxDAchecker dachecker(.local_invalid(local_invalid), .broad_valid(broad_valid), .multi_valid(multi_valid), .MAC_Addr(MAC_Addr),
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.da_addr(da_addr));
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.da_addr(da_addr));
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defparam dachecker.Multicast = 48'h0180C2000001;
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defparam dachecker.Multicast = 48'h0180C2000001;
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defparam dachecker.Broadcast = 48'hffffffffffff;
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defparam dachecker.Broadcast = 48'hffffffffffff;
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/////////////////////////////////////
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/////////////////////////////////////
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// Length/Type field checker
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// Length/Type field checker
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/////////////////////////////////////
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/////////////////////////////////////
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rxLenTypChecker lenchecker(.lt_data(lt_data), .tagged_len(tagged_len), .jumbo_enable(jumbo_enable), .tagged_frame(tagged_frame),
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rxLenTypChecker lenchecker(.lt_data(lt_data), .tagged_len(tagged_len), .jumbo_enable(jumbo_enable), .tagged_frame(tagged_frame),
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.pause_frame(pause_frame), .small_frame(small_frame), .len_invalid(len_invalid), .vlan_enable(vlan_enable),
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.pause_frame(pause_frame), .small_frame(small_frame), .len_invalid(len_invalid), .vlan_enable(vlan_enable),
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.integer_cnt(integer_cnt), .small_integer_cnt(small_integer_cnt), .inband_fcs(inband_fcs),
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.integer_cnt(integer_cnt), .small_integer_cnt(small_integer_cnt), .inband_fcs(inband_fcs),
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.bits_more(bits_more), .small_bits_more(small_bits_more)
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.bits_more(bits_more), .small_bits_more(small_bits_more)
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);
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);
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/////////////////////////////////////
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/////////////////////////////////////
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// Counters used in Receive Engine
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// Counters used in Receive Engine
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/////////////////////////////////////
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/////////////////////////////////////
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rxNumCounter counters(.rxclk(rxclk), .reset(reset), .start_data_cnt(start_data_cnt), .start_tagged_cnt(start_tagged_cnt), .small_frame(small_frame),
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rxNumCounter counters(.rxclk(rxclk), .reset(reset), .start_data_cnt(start_data_cnt), .start_tagged_cnt(start_tagged_cnt), .small_frame(small_frame),
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.integer_cnt(integer_cnt), .small_integer_cnt(small_integer_cnt), .tagged_frame(tagged_frame),
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.integer_cnt(integer_cnt), .small_integer_cnt(small_integer_cnt), .tagged_frame(tagged_frame),
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.end_data_cnt(end_data_cnt), .end_small_cnt(end_small_cnt), .end_tagged_cnt(end_tagged_cnt)
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.end_data_cnt(end_data_cnt), .end_small_cnt(end_small_cnt), .end_tagged_cnt(end_tagged_cnt)
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);
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);
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/////////////////////////////////////
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/////////////////////////////////////
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// State Machine in Receive Process
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// State Machine in Receive Process
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/////////////////////////////////////
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/////////////////////////////////////
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rxStateMachine statemachine(.rxclk(rxclk), .reset(reset), .recv_enable(recv_enable), .get_sfd(get_sfd), .local_invalid(local_invalid), .len_invalid(len_invalid),
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rxStateMachine statemachine(.rxclk(rxclk), .reset(reset), .recv_enable(recv_enable), .get_sfd(get_sfd), .local_invalid(local_invalid), .len_invalid(len_invalid),
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.end_data_cnt(end_data_cnt), .end_tagged_cnt(end_tagged_cnt), .tagged_frame(tagged_frame),
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.end_data_cnt(end_data_cnt), .end_tagged_cnt(end_tagged_cnt), .tagged_frame(tagged_frame),
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.length_error(length_error), .end_fcs(end_fcs), .crc_check_valid(crc_check_valid), .get_error_code(get_error_code),
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.length_error(length_error), .end_fcs(end_fcs), .crc_check_valid(crc_check_valid), .get_error_code(get_error_code),
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.crc_check_invalid(crc_check_invalid), .start_da(start_da), .start_lt(start_lt), .inband_fcs(inband_fcs),
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.crc_check_invalid(crc_check_invalid), .start_da(start_da), .start_lt(start_lt), .inband_fcs(inband_fcs),
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.start_data_cnt(start_data_cnt), .start_tagged_cnt(start_tagged_cnt), .receiving(receiving),
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.start_data_cnt(start_data_cnt), .start_tagged_cnt(start_tagged_cnt), .receiving(receiving),
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.recv_end(recv_end), .good_frame_get(good_frame_get), .bad_frame_get(bad_frame_get), .small_frame(small_frame),
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.recv_end(recv_end), .good_frame_get(good_frame_get), .bad_frame_get(bad_frame_get), .small_frame(small_frame),
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.end_small_cnt(end_small_cnt),.receiving_frame(receiving_frame)
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.end_small_cnt(end_small_cnt),.receiving_frame(receiving_frame)
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);
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);
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assign rx_good_frame = good_frame_get;
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assign rx_good_frame = good_frame_get;
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assign rx_bad_frame = bad_frame_get;
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assign rx_bad_frame = bad_frame_get;
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endmodule
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endmodule
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