`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 09:59:01 11/21/05
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// Create Date: 09:59:01 11/21/05
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// Design Name:
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// Design Name:
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// Module Name: rxStateMachine
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// Module Name: rxStateMachine
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// Project Name:
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// Project Name:
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// Target Device:
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// Target Device:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module rxStateMachine(rxclk, reset, recv_enable, get_sfd, local_invalid, len_invalid, end_data_cnt, end_tagged_cnt,
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module rxStateMachine(rxclk, reset, recv_enable, get_sfd, local_invalid, len_invalid, end_data_cnt, end_tagged_cnt,
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tagged_frame, length_error, end_fcs, crc_check_valid, crc_check_invalid, start_da, start_lt, inband_fcs,
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tagged_frame, length_error, end_fcs, crc_check_valid, crc_check_invalid, start_da, start_lt, inband_fcs,
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start_data_cnt, start_tagged_cnt, receiving, recv_end, good_frame_get, bad_frame_get, get_error_code, small_frame
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start_data_cnt, start_tagged_cnt, receiving, recv_end, good_frame_get, bad_frame_get, get_error_code, small_frame
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, end_small_cnt,receiving_frame);
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, end_small_cnt,receiving_frame);
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input rxclk;
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input rxclk;
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input reset;
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input reset;
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input recv_enable;
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input recv_enable;
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input inband_fcs;
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input inband_fcs;
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//PRE & SFD
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//PRE & SFD
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input get_sfd; // SFD has been received;
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input get_sfd; // SFD has been received;
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//DA field
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//DA field
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input local_invalid;// The Frame's DA field is not Local MAC;
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input local_invalid;// The Frame's DA field is not Local MAC;
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//Length/Type field
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//Length/Type field
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input len_invalid;// Indicate if Length field is valid;
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input len_invalid;// Indicate if Length field is valid;
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input end_data_cnt;// Indicate end of receiving DATA field(not jumbo frame);
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input end_data_cnt;// Indicate end of receiving DATA field(not jumbo frame);
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input end_tagged_cnt;// Indicate end of receiving DATA field of tagged Frame;
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input end_tagged_cnt;// Indicate end of receiving DATA field of tagged Frame;
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input end_small_cnt; // Indicate end of receiving small data field
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input end_small_cnt; // Indicate end of receiving small data field
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input tagged_frame;// Indicate current frame is a jumbo_frame;
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input tagged_frame;// Indicate current frame is a jumbo_frame;
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input small_frame; // Indicate current frame is a small frame;
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input small_frame; // Indicate current frame is a small frame;
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input length_error;//Indicate Length received is not equal to the Length in LT field;
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input length_error;//Indicate Length received is not equal to the Length in LT field;
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//FCS field
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//FCS field
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input end_fcs;//Indicate end of receiving FCS field;
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input end_fcs;//Indicate end of receiving FCS field;
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input crc_check_valid;//Indicate the frame passed CRC Check;
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input crc_check_valid;//Indicate the frame passed CRC Check;
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input crc_check_invalid;//Indicate the frame failed in CRC Check;
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input crc_check_invalid;//Indicate the frame failed in CRC Check;
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input get_error_code;
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input get_error_code;
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//DA field
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//DA field
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output start_da;// Start to receive Destination Address;
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output start_da;// Start to receive Destination Address;
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//Length/Type field
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//Length/Type field
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output start_lt;// Start to receive Length/Type field;
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output start_lt;// Start to receive Length/Type field;
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//DATA field
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//DATA field
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output start_data_cnt;// Start to receive DATA field;
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output start_data_cnt;// Start to receive DATA field;
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output start_tagged_cnt;// Start to receive DATA field, but the frame is a tagged frame.
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output start_tagged_cnt;// Start to receive DATA field, but the frame is a tagged frame.
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//Receive process control
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//Receive process control
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output receiving;// Rx Engine is receiving valid part of frame;
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output receiving;// Rx Engine is receiving valid part of frame;
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output receiving_frame; //Rx Engine is working, not in IDLE state and Check state.
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output receiving_frame; //Rx Engine is working, not in IDLE state and Check state.
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output recv_end; // Receive process ends, either because formal ending or faults happen;
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output recv_end; // Receive process ends, either because formal ending or faults happen;
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output good_frame_get;// A good frame has been received;
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output good_frame_get;// A good frame has been received;
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output bad_frame_get; // A bad frame has been received;
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output bad_frame_get; // A bad frame has been received;
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parameter IDLE = 0, rxReceiveDA = 1, rxReceiveLT = 2, rxReceiveData = 3;
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parameter IDLE = 0, rxReceiveDA = 1, rxReceiveLT = 2, rxReceiveData = 3;
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parameter rxReceiveFCS = 4, rxWaitCheck = 5;
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parameter rxReceiveFCS = 4, rxWaitCheck = 5;
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parameter TP =1;
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parameter TP =1;
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wire start_da;
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wire start_da;
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wire start_lt;
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wire start_lt;
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wire start_data_cnt;
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wire start_data_cnt;
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wire start_tagged_cnt;
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wire start_tagged_cnt;
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wire receiving_data;
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wire receiving_data;
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wire receiving_frame;
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wire receiving_frame;
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wire receiving;
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wire receiving;
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wire recv_end;
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wire recv_end;
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wire good_frame_get;
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wire good_frame_get;
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wire bad_frame_get;
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wire bad_frame_get;
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reg[2:0] rxstate, rxstate_next;
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reg[2:0] rxstate, rxstate_next;
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always@(rxstate, get_sfd, local_invalid, len_invalid, recv_enable,
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always@(rxstate, get_sfd, local_invalid, len_invalid, recv_enable,
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tagged_frame, end_data_cnt, end_tagged_cnt, get_error_code,
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tagged_frame, end_data_cnt, end_tagged_cnt, get_error_code,
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end_fcs, length_error, crc_check_valid,crc_check_invalid, reset)begin
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end_fcs, length_error, crc_check_valid,crc_check_invalid, reset)begin
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if (reset) begin
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if (reset) begin
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rxstate_next <=#TP IDLE;
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rxstate_next <=#TP IDLE;
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end
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end
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else begin
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else begin
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case (rxstate)
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case (rxstate)
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IDLE: begin
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IDLE: begin
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if (get_sfd & recv_enable)
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if (get_sfd & recv_enable)
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rxstate_next <=#TP rxReceiveDA;
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rxstate_next <=#TP rxReceiveDA;
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end
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end
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rxReceiveDA: begin
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rxReceiveDA: begin
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rxstate_next <=#TP rxReceiveLT;
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rxstate_next <=#TP rxReceiveLT;
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end
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end
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rxReceiveLT: begin
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rxReceiveLT: begin
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rxstate_next <=#TP rxReceiveData;
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rxstate_next <=#TP rxReceiveData;
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end
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end
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rxReceiveData: begin
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rxReceiveData: begin
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if (local_invalid | len_invalid | get_error_code)
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if (local_invalid | len_invalid | get_error_code)
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rxstate_next <=#TP rxWaitCheck;
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rxstate_next <=#TP rxWaitCheck;
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else if (end_data_cnt | end_tagged_cnt)
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else if (end_data_cnt | end_tagged_cnt)
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rxstate_next <=#TP rxReceiveFCS;
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rxstate_next <=#TP rxReceiveFCS;
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end
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end
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rxReceiveFCS: begin //length_error should have high priority to end_fcs
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rxReceiveFCS: begin //length_error should have high priority to end_fcs
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if (length_error)
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if (length_error)
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rxstate_next <=#TP IDLE;
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rxstate_next <=#TP IDLE;
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else if (end_fcs)
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else if (end_fcs)
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rxstate_next <=#TP rxWaitCheck;
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rxstate_next <=#TP rxWaitCheck;
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end
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end
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rxWaitCheck: begin
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rxWaitCheck: begin
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if (crc_check_valid)
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if (crc_check_valid)
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rxstate_next <=#TP IDLE;
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rxstate_next <=#TP IDLE;
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else if (local_invalid | len_invalid | length_error | crc_check_invalid)
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else if (local_invalid | len_invalid | length_error | crc_check_invalid)
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rxstate_next <=#TP IDLE;
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rxstate_next <=#TP IDLE;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always@(posedge rxclk or posedge reset) begin
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always@(posedge rxclk or posedge reset) begin
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if (reset)
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if (reset)
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rxstate <=#TP IDLE;
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rxstate <=#TP IDLE;
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else
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else
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rxstate <=#TP rxstate_next;
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rxstate <=#TP rxstate_next;
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end
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end
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reg end_small_cnt_d1;
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reg end_small_cnt_d1;
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reg end_small_cnt_d2;
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reg end_small_cnt_d2;
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always@(posedge rxclk or posedge reset) begin
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always@(posedge rxclk or posedge reset) begin
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if (reset)begin
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if (reset)begin
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end_small_cnt_d1 <= 0;
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end_small_cnt_d1 <= 0;
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end_small_cnt_d2 <= 0;
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end_small_cnt_d2 <= 0;
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end
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end
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else begin
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else begin
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end_small_cnt_d1 <=end_small_cnt;
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end_small_cnt_d1 <=end_small_cnt;
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if (end_small_cnt_d1)
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if (end_small_cnt_d1)
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end_small_cnt_d2 <= 1'b1;
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end_small_cnt_d2 <= 1'b1;
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else
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else
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end_small_cnt_d2 <= #TP end_small_cnt_d2;
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end_small_cnt_d2 <= #TP end_small_cnt_d2;
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end
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end
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end
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end
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assign start_da = (rxstate == rxReceiveDA);
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assign start_da = (rxstate == rxReceiveDA);
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assign start_lt = (rxstate == rxReceiveLT);
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assign start_lt = (rxstate == rxReceiveLT);
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assign start_data_cnt = (rxstate == rxReceiveData) & (~tagged_frame);
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assign start_data_cnt = (rxstate == rxReceiveData) & (~tagged_frame);
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assign start_tagged_cnt = (rxstate == rxReceiveData) & tagged_frame;
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assign start_tagged_cnt = (rxstate == rxReceiveData) & tagged_frame;
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assign receiving_data = (~rxstate[2]&(rxstate[0] | rxstate[1])); // in DA,LT,DATA status
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assign receiving_data = (~rxstate[2]&(rxstate[0] | rxstate[1])); // in DA,LT,DATA status
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assign receiving_frame = receiving_data |(rxstate[2]&~rxstate[1]&~rxstate[0]); //in DA,LT,Data,FCS status
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assign receiving_frame = receiving_data |(rxstate[2]&~rxstate[1]&~rxstate[0]); //in DA,LT,Data,FCS status
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assign receiving_small = start_da | start_lt | ((rxstate == rxReceiveData) & ~end_small_cnt_d2);
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assign receiving_small = start_da | start_lt | ((rxstate == rxReceiveData) & ~end_small_cnt_d2);
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assign receiving = inband_fcs? receiving_frame:(small_frame? receiving_small:receiving_data);
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assign receiving = inband_fcs? receiving_frame:(small_frame? receiving_small:receiving_data);
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assign recv_end = ~receiving_frame;
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assign recv_end = ~receiving_frame;
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assign bad_frame_get = ((rxstate == rxReceiveFCS) & length_error) | ((rxstate == rxWaitCheck) & (local_invalid | len_invalid | length_error | crc_check_invalid));
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assign bad_frame_get = ((rxstate == rxReceiveFCS) & length_error) | ((rxstate == rxWaitCheck) & (local_invalid | len_invalid | length_error | crc_check_invalid));
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assign good_frame_get = (rxstate == rxWaitCheck) & crc_check_valid;
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assign good_frame_get = (rxstate == rxWaitCheck) & crc_check_valid;
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endmodule
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endmodule
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