`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 15:23:18 12/26/2005
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// Create Date: 15:23:18 12/26/2005
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// Design Name: rxReceiveEngine
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// Design Name: rxReceiveEngine
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// Module Name: rxtest.v
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// Module Name: rxtest.v
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// Project Name: ethmac10g
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// Project Name: ethmac10g
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// Target Device:
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// Target Device:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Verilog Test Fixture created by ISE for module: rxReceiveEngine
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// Verilog Test Fixture created by ISE for module: rxReceiveEngine
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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module rxtest_v;
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module rxtest_v;
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// Inputs
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// Inputs
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reg rxclk_in;
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reg rxclk_in;
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reg reset_in;
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reg reset_in;
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reg [63:0] rxd64;
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reg [63:0] rxd64;
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reg [7:0] rxc8;
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reg [7:0] rxc8;
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reg [52:0] cfgRxRegData;
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reg [52:0] cfgRxRegData;
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reg [1:0] link_fault;
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reg [1:0] link_fault;
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// Outputs
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// Outputs
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wire [12:0] rxStatRegPlus;
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wire [12:0] rxStatRegPlus;
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wire [63:0] rx_data;
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wire [63:0] rx_data;
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wire [7:0] rx_data_valid;
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wire [7:0] rx_data_valid;
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wire rx_good_frame;
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wire rx_good_frame;
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wire rx_bad_frame;
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wire rx_bad_frame;
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wire [2:0] rxCfgofRS;
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wire [2:0] rxCfgofRS;
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wire [1:0] rxTxLinkFaul;
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wire [1:0] rxTxLinkFaul;
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wire reset_out;
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wire reset_out;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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rxReceiveEngine uut (
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rxReceiveEngine uut (
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.rxclk_in(rxclk_in),
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.rxclk_in(rxclk_in),
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.reset_in(reset_in),
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.reset_in(reset_in),
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.reset_out(reset_out),
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.reset_out(reset_out),
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.rxd64(rxd64),
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.rxd64(rxd64),
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.rxc8(rxc8),
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.rxc8(rxc8),
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.rxStatRegPlus(rxStatRegPlus),
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.rxStatRegPlus(rxStatRegPlus),
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.cfgRxRegData(cfgRxRegData),
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.cfgRxRegData(cfgRxRegData),
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.rx_data(rx_data),
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.rx_data(rx_data),
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.rx_data_valid(rx_data_valid),
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.rx_data_valid(rx_data_valid),
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.rx_good_frame(rx_good_frame),
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.rx_good_frame(rx_good_frame),
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.link_fault(link_fault),
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.link_fault(link_fault),
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.rx_bad_frame(rx_bad_frame),
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.rx_bad_frame(rx_bad_frame),
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.rxCfgofRS(rxCfgofRS),
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.rxCfgofRS(rxCfgofRS),
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.rxTxLinkFaul(rxTxLinkFaul)
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.rxTxLinkFaul(rxTxLinkFaul)
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);
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);
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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rxclk_in = 0;
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rxclk_in = 0;
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rxd64 = 0;
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rxd64 = 0;
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rxc8 = 0;
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rxc8 = 0;
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cfgRxRegData = 0;
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cfgRxRegData = 0;
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cfgRxRegData[35] = 1'b1;//recv_enable
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cfgRxRegData[35] = 1'b1;//recv_enable
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cfgRxRegData[36] = 1'b1;//vlan enable
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cfgRxRegData[36] = 1'b1;//vlan enable
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cfgRxRegData[34] = 1'b0;//inband fcs
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cfgRxRegData[34] = 1'b0;//inband fcs
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cfgRxRegData[52:37] = 16'h00c0;
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cfgRxRegData[52:37] = 16'h00c0;
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cfgRxRegData[31:0]=32'h9fe22972;
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cfgRxRegData[31:0]=32'h9fe22972;
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link_fault = 0;
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link_fault = 0;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#100;
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#100;
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// Add stimulus here
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// Add stimulus here
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end
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end
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wire [63:0]testvector1[15:0]; //normal frame
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wire [63:0]testvector1[15:0]; //normal frame
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wire [7:0] testvector2[15:0];
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wire [7:0] testvector2[15:0];
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wire [63:0]smallvector1[10:0]; //small frame
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wire [63:0]smallvector1[10:0]; //small frame
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wire [7:0] smallvector2[10:0];
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wire [7:0] smallvector2[10:0];
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wire [63:0]taggedvector1[15:0];
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wire [63:0]taggedvector1[15:0];
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wire [7:0] taggedvector2[15:0];
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wire [7:0] taggedvector2[15:0];
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assign testvector1[0] = 64'h0707070707070707;
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assign testvector1[0] = 64'h0707070707070707;
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assign testvector1[1] = 64'hfbaaaaaaaaaaaaab;
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assign testvector1[1] = 64'hfbaaaaaaaaaaaaab;
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assign testvector1[2] = 64'h00c09fe229720015;
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assign testvector1[2] = 64'h00c09fe229720015;
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assign testvector1[3] = 64'h0024ac34004e9889;
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assign testvector1[3] = 64'h0024ac34004e9889;
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// assign testvector1[3] = 64'h0024ac3400639889; //length error frame
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// assign testvector1[3] = 64'h0024ac3400639889; //length error frame
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assign testvector1[4] = 64'h1234567890123456;
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assign testvector1[4] = 64'h1234567890123456;
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assign testvector1[5] = 64'h7890123456789012;
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assign testvector1[5] = 64'h7890123456789012;
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assign testvector1[6] = 64'h3456789012345678;
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assign testvector1[6] = 64'h3456789012345678;
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assign testvector1[7] = 64'h9012345678901234;
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assign testvector1[7] = 64'h9012345678901234;
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assign testvector1[8] = 64'h5678901234567890;
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assign testvector1[8] = 64'h5678901234567890;
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assign testvector1[9] = 64'h1234567890123456;
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assign testvector1[9] = 64'h1234567890123456;
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assign testvector1[10] = 64'h7890123456789012;
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assign testvector1[10] = 64'h7890123456789012;
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assign testvector1[11] = 64'h3456789012345678;
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assign testvector1[11] = 64'h3456789012345678;
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assign testvector1[12] = 64'h9012345678901234;
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assign testvector1[12] = 64'h9012345678901234;
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assign testvector1[13] = 64'h5678901234555555;
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assign testvector1[13] = 64'h5678901234555555;
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assign testvector1[14] = 64'h55fd070707070707;
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assign testvector1[14] = 64'h55fd070707070707;
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assign testvector1[15] = 64'h0707070707070707;
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assign testvector1[15] = 64'h0707070707070707;
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assign testvector2[0] = 8'hff;
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assign testvector2[0] = 8'hff;
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assign testvector2[1] = 8'h80;
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assign testvector2[1] = 8'h80;
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assign testvector2[2] = 8'h00;
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assign testvector2[2] = 8'h00;
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assign testvector2[3] = 8'h00;
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assign testvector2[3] = 8'h00;
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assign testvector2[4] = 8'h00;
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assign testvector2[4] = 8'h00;
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assign testvector2[5] = 8'h00;
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assign testvector2[5] = 8'h00;
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assign testvector2[6] = 8'h00;
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assign testvector2[6] = 8'h00;
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assign testvector2[7] = 8'h00;
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assign testvector2[7] = 8'h00;
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assign testvector2[8] = 8'h00;
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assign testvector2[8] = 8'h00;
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assign testvector2[9] = 8'h00;
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assign testvector2[9] = 8'h00;
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assign testvector2[10] = 8'h00;
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assign testvector2[10] = 8'h00;
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assign testvector2[11] = 8'h00;
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assign testvector2[11] = 8'h00;
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assign testvector2[12] = 8'h00;
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assign testvector2[12] = 8'h00;
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assign testvector2[13] = 8'h00;
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assign testvector2[13] = 8'h00;
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assign testvector2[14] = 8'h4f;
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assign testvector2[14] = 8'h4f;
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assign testvector2[15] = 8'hff;
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assign testvector2[15] = 8'hff;
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assign smallvector1[0] = 64'h0707070707070707;
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assign smallvector1[0] = 64'h0707070707070707;
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assign smallvector1[1] = 64'hfbaaaaaaaaaaaaab;
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assign smallvector1[1] = 64'hfbaaaaaaaaaaaaab;
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assign smallvector1[2] = 64'h00c09fe229720015;
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assign smallvector1[2] = 64'h00c09fe229720015;
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assign smallvector1[3] = 64'h0024ac3400039889;
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assign smallvector1[3] = 64'h0024ac3400039889;
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assign smallvector1[4] = 64'h1234567890123456;
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assign smallvector1[4] = 64'h1234567890123456;
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assign smallvector1[5] = 64'h7890123456789012;
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assign smallvector1[5] = 64'h7890123456789012;
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assign smallvector1[6] = 64'h3456789012345678;
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assign smallvector1[6] = 64'h3456789012345678;
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assign smallvector1[7] = 64'h9012345678901234;
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assign smallvector1[7] = 64'h9012345678901234;
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assign smallvector1[8] = 64'h5678901234567890;
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assign smallvector1[8] = 64'h5678901234567890;
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assign smallvector1[9] = 64'h1234567855555555;
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assign smallvector1[9] = 64'h1234567855555555;
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assign smallvector1[10] = 64'hfd07070707070707;
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assign smallvector1[10] = 64'hfd07070707070707;
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assign smallvector2[0] = 8'hff;
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assign smallvector2[0] = 8'hff;
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assign smallvector2[1] = 8'h80;
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assign smallvector2[1] = 8'h80;
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assign smallvector2[2] = 8'h00;
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assign smallvector2[2] = 8'h00;
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assign smallvector2[3] = 8'h00;
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assign smallvector2[3] = 8'h00;
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assign smallvector2[4] = 8'h00;
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assign smallvector2[4] = 8'h00;
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assign smallvector2[5] = 8'h00;
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assign smallvector2[5] = 8'h00;
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assign smallvector2[6] = 8'h00;
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assign smallvector2[6] = 8'h00;
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assign smallvector2[7] = 8'h00;
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assign smallvector2[7] = 8'h00;
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assign smallvector2[8] = 8'h00;
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assign smallvector2[8] = 8'h00;
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assign smallvector2[9] = 8'h00;
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assign smallvector2[9] = 8'h00;
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assign smallvector2[10] = 8'hff;
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assign smallvector2[10] = 8'hff;
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assign taggedvector1[0] = 64'h0707070707070707;
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assign taggedvector1[0] = 64'h0707070707070707;
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assign taggedvector1[1] = 64'hfbaaaaaaaaaaaaab;
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assign taggedvector1[1] = 64'hfbaaaaaaaaaaaaab;
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assign taggedvector1[2] = 64'h00c09fe229720015;
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assign taggedvector1[2] = 64'h00c09fe229720015;
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assign taggedvector1[3] = 64'h0024ac348100004f; // assign taggedvector1[3] = 64'h0024ac3400639889; //length error frame
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assign taggedvector1[3] = 64'h0024ac348100004f; // assign taggedvector1[3] = 64'h0024ac3400639889; //length error frame
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assign taggedvector1[4] = 64'h004f123456789012;
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assign taggedvector1[4] = 64'h004f123456789012;
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assign taggedvector1[5] = 64'h3456789012345678;
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assign taggedvector1[5] = 64'h3456789012345678;
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assign taggedvector1[6] = 64'h9012345678901234;
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assign taggedvector1[6] = 64'h9012345678901234;
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assign taggedvector1[7] = 64'h5678901234567890;
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assign taggedvector1[7] = 64'h5678901234567890;
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assign taggedvector1[8] = 64'h1234567890123456;
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assign taggedvector1[8] = 64'h1234567890123456;
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assign taggedvector1[9] = 64'h7890123456789012;
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assign taggedvector1[9] = 64'h7890123456789012;
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assign taggedvector1[10] = 64'h7890123456789012;
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assign taggedvector1[10] = 64'h7890123456789012;
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assign taggedvector1[11] = 64'h3456789012345678;
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assign taggedvector1[11] = 64'h3456789012345678;
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assign taggedvector1[12] = 64'h9012345678901234;
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assign taggedvector1[12] = 64'h9012345678901234;
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assign taggedvector1[13] = 64'h5678901234567890;
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assign taggedvector1[13] = 64'h5678901234567890;
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assign taggedvector1[14] = 64'h1255555555fd0707;
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assign taggedvector1[14] = 64'h1255555555fd0707;
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assign taggedvector1[15] = 64'h0707070707070707;
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assign taggedvector1[15] = 64'h0707070707070707;
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assign taggedvector2[0] = 8'hff;
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assign taggedvector2[0] = 8'hff;
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assign taggedvector2[1] = 8'h80;
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assign taggedvector2[1] = 8'h80;
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assign taggedvector2[2] = 8'h00;
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assign taggedvector2[2] = 8'h00;
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assign taggedvector2[3] = 8'h00;
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assign taggedvector2[3] = 8'h00;
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assign taggedvector2[4] = 8'h00;
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assign taggedvector2[4] = 8'h00;
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assign taggedvector2[5] = 8'h00;
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assign taggedvector2[5] = 8'h00;
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assign taggedvector2[6] = 8'h00;
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assign taggedvector2[6] = 8'h00;
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assign taggedvector2[7] = 8'h00;
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assign taggedvector2[7] = 8'h00;
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assign taggedvector2[8] = 8'h00;
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assign taggedvector2[8] = 8'h00;
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assign taggedvector2[9] = 8'h00;
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assign taggedvector2[9] = 8'h00;
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assign taggedvector2[10] = 8'h00;
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assign taggedvector2[10] = 8'h00;
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assign taggedvector2[11] = 8'h00;
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assign taggedvector2[11] = 8'h00;
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assign taggedvector2[12] = 8'h00;
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assign taggedvector2[12] = 8'h00;
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assign taggedvector2[13] = 8'h00;
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assign taggedvector2[13] = 8'h00;
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assign taggedvector2[14] = 8'h07;
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assign taggedvector2[14] = 8'h07;
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assign taggedvector2[15] = 8'hff;
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assign taggedvector2[15] = 8'hff;
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initial begin
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initial begin
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reset_in = 1;
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reset_in = 1;
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#100
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#100
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reset_in = 0;
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reset_in = 0;
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end
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end
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always rxclk_in =#5 ~rxclk_in;
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always rxclk_in =#5 ~rxclk_in;
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reg [3:0]i;
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reg [3:0]i;
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always@(posedge rxclk_in or posedge reset_out) begin
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always@(posedge rxclk_in or posedge reset_out) begin
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if (reset_out) begin
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if (reset_out) begin
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i <= 0;
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i <= 0;
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rxd64 <=0;
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rxd64 <=0;
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rxc8 <=0;
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rxc8 <=0;
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end
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end
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else begin
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else begin
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i <= i+1;
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i <= i+1;
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rxd64 <=taggedvector1[i];
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rxd64 <=taggedvector1[i];
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rxc8 <=taggedvector2[i];
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rxc8 <=taggedvector2[i];
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// rxd64 <=testvector1[i];
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// rxd64 <=testvector1[i];
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// rxc8 <=testvector2[i];
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// rxc8 <=testvector2[i];
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// rxd64 <=smallvector1[i];
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// rxd64 <=smallvector1[i];
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// rxc8 <=smallvector2[i];
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// rxc8 <=smallvector2[i];
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end
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end
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end
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end
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endmodule
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endmodule
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