`include "TransmitTop.v"
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`include "TransmitTop.v"
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module TransmitTop_min_frame_tb();
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module TransmitTop_min_frame_tb();
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//Input from user logic
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//Input from user logic
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reg [63:0] TX_DATA;
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reg [63:0] TX_DATA;
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reg [63:0] TX_DATA_int;
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reg [63:0] TX_DATA_int;
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reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
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reg [7:0] TX_DATA_VALID; // To accept the data valid to be available
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reg Append_last_bit;
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reg Append_last_bit;
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reg TX_CLK;
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reg TX_CLK;
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reg RESET;
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reg RESET;
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reg TX_START; // This signify the first frame of data
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reg TX_START; // This signify the first frame of data
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reg TX_UNDERRUN; // this will cause an error to be injected into the data
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reg TX_UNDERRUN; // this will cause an error to be injected into the data
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reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
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reg [7:0] TX_IFG_DELAY; // this will cause a delay in the ack signal
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//input to transmit fault signals
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//input to transmit fault signals
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reg RXTXLINKFAULT;
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reg RXTXLINKFAULT;
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reg LOCALLINKFAULT;
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reg LOCALLINKFAULT;
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reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
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reg [15:0] FC_TRANS_PAUSEDATA; //pause frame data
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reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
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reg FC_TRANS_PAUSEVAL; //pulse signal to indicate a pause frame to be sent
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//apply pause timing
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//apply pause timing
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reg [15:0] FC_TX_PAUSEDATA;
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reg [15:0] FC_TX_PAUSEDATA;
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reg FC_TX_PAUSEVALID;
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reg FC_TX_PAUSEVALID;
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//apply configuration value
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//apply configuration value
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reg [31:0] TX_CFG_REG_VALUE;
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reg [31:0] TX_CFG_REG_VALUE;
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reg TX_CFG_REG_VALID;
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reg TX_CFG_REG_VALID;
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//output to stat register
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//output to stat register
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wire TX_STATS_VALID;
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wire TX_STATS_VALID;
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wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
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wire [9:0] TXSTATREGPLUS; // a pulse for each reg for stats
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wire [63:0] TXD;
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wire [63:0] TXD;
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wire [7:0] TXC;
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wire [7:0] TXC;
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wire TX_ACK;
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wire TX_ACK;
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reg D_START;
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reg D_START;
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reg START_TX_BITS;
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reg START_TX_BITS;
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// Initialize all variables
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// Initialize all variables
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initial begin
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initial begin
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Append_last_bit = 0;
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Append_last_bit = 0;
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TX_CLK = 1; // initial value of clock
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TX_CLK = 1; // initial value of clock
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RESET <= 0; // initial value of reset
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RESET <= 0; // initial value of reset
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TX_START <= 0; // initial value of enable
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TX_START <= 0; // initial value of enable
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TX_DATA_VALID <= 8'h00;
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TX_DATA_VALID <= 8'h00;
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D_START = 0;
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D_START = 0;
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FC_TX_PAUSEVALID <= 0;
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FC_TX_PAUSEVALID <= 0;
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FC_TX_PAUSEDATA <= 0;
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FC_TX_PAUSEDATA <= 0;
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FC_TRANS_PAUSEDATA <= 0;
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FC_TRANS_PAUSEDATA <= 0;
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FC_TRANS_PAUSEVAL <= 0;
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FC_TRANS_PAUSEVAL <= 0;
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TX_UNDERRUN = 0;
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TX_UNDERRUN = 0;
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#5 RESET= 1; // Assert the reset
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#5 RESET= 1; // Assert the reset
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#10 RESET= 0; // De-assert the reset
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#10 RESET= 0; // De-assert the reset
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#15 TX_START = 1;
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#15 TX_START = 1;
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// TX_DATA = 64'h0000560000000000;
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// TX_DATA = 64'h0000560000000000;
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TX_DATA_VALID = 8'hFF;
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TX_DATA_VALID = 8'hFF;
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D_START = 1;
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D_START = 1;
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#20 TX_START = 0;
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#20 TX_START = 0;
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//#1800 TX_DATA_VALID = 8'h07;
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//#1800 TX_DATA_VALID = 8'h07;
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#60 TX_DATA_VALID = 8'h07;
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#60 TX_DATA_VALID = 8'h07;
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// #1960 TX_DATA_VALID = 8'h07;
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// #1960 TX_DATA_VALID = 8'h07;
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// TX_DATA = 64'h0000000000000011;
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// TX_DATA = 64'h0000000000000011;
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#10 TX_DATA_VALID = 8'h00;
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#10 TX_DATA_VALID = 8'h00;
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D_START = 0;
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D_START = 0;
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//next frame
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//next frame
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#20 TX_START <= 1;
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#20 TX_START <= 1;
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TX_DATA_VALID <= 8'hFF;
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TX_DATA_VALID <= 8'hFF;
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D_START = 1;
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D_START = 1;
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#20 TX_START <= 0;
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#20 TX_START <= 0;
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#400 TX_DATA_VALID <= 8'h00;
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#400 TX_DATA_VALID <= 8'h00;
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#10 TX_DATA_VALID <= 8'h00;
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#10 TX_DATA_VALID <= 8'h00;
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D_START = 0;
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D_START = 0;
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#1000 $finish; // Terminate simulation
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#1000 $finish; // Terminate simulation
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end
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end
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always @(posedge D_START or posedge TX_CLK)
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always @(posedge D_START or posedge TX_CLK)
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begin
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begin
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if (D_START == 0) begin
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if (D_START == 0) begin
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TX_DATA = 64'h0000000000000000;
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TX_DATA = 64'h0000000000000000;
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end
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end
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//else if (TX_DATA_VALID == 8'h07) begin
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//else if (TX_DATA_VALID == 8'h07) begin
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// TX_DATA = 64'h000000000077FFCC;
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// TX_DATA = 64'h000000000077FFCC;
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//end
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//end
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else if (Append_last_bit == 1) begin
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else if (Append_last_bit == 1) begin
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// TX_DATA = 64'h202020202077FFCC;
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// TX_DATA = 64'h202020202077FFCC;
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TX_DATA = 64'h000000000077FFCC;
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TX_DATA = 64'h000000000077FFCC;
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end
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end
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else if (START_TX_BITS == 1) begin
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else if (START_TX_BITS == 1) begin
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TX_DATA = TX_DATA + 1;
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TX_DATA = TX_DATA + 1;
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end
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end
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else begin
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else begin
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TX_DATA = 64'h0000000000000001;
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TX_DATA = 64'h0000000000000001;
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end
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end
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end
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end
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always @(TX_DATA)
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always @(TX_DATA)
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begin
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begin
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if (TX_DATA == 2) begin
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if (TX_DATA == 2) begin
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TX_DATA_int[31:0] <= TX_DATA[31:0];
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TX_DATA_int[31:0] <= TX_DATA[31:0];
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TX_DATA_int[47:32] <= 300;
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TX_DATA_int[47:32] <= 300;
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TX_DATA_int[63:48] <= TX_DATA[63:48];
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TX_DATA_int[63:48] <= TX_DATA[63:48];
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end
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end
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else begin
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else begin
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TX_DATA_int <= TX_DATA;
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TX_DATA_int <= TX_DATA;
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end
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end
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end
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end
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always @(TX_ACK | TX_START)
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always @(TX_ACK | TX_START)
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begin
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begin
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if (TX_ACK) begin
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if (TX_ACK) begin
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START_TX_BITS = 1;
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START_TX_BITS = 1;
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end
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end
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else if (TX_START) begin
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else if (TX_START) begin
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START_TX_BITS = 0;
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START_TX_BITS = 0;
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end
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end
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end
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end
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// Clock generator
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// Clock generator
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always begin
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always begin
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#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
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#5 TX_CLK= ~TX_CLK; // Toggle clock every 5 ticks
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end
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end
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// Connect DUT to test bench
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// Connect DUT to test bench
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TRANSMIT_TOP U_top_module (
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TRANSMIT_TOP U_top_module (
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TX_DATA_int,
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TX_DATA_int,
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TX_DATA_VALID,
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TX_DATA_VALID,
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TX_CLK,
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TX_CLK,
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RESET,
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RESET,
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TX_START,
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TX_START,
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TX_ACK,
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TX_ACK,
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TX_UNDERRUN,
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TX_UNDERRUN,
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TX_IFG_DELAY,
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TX_IFG_DELAY,
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RXTXLINKFAULT,
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RXTXLINKFAULT,
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LOCALLINKFAULT,
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LOCALLINKFAULT,
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TX_STATS_VALID,
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TX_STATS_VALID,
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TXSTATREGPLUS,
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TXSTATREGPLUS,
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TXD,
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TXD,
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TXC,
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TXC,
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FC_TRANS_PAUSEDATA,
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FC_TRANS_PAUSEDATA,
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FC_TRANS_PAUSEVAL,
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FC_TRANS_PAUSEVAL,
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FC_TX_PAUSEDATA,
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FC_TX_PAUSEDATA,
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FC_TX_PAUSEVALID,
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FC_TX_PAUSEVALID,
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TX_CFG_REG_VALUE,
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TX_CFG_REG_VALUE,
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TX_CFG_REG_VALID
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TX_CFG_REG_VALID
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);
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);
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