`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// MODULE NAME: testbech for management module ////
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//// MODULE NAME: testbech for management module ////
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//// ////
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//// ////
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//// DESCRIPTION: Test Read & Write Internal Registers. Test MDIO ////
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//// DESCRIPTION: Test Read & Write Internal Registers. Test MDIO ////
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//// signals, including Read & Write ////
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//// signals, including Read & Write ////
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//// ////
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//// ////
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//// This file is part of the 10 Gigabit Ethernet IP core project ////
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//// This file is part of the 10 Gigabit Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac10g/ ////
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//// http://www.opencores.org/projects/ethmac10g/ ////
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//// ////
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//// ////
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//// AUTHOR(S): ////
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//// AUTHOR(S): ////
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//// Zheng Cao ////
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//// Zheng Cao ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
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//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS REVISION HISTORY:
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// CVS REVISION HISTORY:
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2006/06/06 05:09:46 fisher5090
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// Revision 1.1 2006/06/06 05:09:46 fisher5090
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// no message
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// no message
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//
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//
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// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
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// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
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//
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//
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//
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//
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//
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//
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module manage_tst_v;
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module manage_tst_v;
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// Inputs
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// Inputs
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reg mgmt_clk;
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reg mgmt_clk;
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reg rxclk;
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reg rxclk;
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reg txclk;
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reg txclk;
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reg [1:0] mgmt_opcode;
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reg [1:0] mgmt_opcode;
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reg [9:0] mgmt_addr;
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reg [9:0] mgmt_addr;
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reg [31:0] mgmt_wr_data;
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reg [31:0] mgmt_wr_data;
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reg mgmt_miim_sel;
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reg mgmt_miim_sel;
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reg mgmt_req;
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reg mgmt_req;
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reg [18:0] rxStatRegPlus;
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reg [18:0] rxStatRegPlus;
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reg [14:0] txStatRegPlus;
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reg [14:0] txStatRegPlus;
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reg reset;
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reg reset;
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// Outputs
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// Outputs
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wire [31:0] mgmt_rd_data;
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wire [31:0] mgmt_rd_data;
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wire mgmt_miim_rdy;
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wire mgmt_miim_rdy;
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wire [52:0] cfgRxRegData;
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wire [52:0] cfgRxRegData;
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wire [9:0] cfgTxRegData;
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wire [9:0] cfgTxRegData;
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wire mdc;
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wire mdc;
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wire mdio;
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wire mdio;
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// Management configuration register address (0x340)
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// Management configuration register address (0x340)
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reg [8:0] CONFIG_MANAGEMENT_ADD;
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reg [8:0] CONFIG_MANAGEMENT_ADD;
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// Flow control configuration register address (0x2C0)
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// Flow control configuration register address (0x2C0)
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reg [8:0] CONFIG_FLOW_CTRL_ADD;
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reg [8:0] CONFIG_FLOW_CTRL_ADD;
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// Reconciliation sublayer configuration register address (0x300)
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// Reconciliation sublayer configuration register address (0x300)
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reg [8:0] CONFIG_RECONCILIATION_ADD;
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reg [8:0] CONFIG_RECONCILIATION_ADD;
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// Receiver configuration register address (0x200)
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// Receiver configuration register address (0x200)
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reg [8:0] RECEIVER_ADD0;
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reg [8:0] RECEIVER_ADD0;
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// Receiver configuration register address (0x240)
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// Receiver configuration register address (0x240)
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reg [8:0] RECEIVER_ADD1;
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reg [8:0] RECEIVER_ADD1;
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// Transmitter configuration register address (0x280)
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// Transmitter configuration register address (0x280)
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reg [8:0] TRANSMITTER_ADD;
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reg [8:0] TRANSMITTER_ADD;
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// Set up constants values....
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// Set up constants values....
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initial
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initial
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begin
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begin
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// Management configuration register address (0x340)
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// Management configuration register address (0x340)
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CONFIG_MANAGEMENT_ADD = 9'b101000000;
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CONFIG_MANAGEMENT_ADD = 9'b101000000;
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// Reconciliation sublayer configuration register address (0x300)
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// Reconciliation sublayer configuration register address (0x300)
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CONFIG_RECONCILIATION_ADD = 9'b100000000;
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CONFIG_RECONCILIATION_ADD = 9'b100000000;
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// Flow control configuration register address (0x2C0)
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// Flow control configuration register address (0x2C0)
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CONFIG_FLOW_CTRL_ADD = 9'b011000000;
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CONFIG_FLOW_CTRL_ADD = 9'b011000000;
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// Receiver configuration register address (0x200)
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// Receiver configuration register address (0x200)
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RECEIVER_ADD0 = 9'b000000000;
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RECEIVER_ADD0 = 9'b000000000;
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// Receiver configuration register address (0x240)
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// Receiver configuration register address (0x240)
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RECEIVER_ADD1 = 9'b001000000;
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RECEIVER_ADD1 = 9'b001000000;
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// Transmitter configuration register address (0x280)
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// Transmitter configuration register address (0x280)
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TRANSMITTER_ADD = 9'b010000000;
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TRANSMITTER_ADD = 9'b010000000;
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end
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end
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management_top uut (
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management_top uut (
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.mgmt_clk(mgmt_clk),
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.mgmt_clk(mgmt_clk),
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.rxclk(rxclk),
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.rxclk(rxclk),
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.txclk(txclk),
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.txclk(txclk),
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.mgmt_opcode(mgmt_opcode),
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.mgmt_opcode(mgmt_opcode),
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.mgmt_addr(mgmt_addr),
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.mgmt_addr(mgmt_addr),
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.mgmt_wr_data(mgmt_wr_data),
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.mgmt_wr_data(mgmt_wr_data),
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.mgmt_rd_data(mgmt_rd_data),
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.mgmt_rd_data(mgmt_rd_data),
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.mgmt_miim_sel(mgmt_miim_sel),
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.mgmt_miim_sel(mgmt_miim_sel),
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.mgmt_req(mgmt_req),
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.mgmt_req(mgmt_req),
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.mgmt_miim_rdy(mgmt_miim_rdy),
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.mgmt_miim_rdy(mgmt_miim_rdy),
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.rxStatRegPlus(rxStatRegPlus),
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.rxStatRegPlus(rxStatRegPlus),
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.txStatRegPlus(txStatRegPlus),
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.txStatRegPlus(txStatRegPlus),
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.cfgRxRegData(cfgRxRegData),
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.cfgRxRegData(cfgRxRegData),
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.cfgTxRegData(cfgTxRegData),
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.cfgTxRegData(cfgTxRegData),
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.mdc(mdc),
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.mdc(mdc),
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.mdio(mdio),
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.mdio(mdio),
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.reset(reset)
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.reset(reset)
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);
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);
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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rxclk = 0;
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rxclk = 0;
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txclk = 0;
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txclk = 0;
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rxStatRegPlus = 0;
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rxStatRegPlus = 0;
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txStatRegPlus = 0;
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txStatRegPlus = 0;
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reset = 1;
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reset = 1;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#100;
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#100;
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reset = 0;
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reset = 0;
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// Add stimulus here
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// Add stimulus here
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end
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end
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initial // drives mgmt_clk
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initial // drives mgmt_clk
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begin
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begin
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mgmt_clk <= 1'b0;
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mgmt_clk <= 1'b0;
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#2000;
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#2000;
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forever
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forever
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begin
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begin
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mgmt_clk <= 1'b0;
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mgmt_clk <= 1'b0;
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#12000;
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#12000;
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mgmt_clk <= 1'b1;
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mgmt_clk <= 1'b1;
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#12000;
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#12000;
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end
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end
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end
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end
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initial
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initial
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begin : p_management
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begin : p_management
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integer I;
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integer I;
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mgmt_req <= 1'b0;
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mgmt_req <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_opcode <= 2'b11;
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mgmt_opcode <= 2'b11;
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mgmt_addr <= 32'h0;
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mgmt_addr <= 32'h0;
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mgmt_wr_data <= 32'h0;
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mgmt_wr_data <= 32'h0;
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// reset the core
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// reset the core
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$display("** Note: Resetting core...");
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$display("** Note: Resetting core...");
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reset <= 1'b1;
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reset <= 1'b1;
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#210000
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#210000
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reset <= 1'b0;
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reset <= 1'b0;
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#500000
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#500000
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// set up MDC frequency. Write 2E to Management configuration
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// set up MDC frequency. Write 2E to Management configuration
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// (register Add=340). This will enable MDIO and set MDC to 2.3 MHz
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// (register Add=340). This will enable MDIO and set MDC to 2.3 MHz
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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$display("** Note: Setting MDC Frequency to 2.3MHZ....");
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$display("** Note: Setting MDC Frequency to 2.3MHZ....");
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// set CLOCK_DIVIDE value to 9 dec. for 41.66. MHz mgmt_CLK and enable MDIO
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// set CLOCK_DIVIDE value to 9 dec. for 41.66. MHz mgmt_CLK and enable MDIO
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[8:0] <= CONFIG_MANAGEMENT_ADD;
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mgmt_addr[8:0] <= CONFIG_MANAGEMENT_ADD;
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mgmt_miim_sel <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_opcode <= 2'b01;
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mgmt_opcode <= 2'b01;
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mgmt_wr_data <= 32'b00000000000000000000000000101001;
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mgmt_wr_data <= 32'b00000000000000000000000000101001;
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Reading Management Configuration Register (Add=340).
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// Reading Management Configuration Register (Add=340).
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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$display("** Note: Reading Management Configuration Register....");
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$display("** Note: Reading Management Configuration Register....");
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// Read from management configuration register
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// Read from management configuration register
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[8:0] <= CONFIG_MANAGEMENT_ADD;
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mgmt_addr[8:0] <= CONFIG_MANAGEMENT_ADD;
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mgmt_miim_sel <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_opcode <= 2'b11;
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mgmt_opcode <= 2'b11;
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Disable Flow Control. Set top 3 bits of the flow control
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// Disable Flow Control. Set top 3 bits of the flow control
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// configuration register (Add=2C0) to zero therefore disabling tx
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// configuration register (Add=2C0) to zero therefore disabling tx
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// and rx flow control.
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// and rx flow control.
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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$display("** Note: Disabling tx and rx flow control...");
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$display("** Note: Disabling tx and rx flow control...");
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// Turn off flow control by writing relevant bits into the register
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// Turn off flow control by writing relevant bits into the register
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[8:0] <= CONFIG_FLOW_CTRL_ADD;
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mgmt_addr[8:0] <= CONFIG_FLOW_CTRL_ADD;
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mgmt_miim_sel <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_opcode <= 2'b01;
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mgmt_opcode <= 2'b01;
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mgmt_wr_data <= 32'b00000000000000000000001100000000;
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mgmt_wr_data <= 32'b00000000000000000000001100000000;
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Reading Flow Control Configuration Register (Add=2C0).
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// Reading Flow Control Configuration Register (Add=2C0).
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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$display("** Note: Reading Flow Control Configuration Register....");
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$display("** Note: Reading Flow Control Configuration Register....");
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// Read from flow control register
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// Read from flow control register
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[8:0] <= CONFIG_RECONCILIATION_ADD;
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mgmt_addr[8:0] <= CONFIG_RECONCILIATION_ADD;
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mgmt_miim_sel <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_opcode <= 2'b11;
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mgmt_opcode <= 2'b11;
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// Read from statistics register 0
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// Read from statistics register 0
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_req <= 1'b1;
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mgmt_req <= 1'b1;
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mgmt_addr[9] <= 1'b0;
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mgmt_addr[9] <= 1'b0;
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mgmt_addr[8:0] <= 0;
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mgmt_addr[8:0] <= 0;
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mgmt_miim_sel <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_opcode <= 2'b11;
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mgmt_opcode <= 2'b11;
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|
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_req <= 1'b0;
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mgmt_req <= 1'b0;
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mgmt_addr[9] <= 1'b0;
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mgmt_addr[9] <= 1'b0;
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mgmt_addr[8:0] <= 1;
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mgmt_addr[8:0] <= 1;
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mgmt_miim_sel <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_opcode <= 2'b11;
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mgmt_opcode <= 2'b11;
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// Read from statistics register 1
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// Read from statistics register 1
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_req <= 1'b1;
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mgmt_req <= 1'b1;
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mgmt_addr[9] <= 1'b0;
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mgmt_addr[9] <= 1'b0;
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mgmt_addr[8:0] <= 1;
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mgmt_addr[8:0] <= 1;
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mgmt_miim_sel <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_opcode <= 2'b11;
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mgmt_opcode <= 2'b11;
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|
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_req <= 1'b0;
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mgmt_req <= 1'b0;
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mgmt_addr[9] <= 1'b0;
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mgmt_addr[9] <= 1'b0;
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mgmt_addr[8:0] <= 1;
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mgmt_addr[8:0] <= 1;
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mgmt_miim_sel <= 1'b0;
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mgmt_miim_sel <= 1'b0;
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mgmt_opcode <= 2'b11;
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mgmt_opcode <= 2'b11;
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|
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// MDIO WRITE
|
// MDIO WRITE
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_req <= 1'b1;
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mgmt_req <= 1'b1;
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[9] <= 1'b1;
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mgmt_addr[8:0] <= CONFIG_FLOW_CTRL_ADD;
|
mgmt_addr[8:0] <= CONFIG_FLOW_CTRL_ADD;
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mgmt_miim_sel <= 1'b1;
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mgmt_miim_sel <= 1'b1;
|
mgmt_opcode <= 2'b01;
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mgmt_opcode <= 2'b01;
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mgmt_wr_data <= 32'b00000000000000000000001100110000;
|
mgmt_wr_data <= 32'b00000000000000000000001100110000;
|
#50000
|
#50000
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@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_req <= 1'b0;
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mgmt_req <= 1'b0;
|
wait (mgmt_miim_rdy ==1'b1);
|
wait (mgmt_miim_rdy ==1'b1);
|
#50000
|
#50000
|
|
|
// MDIO READ
|
// MDIO READ
|
@(negedge mgmt_clk)
|
@(negedge mgmt_clk)
|
mgmt_req <= 1'b1;
|
mgmt_req <= 1'b1;
|
mgmt_addr[9] <= 1'b1;
|
mgmt_addr[9] <= 1'b1;
|
mgmt_addr[8:0] <= CONFIG_FLOW_CTRL_ADD;
|
mgmt_addr[8:0] <= CONFIG_FLOW_CTRL_ADD;
|
mgmt_miim_sel <= 1'b1;
|
mgmt_miim_sel <= 1'b1;
|
mgmt_opcode <= 2'b10;
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mgmt_opcode <= 2'b10;
|
mgmt_wr_data <= 32'b00000000000000000000001100110000;
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mgmt_wr_data <= 32'b00000000000000000000001100110000;
|
|
|
@(negedge mgmt_clk)
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@(negedge mgmt_clk)
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mgmt_req <= 1'b0;
|
mgmt_req <= 1'b0;
|
|
|
#100000
|
#100000
|
// test process here is done
|
// test process here is done
|
$display("** failure: Simulation Stopped");
|
$display("** failure: Simulation Stopped");
|
$stop;
|
$stop;
|
|
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
