//
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//
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// Module SwitchSyncFIFO
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// Module SwitchSyncFIFO
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//
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//
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// the differences between this FIFO and the general one are listed below
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// the differences between this FIFO and the general one are listed below
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// 1. because there is no any write and read acknowledgements, the user should take advantage of the status flags to generate the write and read requests.
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// 1. because there is no any write and read acknowledgements, the user should take advantage of the status flags to generate the write and read requests.
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// 2. after the full flag has been asserted, the word can not be written into the FIFO even if the reacd request is being asserted at the same cycle.
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// 2. after the full flag has been asserted, the word can not be written into the FIFO even if the reacd request is being asserted at the same cycle.
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//
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//
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// Created:
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// Created:
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// by - Xinchun Liu
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// by - Xinchun Liu
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// at - 2006-09-25
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// at - 2006-09-25
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// History:
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// History:
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// 2007-1-31 9:50 change iReset to nReset Revised By Wang Dawei wangdawei@ncic.ac.cn
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// 2007-1-31 9:50 change iReset to nReset Revised By Wang Dawei wangdawei@ncic.ac.cn
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//
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//
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`resetall
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`resetall
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module SwitchSyncFIFO (
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module SwitchSyncFIFO (
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nReset,
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nReset,
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iClk,
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iClk,
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iWEn,
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iWEn,
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ivDataIn,
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ivDataIn,
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iREn,
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iREn,
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ovDataOut,
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ovDataOut,
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qEmpty,
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qEmpty,
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qFull,
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qFull,
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qvCount
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qvCount
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);
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);
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// Default address and data width
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// Default address and data width
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parameter pDepthWidth = 5 ;
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parameter pDepthWidth = 5 ;
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parameter pWordWidth = 16 ;
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parameter pWordWidth = 16 ;
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input nReset ;
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input nReset ;
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input iClk ;
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input iClk ;
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input iWEn ;
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input iWEn ;
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input [pWordWidth-1:0] ivDataIn ;
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input [pWordWidth-1:0] ivDataIn ;
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input iREn ;
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input iREn ;
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output [pWordWidth-1:0] ovDataOut ;
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output [pWordWidth-1:0] ovDataOut ;
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output qEmpty ;
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output qEmpty ;
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output qFull ;
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output qFull ;
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output [pDepthWidth:0] qvCount ;
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output [pDepthWidth:0] qvCount ;
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wire nReset ;
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wire nReset ;
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wire iClk ;
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wire iClk ;
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wire iWEn ;
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wire iWEn ;
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wire [pWordWidth-1:0] ivDataIn ;
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wire [pWordWidth-1:0] ivDataIn ;
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wire iREn ;
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wire iREn ;
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wire [pWordWidth-1:0] ovDataOut_i ;
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wire [pWordWidth-1:0] ovDataOut_i ;
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wire qEmpty ;
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wire qEmpty ;
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wire qFull ;
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wire qFull ;
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wire [pDepthWidth:0] qvCount ;
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wire [pDepthWidth:0] qvCount ;
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wire MemWEn;
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wire MemWEn;
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wire MemREn;
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wire MemREn;
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wire [pDepthWidth-1:0] vWriteAddr ;
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wire [pDepthWidth-1:0] vWriteAddr ;
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wire [pDepthWidth-1:0] vReadAddr ;
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wire [pDepthWidth-1:0] vReadAddr ;
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DualPortRAM #( pDepthWidth, pWordWidth ) Fifo_Storage // Generic synchronous two-port RAM interface
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DualPortRAM #( pDepthWidth, pWordWidth ) Fifo_Storage // Generic synchronous two-port RAM interface
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(
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(
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.clock ( iClk ) ,
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.clock ( iClk ) ,
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.MemWEn ( MemWEn ) ,
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.MemWEn ( MemWEn ) ,
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.qvWAddr ( vWriteAddr ) ,
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.qvWAddr ( vWriteAddr ) ,
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.vDataIn ( ivDataIn ) ,
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.vDataIn ( ivDataIn ) ,
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.qvRAddr ( vReadAddr ) ,
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.qvRAddr ( vReadAddr ) ,
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.vDataOut ( ovDataOut_i )
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.vDataOut ( ovDataOut_i )
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);
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);
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reg [pWordWidth-1:0] ovDataOut ;
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reg [pWordWidth-1:0] ovDataOut ;
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always @ ( posedge iClk )
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always @ ( posedge iClk )
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if ( MemREn )
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if ( MemREn )
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ovDataOut <= ovDataOut_i ;
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ovDataOut <= ovDataOut_i ;
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else
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else
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ovDataOut <= 0;
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ovDataOut <= 0;
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FifoControl #( pDepthWidth ) Fifo_Ctrl
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FifoControl #( pDepthWidth ) Fifo_Ctrl
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(
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(
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.Reset ( nReset ) ,
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.Reset ( nReset ) ,
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.clock ( iClk ) ,
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.clock ( iClk ) ,
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.iWEn ( iWEn ) ,
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.iWEn ( iWEn ) ,
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.MemWEn ( MemWEn ) ,
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.MemWEn ( MemWEn ) ,
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.MemREn (MemREn),
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.MemREn (MemREn),
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.qvWAddr ( vWriteAddr ) ,
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.qvWAddr ( vWriteAddr ) ,
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.iREn ( iREn ) ,
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.iREn ( iREn ) ,
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.qvRAddr ( vReadAddr ) ,
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.qvRAddr ( vReadAddr ) ,
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.qEmpty ( qEmpty ) ,
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.qEmpty ( qEmpty ) ,
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.qFull ( qFull ) ,
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.qFull ( qFull ) ,
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.qvCount ( qvCount )
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.qvCount ( qvCount )
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) ;
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) ;
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endmodule
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endmodule
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module FifoControl(
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module FifoControl(
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Reset ,
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Reset ,
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clock ,
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clock ,
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iWEn ,
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iWEn ,
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MemWEn ,
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MemWEn ,
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MemREn,
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MemREn,
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qvWAddr ,
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qvWAddr ,
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iREn ,
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iREn ,
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qvRAddr ,
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qvRAddr ,
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qEmpty ,
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qEmpty ,
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qFull ,
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qFull ,
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qvCount
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qvCount
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) ;
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) ;
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parameter pDepthWidth = 5;
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parameter pDepthWidth = 5;
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input Reset ;
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input Reset ;
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input clock ;
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input clock ;
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input iWEn ;
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input iWEn ;
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output MemWEn ;
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output MemWEn ;
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output MemREn ;
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output MemREn ;
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output [pDepthWidth-1:0] qvWAddr ;
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output [pDepthWidth-1:0] qvWAddr ;
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input iREn ;
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input iREn ;
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output [pDepthWidth-1:0] qvRAddr ;
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output [pDepthWidth-1:0] qvRAddr ;
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output qEmpty ;
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output qEmpty ;
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output qFull ;
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output qFull ;
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output [pDepthWidth:0] qvCount ;
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output [pDepthWidth:0] qvCount ;
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wire Reset ;
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wire Reset ;
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wire clock ;
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wire clock ;
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wire iWEn ;
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wire iWEn ;
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wire MemWEn ;
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wire MemWEn ;
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reg [pDepthWidth-1:0] qvWAddr ;
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reg [pDepthWidth-1:0] qvWAddr ;
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wire iREn ;
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wire iREn ;
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reg [pDepthWidth-1:0] qvRAddr ;
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reg [pDepthWidth-1:0] qvRAddr ;
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reg qEmpty ;
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reg qEmpty ;
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reg qFull ;
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reg qFull ;
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reg [pDepthWidth:0] qvCount ;
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reg [pDepthWidth:0] qvCount ;
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wire MemREn ;
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wire MemREn ;
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// write allow wire - writes are allowed when fifo is not full
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// write allow wire - writes are allowed when fifo is not full
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// read allow wire - reads are allowed when fifo is not empty
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// read allow wire - reads are allowed when fifo is not empty
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assign MemWEn = iWEn && ( ~qFull ) ;
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assign MemWEn = iWEn && ( ~qFull ) ;
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assign MemREn = iREn && ( ~qEmpty ) ;
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assign MemREn = iREn && ( ~qEmpty ) ;
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// write address module
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// write address module
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always @ ( posedge clock or negedge Reset) begin
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always @ ( posedge clock or negedge Reset) begin
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if( ~Reset ) begin
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if( ~Reset ) begin
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qvWAddr <= 0 ;
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qvWAddr <= 0 ;
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end
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end
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else begin
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else begin
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if( MemWEn ) qvWAddr <= qvWAddr + 1'b1 ;
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if( MemWEn ) qvWAddr <= qvWAddr + 1'b1 ;
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end
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end
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end
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end
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// read address module
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// read address module
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always @ ( posedge clock or negedge Reset) begin
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always @ ( posedge clock or negedge Reset) begin
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if( ~Reset ) begin
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if( ~Reset ) begin
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qvRAddr <= 0 ;
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qvRAddr <= 0 ;
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end
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end
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else begin
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else begin
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if( MemREn ) qvRAddr <= qvRAddr + 1'b1 ;
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if( MemREn ) qvRAddr <= qvRAddr + 1'b1 ;
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end
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end
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end
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end
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// flags module
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// flags module
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always @ ( posedge clock or negedge Reset) begin
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always @ ( posedge clock or negedge Reset) begin
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if( ~Reset ) begin
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if( ~Reset ) begin
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qFull <= 0 ;
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qFull <= 0 ;
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qEmpty <= 1 ;
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qEmpty <= 1 ;
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qvCount <= 0 ;
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qvCount <= 0 ;
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end
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end
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else begin
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else begin
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if( MemWEn ) begin
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if( MemWEn ) begin
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if( qEmpty ) qEmpty <= 0 ;
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if( qEmpty ) qEmpty <= 0 ;
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if ( ~MemREn ) begin
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if ( ~MemREn ) begin
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qvCount <= qvCount + 1'b1 ;
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qvCount <= qvCount + 1'b1 ;
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if( qvCount[pDepthWidth-1:0] == { pDepthWidth{1'b1} } )
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if( qvCount[pDepthWidth-1:0] == { pDepthWidth{1'b1} } )
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qFull <= 1 ;
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qFull <= 1 ;
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end
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end
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end
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end
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else begin
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else begin
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if( MemREn ) begin
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if( MemREn ) begin
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qvCount <= qvCount - 1'b1 ;
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qvCount <= qvCount - 1'b1 ;
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if( qvCount == 1'b1 ) qEmpty <= 1;
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if( qvCount == 1'b1 ) qEmpty <= 1;
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if( qFull ) qFull <= 0;
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if( qFull ) qFull <= 0;
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end
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end
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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//=============================================================================================================
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//=============================================================================================================
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module DualPortRAM
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module DualPortRAM
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(
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(
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clock ,
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clock ,
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MemWEn ,
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MemWEn ,
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qvWAddr ,
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qvWAddr ,
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vDataIn ,
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vDataIn ,
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qvRAddr ,
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qvRAddr ,
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vDataOut
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vDataOut
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);
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);
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// Default address and data width
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// Default address and data width
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parameter pDepthWidth = 5 ;
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parameter pDepthWidth = 5 ;
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parameter pWordWidth = 16 ;
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parameter pWordWidth = 16 ;
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|
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// Generic synchronous two-port RAM interface
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// Generic synchronous two-port RAM interface
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input clock ; // clock
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input clock ; // clock
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input MemWEn ; // write enable input
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input MemWEn ; // write enable input
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input [pDepthWidth-1:0] qvWAddr ; // write address bus
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input [pDepthWidth-1:0] qvWAddr ; // write address bus
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input [pWordWidth-1:0] vDataIn ; // input data bus
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input [pWordWidth-1:0] vDataIn ; // input data bus
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input [pDepthWidth-1:0] qvRAddr ; // read address bus
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input [pDepthWidth-1:0] qvRAddr ; // read address bus
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output [pWordWidth-1:0] vDataOut ; // output data bus
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output [pWordWidth-1:0] vDataOut ; // output data bus
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// Generic two-port synchronous RAM model
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// Generic two-port synchronous RAM model
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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reg [pWordWidth-1:0] mem[(1<<pDepthWidth)-1:0] /*synthesis syn_ramstyle="no_rw_check"*/;
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reg [pWordWidth-1:0] mem[(1<<pDepthWidth)-1:0] /*synthesis syn_ramstyle="no_rw_check"*/;
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always @ ( posedge clock )
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always @ ( posedge clock )
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if ( MemWEn )
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if ( MemWEn )
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mem[qvWAddr] <= vDataIn ;
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mem[qvWAddr] <= vDataIn ;
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assign vDataOut = mem[qvRAddr] ;
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assign vDataOut = mem[qvRAddr] ;
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endmodule
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endmodule
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///**********************************************************************
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///**********************************************************************
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// FIFO
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// FIFO
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