//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// MODULE NAME: rxRSIO ////
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//// MODULE NAME: rxRSIO ////
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//// ////
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//// ////
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//// DESCRIPTION: Datapath of Reconciliation Sublayer. ////
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//// DESCRIPTION: Datapath of Reconciliation Sublayer. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// This file is part of the 10 Gigabit Ethernet IP core project ////
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//// This file is part of the 10 Gigabit Ethernet IP core project ////
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//// http://www.opencores.org/projects/ethmac10g/ ////
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//// http://www.opencores.org/projects/ethmac10g/ ////
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//// ////
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//// ////
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//// AUTHOR(S): ////
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//// AUTHOR(S): ////
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//// Zheng Cao ////
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//// Zheng Cao ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
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//// Copyright (c) 2005 AUTHORS. All rights reserved. ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS REVISION HISTORY:
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// CVS REVISION HISTORY:
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2006/06/16 06:36:28 fisher5090
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// Revision 1.2 2006/06/16 06:36:28 fisher5090
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// no message
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// no message
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//
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//
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// Revision 1.1.1.1 2006/05/31 05:59:43 Zheng Cao
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// Revision 1.1.1.1 2006/05/31 05:59:43 Zheng Cao
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// first version
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// first version
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//
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//
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// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
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// Revision 1.1 2005/12/25 16:43:10 Zheng Cao
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//
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//
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//
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//
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//
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//
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "xgiga_define.v"
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`include "xgiga_define.v"
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module rxRSIO(rxclk, rxclk_180, rxclk_2x, reset, rxd_in, rxc_in, rxd64, rxc8, local_fault, remote_fault);
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module rxRSIO(rxclk, rxclk_180, rxclk_2x, reset, rxd_in, rxc_in, rxd64, rxc8, local_fault, remote_fault);
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input rxclk;
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input rxclk;
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input rxclk_180;
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input rxclk_180;
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input rxclk_2x;
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input rxclk_2x;
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input reset;
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input reset;
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input [31:0] rxd_in;
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input [31:0] rxd_in;
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input [3:0] rxc_in;
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input [3:0] rxc_in;
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output [63:0] rxd64;
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output [63:0] rxd64;
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output [7:0] rxc8;
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output [7:0] rxc8;
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output local_fault;
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output local_fault;
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output remote_fault;
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output remote_fault;
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parameter TP =1;
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parameter TP =1;
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reg local_fault, remote_fault;
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reg local_fault, remote_fault;
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// wire get_align, get_seq;
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// wire get_align, get_seq;
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always@(posedge rxclk or posedge reset) begin
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always@(posedge rxclk or posedge reset) begin
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if(reset) begin
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if(reset) begin
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local_fault <=#TP 0;
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local_fault <=#TP 0;
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remote_fault <=#TP 0;
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remote_fault <=#TP 0;
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end
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end
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else begin
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else begin
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local_fault <=#TP (rxd_in[7:0] == `SEQUENCE) & (rxd_in[29:8] == 0) & (rxc_in[3:0]== 4'h8) & ~rxd_in[30] & rxd_in[31];
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local_fault <=#TP (rxd_in[7:0] == `SEQUENCE) & (rxd_in[29:8] == 0) & (rxc_in[3:0]== 4'h8) & ~rxd_in[30] & rxd_in[31];
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remote_fault<=#TP (rxd_in[7:0] == `SEQUENCE) & (rxd_in[29:8] == 0) & (rxc_in[3:0]== 4'h8) & rxd_in[30] & rxd_in[31];
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remote_fault<=#TP (rxd_in[7:0] == `SEQUENCE) & (rxd_in[29:8] == 0) & (rxc_in[3:0]== 4'h8) & rxd_in[30] & rxd_in[31];
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end
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end
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end
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end
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// assign get_align = ((rxd_in[7:0]==`START) & rxc_in[0]);
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// assign get_align = ((rxd_in[7:0]==`START) & rxc_in[0]);
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// assign get_seq = (rxd_in[7:0] == `SEQUENCE) & (rxd_in[29:8] == 0) & (rxc_in[3:0]== 4'h8) & rxd_in[31];
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// assign get_seq = (rxd_in[7:0] == `SEQUENCE) & (rxd_in[29:8] == 0) & (rxc_in[3:0]== 4'h8) & rxd_in[31];
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// assign local_fault = get_seq & ~rxd_in[30];
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// assign local_fault = get_seq & ~rxd_in[30];
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// assign remote_fault = get_seq & rxd_in[30];
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// assign remote_fault = get_seq & rxd_in[30];
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reg[7:0] rxc8_in_tmp;
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reg[7:0] rxc8_in_tmp;
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reg[63:0]rxd64_in_tmp;
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reg[63:0]rxd64_in_tmp;
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reg[3:0] rxc4_in_tmp;
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reg[3:0] rxc4_in_tmp;
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reg[31:0]rxd32_in_tmp;
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reg[31:0]rxd32_in_tmp;
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reg[31:0]rxd32_in_tmp_d1;
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reg[31:0]rxd32_in_tmp_d1;
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reg[3:0] rxc4_in_tmp_d1;
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reg[3:0] rxc4_in_tmp_d1;
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always@(posedge rxclk_2x or posedge reset) begin
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always@(posedge rxclk_2x or posedge reset) begin
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if (reset) begin
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if (reset) begin
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rxc4_in_tmp <= #TP 0;
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rxc4_in_tmp <= #TP 0;
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rxd32_in_tmp <= #TP 0;
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rxd32_in_tmp <= #TP 0;
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rxc4_in_tmp_d1 <= #TP 0;
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rxc4_in_tmp_d1 <= #TP 0;
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rxd32_in_tmp_d1 <= #TP 0;
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rxd32_in_tmp_d1 <= #TP 0;
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end
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end
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else begin
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else begin
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rxc4_in_tmp <= #TP rxc_in;
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rxc4_in_tmp <= #TP rxc_in;
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rxd32_in_tmp <= #TP rxd_in;
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rxd32_in_tmp <= #TP rxd_in;
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rxc4_in_tmp_d1 <= #TP rxc4_in_tmp;
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rxc4_in_tmp_d1 <= #TP rxc4_in_tmp;
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rxd32_in_tmp_d1 <= #TP rxd32_in_tmp;
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rxd32_in_tmp_d1 <= #TP rxd32_in_tmp;
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end
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end
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end
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end
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reg get_align_reg;
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reg get_align_reg;
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always@(posedge rxclk_2x or posedge reset) begin
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always@(posedge rxclk_2x or posedge reset) begin
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if (reset)
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if (reset)
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get_align_reg <=#TP 0;
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get_align_reg <=#TP 0;
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else if((rxd32_in_tmp[7:0]==`START) & rxc4_in_tmp[0])
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else if((rxd32_in_tmp[7:0]==`START) & rxc4_in_tmp[0])
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get_align_reg <=#TP 1'b1;
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get_align_reg <=#TP 1'b1;
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else if((&rxc4_in_tmp)&(rxd32_in_tmp==32'h07070707))
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else if((&rxc4_in_tmp)&(rxd32_in_tmp==32'h07070707))
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get_align_reg <=#TP 1'b0;
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get_align_reg <=#TP 1'b0;
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end
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end
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reg [1:0] qvWriteCntrl;
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reg [1:0] qvWriteCntrl;
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always@(posedge rxclk_2x or posedge reset) begin
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always@(posedge rxclk_2x or posedge reset) begin
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if (reset)
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if (reset)
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qvWriteCntrl <= 2'b01;
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qvWriteCntrl <= 2'b01;
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else if(get_align_reg) begin
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else if(get_align_reg) begin
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qvWriteCntrl[1] <= qvWriteCntrl[0];
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qvWriteCntrl[1] <= qvWriteCntrl[0];
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qvWriteCntrl[0] <= qvWriteCntrl[1];
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qvWriteCntrl[0] <= qvWriteCntrl[1];
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end
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end
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else
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else
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qvWriteCntrl <= 2'b01;
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qvWriteCntrl <= 2'b01;
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end
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end
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always@(posedge rxclk_2x or posedge reset) begin
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always@(posedge rxclk_2x or posedge reset) begin
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if (reset)begin
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if (reset)begin
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rxd64_in_tmp <= #TP 0;
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rxd64_in_tmp <= #TP 0;
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rxc8_in_tmp <= #TP 0;
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rxc8_in_tmp <= #TP 0;
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end
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end
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else if(qvWriteCntrl[1]) begin
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else if(qvWriteCntrl[1]) begin
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rxd64_in_tmp[63:32] <= #TP rxd32_in_tmp_d1;
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rxd64_in_tmp[63:32] <= #TP rxd32_in_tmp_d1;
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rxc8_in_tmp[7:4] <= #TP rxc4_in_tmp_d1;
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rxc8_in_tmp[7:4] <= #TP rxc4_in_tmp_d1;
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end
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end
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else begin
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else begin
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rxd64_in_tmp[31:0] <= #TP rxd32_in_tmp_d1;
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rxd64_in_tmp[31:0] <= #TP rxd32_in_tmp_d1;
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rxc8_in_tmp[3:0] <= #TP rxc4_in_tmp_d1;
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rxc8_in_tmp[3:0] <= #TP rxc4_in_tmp_d1;
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end
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end
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end
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end
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wire [71:0] rxdata;
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wire [71:0] rxdata;
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assign rxd64 = rxdata[63:0];
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assign rxd64 = rxdata[63:0];
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assign rxc8 = rxdata[71:64];
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assign rxc8 = rxdata[71:64];
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defparam RealignInst.pDepthWidth = 5;
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defparam RealignInst.pDepthWidth = 5;
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defparam RealignInst.pWordWidth = 72;
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defparam RealignInst.pWordWidth = 72;
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SwitchAsyncFIFO RealignInst(
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SwitchAsyncFIFO RealignInst(
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.inReset(!reset),
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.inReset(!reset),
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.iWClk(rxclk_2x),
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.iWClk(rxclk_2x),
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.iWEn(qvWriteCntrl[0]),
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.iWEn(qvWriteCntrl[0]),
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.ivDataIn({rxc8_in_tmp,rxd64_in_tmp}),
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.ivDataIn({rxc8_in_tmp,rxd64_in_tmp}),
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.qWFull(),
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.qWFull(),
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.qvWCount(),
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.qvWCount(),
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.iRClk(rxclk),
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.iRClk(rxclk),
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.iREn(1'b1),
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.iREn(1'b1),
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.ovDataOut(rxdata),
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.ovDataOut(rxdata),
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.qREmpty(),
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.qREmpty(),
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.qvRNumberLeft()
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.qvRNumberLeft()
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);
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);
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endmodule
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endmodule
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