library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.pkt_ack_pkg.all;
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use work.pkt_ack_pkg.all;
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use work.desc_mgr_pkg.all;
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use work.desc_mgr_pkg.all;
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library unisim;
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library unisim;
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use unisim.vcomponents.all;
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use unisim.vcomponents.all;
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library work;
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library work;
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entity afck_10g_2 is
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entity afck_10g_2 is
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port (
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port (
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gtx10g_txn : out std_logic_vector(3 downto 0);
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gtx10g_txn : out std_logic_vector(3 downto 0);
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gtx10g_txp : out std_logic_vector(3 downto 0);
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gtx10g_txp : out std_logic_vector(3 downto 0);
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gtx10g_rxn : in std_logic_vector(3 downto 0);
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gtx10g_rxn : in std_logic_vector(3 downto 0);
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gtx10g_rxp : in std_logic_vector(3 downto 0);
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gtx10g_rxp : in std_logic_vector(3 downto 0);
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gtx_refclk_n : in std_logic;
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gtx_refclk_n : in std_logic;
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gtx_refclk_p : in std_logic;
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gtx_refclk_p : in std_logic;
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gtx_sfp_disable : out std_logic_vector(3 downto 0);
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gtx_sfp_disable : out std_logic_vector(3 downto 0);
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gtx_rate_sel : out std_logic_vector(3 downto 0);
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gtx_rate_sel : out std_logic_vector(3 downto 0);
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si570_oe : out std_logic;
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si570_oe : out std_logic;
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clk_2_n : in std_logic;
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clk_2_n : in std_logic;
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clk_2_p : in std_logic
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clk_2_p : in std_logic
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);
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);
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end afck_10g_2;
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end afck_10g_2;
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architecture beh1 of afck_10g_2 is
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architecture beh1 of afck_10g_2 is
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constant N_OF_LINKS : integer := 4;
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constant N_OF_LINKS : integer := 4;
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signal heart_bit : integer := 0;
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signal heart_bit : integer := 0;
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signal refclk_p : std_logic := '0';
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signal refclk_p : std_logic := '0';
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signal refclk_n : std_logic := '0';
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signal refclk_n : std_logic := '0';
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signal reset : std_logic := '0';
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signal reset : std_logic := '0';
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signal clk_rst_buf, clk_rst_156 : std_logic := '1'; -- generated reset
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signal clk_rst_buf, clk_rst_156 : std_logic := '1'; -- generated reset
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signal rst_p : std_logic := '1'; -- generated reset
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signal rst_p : std_logic := '1'; -- generated reset
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signal rst_cnt : integer := 200000000;
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signal rst_cnt : integer := 200000000;
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signal s_resetdone : std_logic := '0';
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signal s_resetdone : std_logic := '0';
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signal core_clk156_out : std_logic := '0';
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signal core_clk156_out : std_logic := '0';
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type T_MAC_TABLE is array (0 to N_OF_LINKS-1) of std_logic_vector(47 downto 0);
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type T_MAC_TABLE is array (0 to N_OF_LINKS-1) of std_logic_vector(47 downto 0);
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constant mac_table : T_MAC_TABLE := (
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constant mac_table : T_MAC_TABLE := (
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0 => x"de_ad_fa_de_00_e2",
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0 => x"de_ad_fa_de_00_e2",
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1 => x"de_ad_fa_de_01_e2",
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1 => x"de_ad_fa_de_01_e2",
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2 => x"de_ad_fa_de_02_e2",
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2 => x"de_ad_fa_de_02_e2",
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3 => x"de_ad_fa_de_03_e2"
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3 => x"de_ad_fa_de_03_e2"
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);
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);
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signal s_txusrclk_out : std_logic := '0';
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signal s_txusrclk_out : std_logic := '0';
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signal s_txusrclk2_out : std_logic := '0';
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signal s_txusrclk2_out : std_logic := '0';
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signal areset_clk156_out : std_logic := '0';
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signal areset_clk156_out : std_logic := '0';
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signal gttxreset_out : std_logic := '0';
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signal gttxreset_out : std_logic := '0';
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signal gtrxreset_out : std_logic := '0';
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signal gtrxreset_out : std_logic := '0';
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signal txuserrdy_out : std_logic := '0';
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signal txuserrdy_out : std_logic := '0';
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signal reset_counter_done_out : std_logic := '0';
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signal reset_counter_done_out : std_logic := '0';
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signal qplllock_out : std_logic := '0';
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signal qplllock_out : std_logic := '0';
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signal qplloutclk_out : std_logic := '0';
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signal qplloutclk_out : std_logic := '0';
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signal qplloutrefclk_out : std_logic := '0';
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signal qplloutrefclk_out : std_logic := '0';
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type T_XGMII_XD is array (0 to N_OF_LINKS-1) of std_logic_vector(63 downto 0);
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type T_XGMII_XD is array (0 to N_OF_LINKS-1) of std_logic_vector(63 downto 0);
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signal xgmii_txd : T_XGMII_XD := (others => (others => '0'));
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signal xgmii_txd : T_XGMII_XD := (others => (others => '0'));
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type T_XGMII_XC is array (0 to N_OF_LINKS-1) of std_logic_vector(7 downto 0);
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type T_XGMII_XC is array (0 to N_OF_LINKS-1) of std_logic_vector(7 downto 0);
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signal xgmii_txc : T_XGMII_XC := (others => (others => '0'));
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signal xgmii_txc : T_XGMII_XC := (others => (others => '0'));
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signal xgmii_rxd : T_XGMII_XD := (others => (others => '0'));
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signal xgmii_rxd : T_XGMII_XD := (others => (others => '0'));
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signal xgmii_rxc : T_XGMII_XC := (others => (others => '0'));
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signal xgmii_rxc : T_XGMII_XC := (others => (others => '0'));
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signal configuration_vector : std_logic_vector(535 downto 0) := (others => '0');
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signal configuration_vector : std_logic_vector(535 downto 0) := (others => '0');
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type T_STATUS_VEC is array (0 to N_OF_LINKS-1) of std_logic_vector(447 downto 0);
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type T_STATUS_VEC is array (0 to N_OF_LINKS-1) of std_logic_vector(447 downto 0);
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signal status_vector : T_STATUS_VEC := (others => (others => '0'));
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signal status_vector : T_STATUS_VEC := (others => (others => '0'));
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type T_CORE_STATUS is array (0 to N_OF_LINKS-1) of std_logic_vector(7 downto 0);
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type T_CORE_STATUS is array (0 to N_OF_LINKS-1) of std_logic_vector(7 downto 0);
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signal core_status : T_CORE_STATUS := (others => (others => '0'));
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signal core_status : T_CORE_STATUS := (others => (others => '0'));
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signal signal_detect : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal signal_detect : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal tx_fault : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal tx_fault : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_req : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_req : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_gnt : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_gnt : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_den_o : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_den_o : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_dwe_o : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_dwe_o : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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type T_DRP_V16 is array (0 to N_OF_LINKS-1) of std_logic_vector(15 downto 0);
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type T_DRP_V16 is array (0 to N_OF_LINKS-1) of std_logic_vector(15 downto 0);
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signal drp_daddr_o : T_DRP_V16 := (others => (others => '0'));
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signal drp_daddr_o : T_DRP_V16 := (others => (others => '0'));
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signal drp_di_o : T_DRP_V16 := (others => (others => '0'));
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signal drp_di_o : T_DRP_V16 := (others => (others => '0'));
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signal drp_drdy_o : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_drdy_o : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_drpdo_o : T_DRP_V16 := (others => (others => '0'));
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signal drp_drpdo_o : T_DRP_V16 := (others => (others => '0'));
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signal drp_den_i : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_den_i : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_dwe_i : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_dwe_i : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_daddr_i : T_DRP_V16 := (others => (others => '0'));
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signal drp_daddr_i : T_DRP_V16 := (others => (others => '0'));
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signal drp_di_i : T_DRP_V16 := (others => (others => '0'));
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signal drp_di_i : T_DRP_V16 := (others => (others => '0'));
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signal drp_drdy_i : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_drdy_i : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal drp_drpdo_i : T_DRP_V16 := (others => (others => '0'));
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signal drp_drpdo_i : T_DRP_V16 := (others => (others => '0'));
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signal tx_disable : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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signal tx_disable : std_logic_vector(N_OF_LINKS-1 downto 0) := (others => '0');
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--signal counter : integer := 0;
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--signal counter : integer := 0;
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--signal probe2 : std_logic_vector(2 downto 0);
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--signal probe2 : std_logic_vector(2 downto 0);
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--signal trig_in, trig_in_ack : std_logic := '0';
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--signal trig_in, trig_in_ack : std_logic := '0';
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signal rst_n : std_logic := '0';
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signal rst_n : std_logic := '0';
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signal rst1, clk1 : std_logic := '0';
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signal rst1, clk1 : std_logic := '0';
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signal hb_led : std_logic := '0';
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signal hb_led : std_logic := '0';
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signal clk_user : std_logic;
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signal clk_user : std_logic;
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component ten_gig_eth_pcs_pma_0 is
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component ten_gig_eth_pcs_pma_0 is
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port (
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port (
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dclk : in std_logic;
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dclk : in std_logic;
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rxrecclk_out : out std_logic;
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rxrecclk_out : out std_logic;
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refclk_p : in std_logic;
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refclk_p : in std_logic;
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refclk_n : in std_logic;
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refclk_n : in std_logic;
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sim_speedup_control : in std_logic;
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sim_speedup_control : in std_logic;
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coreclk_out : out std_logic;
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coreclk_out : out std_logic;
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qplloutclk_out : out std_logic;
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qplloutclk_out : out std_logic;
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qplloutrefclk_out : out std_logic;
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qplloutrefclk_out : out std_logic;
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qplllock_out : out std_logic;
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qplllock_out : out std_logic;
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txusrclk_out : out std_logic;
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txusrclk_out : out std_logic;
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txusrclk2_out : out std_logic;
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txusrclk2_out : out std_logic;
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areset_datapathclk_out : out std_logic;
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areset_datapathclk_out : out std_logic;
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gttxreset_out : out std_logic;
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gttxreset_out : out std_logic;
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gtrxreset_out : out std_logic;
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gtrxreset_out : out std_logic;
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txuserrdy_out : out std_logic;
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txuserrdy_out : out std_logic;
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reset_counter_done_out : out std_logic;
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reset_counter_done_out : out std_logic;
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reset : in std_logic;
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reset : in std_logic;
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gt0_eyescanreset : in std_logic;
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gt0_eyescanreset : in std_logic;
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gt0_eyescantrigger : in std_logic;
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gt0_eyescantrigger : in std_logic;
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gt0_rxcdrhold : in std_logic;
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gt0_rxcdrhold : in std_logic;
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gt0_txprbsforceerr : in std_logic;
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gt0_txprbsforceerr : in std_logic;
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gt0_txpolarity : in std_logic;
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gt0_txpolarity : in std_logic;
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gt0_rxpolarity : in std_logic;
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gt0_rxpolarity : in std_logic;
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gt0_rxrate : in std_logic_vector (2 downto 0);
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gt0_rxrate : in std_logic_vector (2 downto 0);
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gt0_txpmareset : in std_logic;
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gt0_txpmareset : in std_logic;
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gt0_rxpmareset : in std_logic;
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gt0_rxpmareset : in std_logic;
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gt0_rxdfelpmreset : in std_logic;
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gt0_rxdfelpmreset : in std_logic;
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gt0_txprecursor : in std_logic_vector (4 downto 0);
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gt0_txprecursor : in std_logic_vector (4 downto 0);
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gt0_txpostcursor : in std_logic_vector (4 downto 0);
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gt0_txpostcursor : in std_logic_vector (4 downto 0);
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gt0_txdiffctrl : in std_logic_vector (3 downto 0);
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gt0_txdiffctrl : in std_logic_vector (3 downto 0);
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gt0_rxlpmen : in std_logic;
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gt0_rxlpmen : in std_logic;
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gt0_eyescandataerror : out std_logic;
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gt0_eyescandataerror : out std_logic;
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gt0_txbufstatus : out std_logic_vector (1 downto 0);
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gt0_txbufstatus : out std_logic_vector (1 downto 0);
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gt0_txresetdone : out std_logic;
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gt0_txresetdone : out std_logic;
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gt0_rxresetdone : out std_logic;
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gt0_rxresetdone : out std_logic;
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gt0_rxbufstatus : out std_logic_vector (2 downto 0);
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gt0_rxbufstatus : out std_logic_vector (2 downto 0);
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gt0_rxprbserr : out std_logic;
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gt0_rxprbserr : out std_logic;
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gt0_dmonitorout : out std_logic_vector (7 downto 0);
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gt0_dmonitorout : out std_logic_vector (7 downto 0);
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xgmii_txd : in std_logic_vector (63 downto 0);
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xgmii_txd : in std_logic_vector (63 downto 0);
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xgmii_txc : in std_logic_vector (7 downto 0);
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xgmii_txc : in std_logic_vector (7 downto 0);
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xgmii_rxd : out std_logic_vector (63 downto 0);
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xgmii_rxd : out std_logic_vector (63 downto 0);
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xgmii_rxc : out std_logic_vector (7 downto 0);
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xgmii_rxc : out std_logic_vector (7 downto 0);
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txp : out std_logic;
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txp : out std_logic;
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txn : out std_logic;
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txn : out std_logic;
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rxp : in std_logic;
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rxp : in std_logic;
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rxn : in std_logic;
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rxn : in std_logic;
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configuration_vector : in std_logic_vector (535 downto 0);
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configuration_vector : in std_logic_vector (535 downto 0);
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status_vector : out std_logic_vector (447 downto 0);
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status_vector : out std_logic_vector (447 downto 0);
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core_status : out std_logic_vector (7 downto 0);
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core_status : out std_logic_vector (7 downto 0);
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resetdone_out : out std_logic;
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resetdone_out : out std_logic;
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signal_detect : in std_logic;
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signal_detect : in std_logic;
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tx_fault : in std_logic;
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tx_fault : in std_logic;
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drp_req : out std_logic;
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drp_req : out std_logic;
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drp_gnt : in std_logic;
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drp_gnt : in std_logic;
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drp_den_o : out std_logic;
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drp_den_o : out std_logic;
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drp_dwe_o : out std_logic;
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drp_dwe_o : out std_logic;
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drp_daddr_o : out std_logic_vector (15 downto 0);
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drp_daddr_o : out std_logic_vector (15 downto 0);
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drp_di_o : out std_logic_vector (15 downto 0);
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drp_di_o : out std_logic_vector (15 downto 0);
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drp_drdy_i : in std_logic;
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drp_drdy_i : in std_logic;
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drp_drpdo_i : in std_logic_vector (15 downto 0);
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drp_drpdo_i : in std_logic_vector (15 downto 0);
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drp_den_i : in std_logic;
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drp_den_i : in std_logic;
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drp_dwe_i : in std_logic;
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drp_dwe_i : in std_logic;
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drp_daddr_i : in std_logic_vector (15 downto 0);
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drp_daddr_i : in std_logic_vector (15 downto 0);
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drp_di_i : in std_logic_vector (15 downto 0);
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drp_di_i : in std_logic_vector (15 downto 0);
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drp_drdy_o : out std_logic;
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drp_drdy_o : out std_logic;
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drp_drpdo_o : out std_logic_vector (15 downto 0);
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drp_drpdo_o : out std_logic_vector (15 downto 0);
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pma_pmd_type : in std_logic_vector (2 downto 0);
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pma_pmd_type : in std_logic_vector (2 downto 0);
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tx_disable : out std_logic);
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tx_disable : out std_logic);
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end component ten_gig_eth_pcs_pma_0;
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end component ten_gig_eth_pcs_pma_0;
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component ten_gig_eth_pcs_pma_1 is
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component ten_gig_eth_pcs_pma_1 is
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port (
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port (
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dclk : in std_logic;
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dclk : in std_logic;
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rxrecclk_out : out std_logic;
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rxrecclk_out : out std_logic;
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coreclk : in std_logic;
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coreclk : in std_logic;
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txusrclk : in std_logic;
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txusrclk : in std_logic;
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txusrclk2 : in std_logic;
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txusrclk2 : in std_logic;
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txoutclk : out std_logic;
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txoutclk : out std_logic;
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areset : in std_logic;
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areset : in std_logic;
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areset_coreclk : in std_logic;
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areset_coreclk : in std_logic;
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gttxreset : in std_logic;
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gttxreset : in std_logic;
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gtrxreset : in std_logic;
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gtrxreset : in std_logic;
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sim_speedup_control : in std_logic;
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sim_speedup_control : in std_logic;
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txuserrdy : in std_logic;
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txuserrdy : in std_logic;
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qplllock : in std_logic;
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qplllock : in std_logic;
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qplloutclk : in std_logic;
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qplloutclk : in std_logic;
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qplloutrefclk : in std_logic;
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qplloutrefclk : in std_logic;
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reset_counter_done : in std_logic;
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reset_counter_done : in std_logic;
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gt0_eyescanreset : in std_logic;
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gt0_eyescanreset : in std_logic;
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gt0_eyescantrigger : in std_logic;
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gt0_eyescantrigger : in std_logic;
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gt0_rxcdrhold : in std_logic;
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gt0_rxcdrhold : in std_logic;
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gt0_txprbsforceerr : in std_logic;
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gt0_txprbsforceerr : in std_logic;
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gt0_txpolarity : in std_logic;
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gt0_txpolarity : in std_logic;
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gt0_rxpolarity : in std_logic;
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gt0_rxpolarity : in std_logic;
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gt0_rxrate : in std_logic_vector (2 downto 0);
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gt0_rxrate : in std_logic_vector (2 downto 0);
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gt0_txpmareset : in std_logic;
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gt0_txpmareset : in std_logic;
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gt0_rxpmareset : in std_logic;
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gt0_rxpmareset : in std_logic;
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gt0_rxdfelpmreset : in std_logic;
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gt0_rxdfelpmreset : in std_logic;
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gt0_txprecursor : in std_logic_vector (4 downto 0);
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gt0_txprecursor : in std_logic_vector (4 downto 0);
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gt0_txpostcursor : in std_logic_vector (4 downto 0);
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gt0_txpostcursor : in std_logic_vector (4 downto 0);
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gt0_txdiffctrl : in std_logic_vector (3 downto 0);
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gt0_txdiffctrl : in std_logic_vector (3 downto 0);
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gt0_rxlpmen : in std_logic;
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gt0_rxlpmen : in std_logic;
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gt0_eyescandataerror : out std_logic;
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gt0_eyescandataerror : out std_logic;
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gt0_txbufstatus : out std_logic_vector (1 downto 0);
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gt0_txbufstatus : out std_logic_vector (1 downto 0);
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gt0_txresetdone : out std_logic;
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gt0_txresetdone : out std_logic;
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gt0_rxresetdone : out std_logic;
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gt0_rxresetdone : out std_logic;
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gt0_rxbufstatus : out std_logic_vector (2 downto 0);
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gt0_rxbufstatus : out std_logic_vector (2 downto 0);
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gt0_rxprbserr : out std_logic;
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gt0_rxprbserr : out std_logic;
|
gt0_dmonitorout : out std_logic_vector (7 downto 0);
|
gt0_dmonitorout : out std_logic_vector (7 downto 0);
|
xgmii_txd : in std_logic_vector (63 downto 0);
|
xgmii_txd : in std_logic_vector (63 downto 0);
|
xgmii_txc : in std_logic_vector (7 downto 0);
|
xgmii_txc : in std_logic_vector (7 downto 0);
|
xgmii_rxd : out std_logic_vector (63 downto 0);
|
xgmii_rxd : out std_logic_vector (63 downto 0);
|
xgmii_rxc : out std_logic_vector (7 downto 0);
|
xgmii_rxc : out std_logic_vector (7 downto 0);
|
txp : out std_logic;
|
txp : out std_logic;
|
txn : out std_logic;
|
txn : out std_logic;
|
rxp : in std_logic;
|
rxp : in std_logic;
|
rxn : in std_logic;
|
rxn : in std_logic;
|
configuration_vector : in std_logic_vector (535 downto 0);
|
configuration_vector : in std_logic_vector (535 downto 0);
|
status_vector : out std_logic_vector (447 downto 0);
|
status_vector : out std_logic_vector (447 downto 0);
|
core_status : out std_logic_vector (7 downto 0);
|
core_status : out std_logic_vector (7 downto 0);
|
tx_resetdone : out std_logic;
|
tx_resetdone : out std_logic;
|
rx_resetdone : out std_logic;
|
rx_resetdone : out std_logic;
|
signal_detect : in std_logic;
|
signal_detect : in std_logic;
|
tx_fault : in std_logic;
|
tx_fault : in std_logic;
|
drp_req : out std_logic;
|
drp_req : out std_logic;
|
drp_gnt : in std_logic;
|
drp_gnt : in std_logic;
|
drp_den_o : out std_logic;
|
drp_den_o : out std_logic;
|
drp_dwe_o : out std_logic;
|
drp_dwe_o : out std_logic;
|
drp_daddr_o : out std_logic_vector (15 downto 0);
|
drp_daddr_o : out std_logic_vector (15 downto 0);
|
drp_di_o : out std_logic_vector (15 downto 0);
|
drp_di_o : out std_logic_vector (15 downto 0);
|
drp_drdy_i : in std_logic;
|
drp_drdy_i : in std_logic;
|
drp_drpdo_i : in std_logic_vector (15 downto 0);
|
drp_drpdo_i : in std_logic_vector (15 downto 0);
|
drp_den_i : in std_logic;
|
drp_den_i : in std_logic;
|
drp_dwe_i : in std_logic;
|
drp_dwe_i : in std_logic;
|
drp_daddr_i : in std_logic_vector (15 downto 0);
|
drp_daddr_i : in std_logic_vector (15 downto 0);
|
drp_di_i : in std_logic_vector (15 downto 0);
|
drp_di_i : in std_logic_vector (15 downto 0);
|
drp_drdy_o : out std_logic;
|
drp_drdy_o : out std_logic;
|
drp_drpdo_o : out std_logic_vector (15 downto 0);
|
drp_drpdo_o : out std_logic_vector (15 downto 0);
|
pma_pmd_type : in std_logic_vector (2 downto 0);
|
pma_pmd_type : in std_logic_vector (2 downto 0);
|
tx_disable : out std_logic);
|
tx_disable : out std_logic);
|
end component ten_gig_eth_pcs_pma_1;
|
end component ten_gig_eth_pcs_pma_1;
|
|
|
component fade_one_channel is
|
component fade_one_channel is
|
generic (
|
generic (
|
my_mac : std_logic_vector(47 downto 0));
|
my_mac : std_logic_vector(47 downto 0));
|
port (
|
port (
|
xgmii_txd : out std_logic_vector(63 downto 0);
|
xgmii_txd : out std_logic_vector(63 downto 0);
|
xgmii_txc : out std_logic_vector(7 downto 0);
|
xgmii_txc : out std_logic_vector(7 downto 0);
|
xgmii_rxd : in std_logic_vector(63 downto 0);
|
xgmii_rxd : in std_logic_vector(63 downto 0);
|
xgmii_rxc : in std_logic_vector(7 downto 0);
|
xgmii_rxc : in std_logic_vector(7 downto 0);
|
rst_n : in std_logic;
|
rst_n : in std_logic;
|
clk_user : in std_logic);
|
clk_user : in std_logic);
|
end component fade_one_channel;
|
end component fade_one_channel;
|
|
|
begin -- beh1
|
begin -- beh1
|
si570_oe <= '1';
|
si570_oe <= '1';
|
-- Initialization vector
|
-- Initialization vector
|
configuration_vector(33) <= '1'; -- training
|
configuration_vector(33) <= '1'; -- training
|
configuration_vector(284) <= '1'; -- auto negotiation
|
configuration_vector(284) <= '1'; -- auto negotiation
|
|
|
gtx_rate_sel <= (others => '1');
|
gtx_rate_sel <= (others => '1');
|
signal_detect <= (others => '1'); -- allow transmission!
|
signal_detect <= (others => '1'); -- allow transmission!
|
gtx_sfp_disable <= (others => '0');
|
gtx_sfp_disable <= (others => '0');
|
|
|
-- Reset generator
|
-- Reset generator
|
process (clk_rst_156) is
|
process (clk_rst_156) is
|
begin -- process
|
begin -- process
|
if clk_rst_156'event and clk_rst_156 = '1' then -- rising clock edge
|
if clk_rst_156'event and clk_rst_156 = '1' then -- rising clock edge
|
if rst_cnt > 0 then
|
if rst_cnt > 0 then
|
rst_cnt <= rst_cnt - 1;
|
rst_cnt <= rst_cnt - 1;
|
else
|
else
|
rst_p <= '0';
|
rst_p <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
cmp_gtp_dedicated_clk_buf : IBUFDS_GTE2
|
cmp_gtp_dedicated_clk_buf : IBUFDS_GTE2
|
-- generic map(
|
-- generic map(
|
-- DIFF_TERM => true,
|
-- DIFF_TERM => true,
|
-- IBUF_LOW_PWR => true,
|
-- IBUF_LOW_PWR => true,
|
-- IOSTANDARD => "DEFAULT")
|
-- IOSTANDARD => "DEFAULT")
|
port map (
|
port map (
|
O => clk_rst_buf,
|
O => clk_rst_buf,
|
ODIV2 => open,
|
ODIV2 => open,
|
CEB => '0',
|
CEB => '0',
|
I => clk_2_p,
|
I => clk_2_p,
|
IB => clk_2_n
|
IB => clk_2_n
|
);
|
);
|
|
|
cmp_clk_ref_buf : BUFG
|
cmp_clk_ref_buf : BUFG
|
port map (
|
port map (
|
O => clk_rst_156,
|
O => clk_rst_156,
|
I => clk_rst_buf);
|
I => clk_rst_buf);
|
|
|
rst_n <= not rst_p;
|
rst_n <= not rst_p;
|
refclk_n <= gtx_refclk_n;
|
refclk_n <= gtx_refclk_n;
|
refclk_p <= gtx_refclk_p;
|
refclk_p <= gtx_refclk_p;
|
reset <= not rst_n;
|
reset <= not rst_n;
|
|
|
--trig_in <= '1' when xgmii_rxc /= x"ff" else '0';
|
--trig_in <= '1' when xgmii_rxc /= x"ff" else '0';
|
gl1 : for n in 0 to N_OF_LINKS-1 generate
|
gl1 : for n in 0 to N_OF_LINKS-1 generate
|
|
|
il1 : if n = 0 generate
|
il1 : if n = 0 generate
|
ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0
|
ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0
|
port map (
|
port map (
|
dclk => clk_user,
|
dclk => clk_user,
|
rxrecclk_out => open, --??
|
rxrecclk_out => open, --??
|
refclk_p => refclk_p,
|
refclk_p => refclk_p,
|
refclk_n => refclk_n,
|
refclk_n => refclk_n,
|
sim_speedup_control => '0',
|
sim_speedup_control => '0',
|
coreclk_out => core_clk156_out,
|
coreclk_out => core_clk156_out,
|
qplloutclk_out => qplloutclk_out,
|
qplloutclk_out => qplloutclk_out,
|
qplloutrefclk_out => qplloutrefclk_out,
|
qplloutrefclk_out => qplloutrefclk_out,
|
qplllock_out => qplllock_out,
|
qplllock_out => qplllock_out,
|
txusrclk_out => s_txusrclk_out,
|
txusrclk_out => s_txusrclk_out,
|
txusrclk2_out => s_txusrclk2_out,
|
txusrclk2_out => s_txusrclk2_out,
|
areset_datapathclk_out => areset_clk156_out,
|
areset_datapathclk_out => areset_clk156_out,
|
gttxreset_out => gttxreset_out,
|
gttxreset_out => gttxreset_out,
|
gtrxreset_out => gtrxreset_out,
|
gtrxreset_out => gtrxreset_out,
|
txuserrdy_out => txuserrdy_out,
|
txuserrdy_out => txuserrdy_out,
|
reset_counter_done_out => reset_counter_done_out,
|
reset_counter_done_out => reset_counter_done_out,
|
reset => reset,
|
reset => reset,
|
gt0_eyescanreset => '0',
|
gt0_eyescanreset => '0',
|
gt0_eyescantrigger => '0',
|
gt0_eyescantrigger => '0',
|
gt0_rxcdrhold => '0',
|
gt0_rxcdrhold => '0',
|
gt0_txprbsforceerr => '0',
|
gt0_txprbsforceerr => '0',
|
gt0_txpolarity => '0',
|
gt0_txpolarity => '0',
|
gt0_rxpolarity => '0',
|
gt0_rxpolarity => '0',
|
gt0_rxrate => (others => '0'),
|
gt0_rxrate => (others => '0'),
|
gt0_txpmareset => '0',
|
gt0_txpmareset => '0',
|
gt0_rxpmareset => '0',
|
gt0_rxpmareset => '0',
|
gt0_rxdfelpmreset => '0',
|
gt0_rxdfelpmreset => '0',
|
gt0_txprecursor => (others => '0'),
|
gt0_txprecursor => (others => '0'),
|
gt0_txpostcursor => (others => '0'),
|
gt0_txpostcursor => (others => '0'),
|
gt0_txdiffctrl => "1110",
|
gt0_txdiffctrl => "1110",
|
gt0_rxlpmen => '0',
|
gt0_rxlpmen => '0',
|
gt0_eyescandataerror => open,
|
gt0_eyescandataerror => open,
|
gt0_txbufstatus => open,
|
gt0_txbufstatus => open,
|
gt0_txresetdone => open,
|
gt0_txresetdone => open,
|
gt0_rxresetdone => open,
|
gt0_rxresetdone => open,
|
gt0_rxbufstatus => open,
|
gt0_rxbufstatus => open,
|
gt0_rxprbserr => open,
|
gt0_rxprbserr => open,
|
gt0_dmonitorout => open,
|
gt0_dmonitorout => open,
|
xgmii_txd => xgmii_txd(n),
|
xgmii_txd => xgmii_txd(n),
|
xgmii_txc => xgmii_txc(n),
|
xgmii_txc => xgmii_txc(n),
|
xgmii_rxd => xgmii_rxd(n),
|
xgmii_rxd => xgmii_rxd(n),
|
xgmii_rxc => xgmii_rxc(n),
|
xgmii_rxc => xgmii_rxc(n),
|
txp => gtx10g_txp(n),
|
txp => gtx10g_txp(n),
|
txn => gtx10g_txn(n),
|
txn => gtx10g_txn(n),
|
rxp => gtx10g_rxp(n),
|
rxp => gtx10g_rxp(n),
|
rxn => gtx10g_rxn(n),
|
rxn => gtx10g_rxn(n),
|
configuration_vector => configuration_vector,
|
configuration_vector => configuration_vector,
|
status_vector => status_vector(n),
|
status_vector => status_vector(n),
|
core_status => core_status(n),
|
core_status => core_status(n),
|
resetdone_out => s_resetdone,
|
resetdone_out => s_resetdone,
|
signal_detect => signal_detect(n),
|
signal_detect => signal_detect(n),
|
tx_fault => tx_fault(n),
|
tx_fault => tx_fault(n),
|
drp_req => drp_req(n),
|
drp_req => drp_req(n),
|
drp_gnt => drp_gnt(n),
|
drp_gnt => drp_gnt(n),
|
drp_den_o => drp_den_o(n),
|
drp_den_o => drp_den_o(n),
|
drp_dwe_o => drp_dwe_o(n),
|
drp_dwe_o => drp_dwe_o(n),
|
drp_daddr_o => drp_daddr_o(n),
|
drp_daddr_o => drp_daddr_o(n),
|
drp_di_o => drp_di_o(n),
|
drp_di_o => drp_di_o(n),
|
drp_drdy_i => drp_drdy_i(n),
|
drp_drdy_i => drp_drdy_i(n),
|
drp_drpdo_i => drp_drpdo_i(n),
|
drp_drpdo_i => drp_drpdo_i(n),
|
drp_den_i => drp_den_i(n),
|
drp_den_i => drp_den_i(n),
|
drp_dwe_i => drp_dwe_i(n),
|
drp_dwe_i => drp_dwe_i(n),
|
drp_daddr_i => drp_daddr_i(n),
|
drp_daddr_i => drp_daddr_i(n),
|
drp_di_i => drp_di_i(n),
|
drp_di_i => drp_di_i(n),
|
drp_drdy_o => drp_drdy_o(n),
|
drp_drdy_o => drp_drdy_o(n),
|
drp_drpdo_o => drp_drpdo_o(n),
|
drp_drpdo_o => drp_drpdo_o(n),
|
pma_pmd_type => "111",
|
pma_pmd_type => "111",
|
tx_disable => tx_disable(n)
|
tx_disable => tx_disable(n)
|
);
|
);
|
|
|
end generate il1;
|
end generate il1;
|
il2 : if n /= 0 generate
|
il2 : if n /= 0 generate
|
ten_gig_eth_pcs_pma_1_1 : ten_gig_eth_pcs_pma_1
|
ten_gig_eth_pcs_pma_1_1 : ten_gig_eth_pcs_pma_1
|
port map (
|
port map (
|
dclk => clk_user,
|
dclk => clk_user,
|
rxrecclk_out => open, --??
|
rxrecclk_out => open, --??
|
coreclk => core_clk156_out,
|
coreclk => core_clk156_out,
|
txusrclk => s_txusrclk_out,
|
txusrclk => s_txusrclk_out,
|
txusrclk2 => s_txusrclk2_out,
|
txusrclk2 => s_txusrclk2_out,
|
txoutclk => open,
|
txoutclk => open,
|
areset => reset,
|
areset => reset,
|
areset_coreclk => areset_clk156_out,
|
areset_coreclk => areset_clk156_out,
|
gttxreset => gttxreset_out,
|
gttxreset => gttxreset_out,
|
gtrxreset => gtrxreset_out,
|
gtrxreset => gtrxreset_out,
|
sim_speedup_control => '0',
|
sim_speedup_control => '0',
|
txuserrdy => txuserrdy_out,
|
txuserrdy => txuserrdy_out,
|
qplllock => qplllock_out,
|
qplllock => qplllock_out,
|
qplloutclk => qplloutclk_out,
|
qplloutclk => qplloutclk_out,
|
qplloutrefclk => qplloutrefclk_out,
|
qplloutrefclk => qplloutrefclk_out,
|
reset_counter_done => reset_counter_done_out,
|
reset_counter_done => reset_counter_done_out,
|
gt0_eyescanreset => '0',
|
gt0_eyescanreset => '0',
|
gt0_eyescantrigger => '0',
|
gt0_eyescantrigger => '0',
|
gt0_rxcdrhold => '0',
|
gt0_rxcdrhold => '0',
|
gt0_txprbsforceerr => '0',
|
gt0_txprbsforceerr => '0',
|
gt0_txpolarity => '0',
|
gt0_txpolarity => '0',
|
gt0_rxpolarity => '0',
|
gt0_rxpolarity => '0',
|
gt0_rxrate => (others => '0'),
|
gt0_rxrate => (others => '0'),
|
gt0_txpmareset => '0',
|
gt0_txpmareset => '0',
|
gt0_rxpmareset => '0',
|
gt0_rxpmareset => '0',
|
gt0_rxdfelpmreset => '0',
|
gt0_rxdfelpmreset => '0',
|
gt0_txprecursor => (others => '0'),
|
gt0_txprecursor => (others => '0'),
|
gt0_txpostcursor => (others => '0'),
|
gt0_txpostcursor => (others => '0'),
|
gt0_txdiffctrl => "1110",
|
gt0_txdiffctrl => "1110",
|
gt0_rxlpmen => '0',
|
gt0_rxlpmen => '0',
|
gt0_eyescandataerror => open,
|
gt0_eyescandataerror => open,
|
gt0_txbufstatus => open,
|
gt0_txbufstatus => open,
|
gt0_txresetdone => open,
|
gt0_txresetdone => open,
|
gt0_rxresetdone => open,
|
gt0_rxresetdone => open,
|
gt0_rxbufstatus => open,
|
gt0_rxbufstatus => open,
|
gt0_rxprbserr => open,
|
gt0_rxprbserr => open,
|
gt0_dmonitorout => open,
|
gt0_dmonitorout => open,
|
xgmii_txd => xgmii_txd(n),
|
xgmii_txd => xgmii_txd(n),
|
xgmii_txc => xgmii_txc(n),
|
xgmii_txc => xgmii_txc(n),
|
xgmii_rxd => xgmii_rxd(n),
|
xgmii_rxd => xgmii_rxd(n),
|
xgmii_rxc => xgmii_rxc(n),
|
xgmii_rxc => xgmii_rxc(n),
|
txp => gtx10g_txp(n),
|
txp => gtx10g_txp(n),
|
txn => gtx10g_txn(n),
|
txn => gtx10g_txn(n),
|
rxp => gtx10g_rxp(n),
|
rxp => gtx10g_rxp(n),
|
rxn => gtx10g_rxn(n),
|
rxn => gtx10g_rxn(n),
|
configuration_vector => configuration_vector,
|
configuration_vector => configuration_vector,
|
status_vector => status_vector(n),
|
status_vector => status_vector(n),
|
core_status => core_status(n),
|
core_status => core_status(n),
|
tx_resetdone => open,
|
tx_resetdone => open,
|
rx_resetdone => open,
|
rx_resetdone => open,
|
signal_detect => signal_detect(n),
|
signal_detect => signal_detect(n),
|
tx_fault => tx_fault(n),
|
tx_fault => tx_fault(n),
|
drp_req => drp_req(n),
|
drp_req => drp_req(n),
|
drp_gnt => drp_gnt(n),
|
drp_gnt => drp_gnt(n),
|
drp_den_o => drp_den_o(n),
|
drp_den_o => drp_den_o(n),
|
drp_dwe_o => drp_dwe_o(n),
|
drp_dwe_o => drp_dwe_o(n),
|
drp_daddr_o => drp_daddr_o(n),
|
drp_daddr_o => drp_daddr_o(n),
|
drp_di_o => drp_di_o(n),
|
drp_di_o => drp_di_o(n),
|
drp_drdy_i => drp_drdy_i(n),
|
drp_drdy_i => drp_drdy_i(n),
|
drp_drpdo_i => drp_drpdo_i(n),
|
drp_drpdo_i => drp_drpdo_i(n),
|
drp_den_i => drp_den_i(n),
|
drp_den_i => drp_den_i(n),
|
drp_dwe_i => drp_dwe_i(n),
|
drp_dwe_i => drp_dwe_i(n),
|
drp_daddr_i => drp_daddr_i(n),
|
drp_daddr_i => drp_daddr_i(n),
|
drp_di_i => drp_di_i(n),
|
drp_di_i => drp_di_i(n),
|
drp_drdy_o => drp_drdy_o(n),
|
drp_drdy_o => drp_drdy_o(n),
|
drp_drpdo_o => drp_drpdo_o(n),
|
drp_drpdo_o => drp_drpdo_o(n),
|
pma_pmd_type => "111",
|
pma_pmd_type => "111",
|
tx_disable => tx_disable(n));
|
tx_disable => tx_disable(n));
|
end generate il2;
|
end generate il2;
|
|
|
drp_gnt(n) <= drp_req(n);
|
drp_gnt(n) <= drp_req(n);
|
drp_den_i(n) <= drp_den_o(n);
|
drp_den_i(n) <= drp_den_o(n);
|
drp_dwe_i(n) <= drp_dwe_o(n);
|
drp_dwe_i(n) <= drp_dwe_o(n);
|
drp_daddr_i(n) <= drp_daddr_o(n);
|
drp_daddr_i(n) <= drp_daddr_o(n);
|
drp_di_i(n) <= drp_di_o(n);
|
drp_di_i(n) <= drp_di_o(n);
|
drp_drpdo_i(n) <= drp_drpdo_o(n);
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drp_drpdo_i(n) <= drp_drpdo_o(n);
|
|
|
fade_one_channel_1 : entity work.fade_one_channel
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fade_one_channel_1 : entity work.fade_one_channel
|
generic map (
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generic map (
|
my_mac => mac_table(n))
|
my_mac => mac_table(n))
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port map (
|
port map (
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xgmii_txd => xgmii_txd(n),
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xgmii_txd => xgmii_txd(n),
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xgmii_txc => xgmii_txc(n),
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xgmii_txc => xgmii_txc(n),
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xgmii_rxd => xgmii_rxd(n),
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xgmii_rxd => xgmii_rxd(n),
|
xgmii_rxc => xgmii_rxc(n),
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xgmii_rxc => xgmii_rxc(n),
|
rst_n => rst_n,
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rst_n => rst_n,
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clk_user => clk_user);
|
clk_user => clk_user);
|
|
|
|
|
|
|
end generate gl1;
|
end generate gl1;
|
|
|
rst1 <= core_status(0)(0);
|
rst1 <= core_status(0)(0);
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--core_ready <= core_status(0);
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--core_ready <= core_status(0);
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clk1 <= core_clk156_out;
|
clk1 <= core_clk156_out;
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clk_user <= core_clk156_out;
|
clk_user <= core_clk156_out;
|
|
|
p1 : process (clk1, rst_n)
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p1 : process (clk1, rst_n)
|
begin -- process p1
|
begin -- process p1
|
if rst_n = '0' then -- asynchronous reset (active low)
|
if rst_n = '0' then -- asynchronous reset (active low)
|
heart_bit <= 0;
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heart_bit <= 0;
|
elsif clk1'event and clk1 = '1' then -- rising clock edge
|
elsif clk1'event and clk1 = '1' then -- rising clock edge
|
if heart_bit < 80000000 then
|
if heart_bit < 80000000 then
|
heart_bit <= heart_bit + 1;
|
heart_bit <= heart_bit + 1;
|
else
|
else
|
heart_bit <= 0;
|
heart_bit <= 0;
|
hb_led <= not hb_led;
|
hb_led <= not hb_led;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process p1;
|
end process p1;
|
|
|
|
|
end beh1;
|
end beh1;
|
|
|