-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : I2C controller driven by VIO objects
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-- Title : I2C controller driven by VIO objects
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-- Project :
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-- Project :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : i2c_vio_ctrl_top.vhd
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-- File : i2c_vio_ctrl_top.vhd
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-- Author : Wojciech M. Zabolotny wzab01<at>gmail.com
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-- Author : Wojciech M. Zabolotny wzab01<at>gmail.com
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-- License : PUBLIC DOMAIN
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-- License : PUBLIC DOMAIN
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-- Company :
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-- Company :
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-- Created : 2015-05-03
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-- Created : 2015-05-03
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-- Last update: 2015-05-07
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-- Last update: 2017-01-22
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-- Platform :
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-- Platform :
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-- Standard : VHDL'93/02
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description:
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-- Description:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (c) 2015
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-- Copyright (c) 2015
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Revisions :
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-- Date Version Author Description
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-- Date Version Author Description
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-- 2015-05-03 1.0 wzab Created
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-- 2015-05-03 1.0 wzab Created
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity i2c_vio_ctrl is
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entity i2c_vio_ctrl is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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--rst_p : in std_logic;
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--rst_p : in std_logic;
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scl : inout std_logic;
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scl : inout std_logic;
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sda : inout std_logic);
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sda : inout std_logic);
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end entity i2c_vio_ctrl;
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end entity i2c_vio_ctrl;
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architecture beh of i2c_vio_ctrl is
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architecture beh of i2c_vio_ctrl is
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signal din : std_logic_vector(7 downto 0);
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signal din : std_logic_vector(7 downto 0);
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signal dout : std_logic_vector(7 downto 0);
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signal dout : std_logic_vector(7 downto 0);
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signal addr : std_logic_vector(2 downto 0);
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signal addr : std_logic_vector(2 downto 0);
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signal rd_nwr : std_logic_vector(0 to 0);
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signal rd_nwr : std_logic_vector(0 to 0);
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signal cs : std_logic_vector(0 to 0);
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signal cs : std_logic_vector(0 to 0);
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signal vclk : std_logic;
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signal vclk : std_logic;
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signal i2c_rst_n : std_logic_vector(0 to 0);
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signal i2c_rst_n : std_logic_vector(0 to 0);
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signal vrst_n : std_logic_vector(0 to 0);
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signal vrst_n : std_logic_vector(0 to 0);
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signal scl_i : std_logic;
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signal scl_i : std_logic;
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signal scl_o : std_logic;
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signal scl_o : std_logic;
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signal sda_i : std_logic;
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signal sda_i : std_logic;
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signal sda_o : std_logic;
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signal sda_o : std_logic;
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component i2c_bus_wrap is
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component i2c_bus_wrap is
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port (
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port (
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din : in std_logic_vector(7 downto 0);
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din : in std_logic_vector(7 downto 0);
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dout : out std_logic_vector(7 downto 0);
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dout : out std_logic_vector(7 downto 0);
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addr : in std_logic_vector(2 downto 0);
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addr : in std_logic_vector(2 downto 0);
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rd_nwr : in std_logic;
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rd_nwr : in std_logic;
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cs : in std_logic;
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cs : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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scl_i : in std_logic;
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scl_i : in std_logic;
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scl_o : out std_logic;
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scl_o : out std_logic;
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sda_i : in std_logic;
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sda_i : in std_logic;
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sda_o : out std_logic);
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sda_o : out std_logic);
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end component i2c_bus_wrap;
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end component i2c_bus_wrap;
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component vio_0 is
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component vio_0 is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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probe_in0 : in std_logic_vector (7 downto 0);
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probe_in0 : in std_logic_vector (7 downto 0);
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probe_out0 : out std_logic_vector (0 downto 0);
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probe_out0 : out std_logic_vector (0 downto 0);
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probe_out1 : out std_logic_vector (7 downto 0);
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probe_out1 : out std_logic_vector (7 downto 0);
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probe_out2 : out std_logic_vector (2 downto 0);
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probe_out2 : out std_logic_vector (2 downto 0);
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probe_out3 : out std_logic_vector (0 to 0);
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probe_out3 : out std_logic_vector (0 to 0);
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probe_out4 : out std_logic_vector (0 to 0);
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probe_out4 : out std_logic_vector (0 to 0);
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probe_out5 : out std_logic_vector (0 to 0));
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probe_out5 : out std_logic_vector (0 to 0));
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end component vio_0;
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end component vio_0;
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begin -- architecture beh
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begin -- architecture beh
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vio_0_1 : entity work.vio_0
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vio_0_1 : vio_0
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port map (
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port map (
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clk => clk,
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clk => clk,
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probe_in0 => dout,
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probe_in0 => dout,
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probe_out0 => i2c_rst_n,
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probe_out0 => i2c_rst_n,
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probe_out1 => din,
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probe_out1 => din,
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probe_out2 => addr,
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probe_out2 => addr,
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probe_out3 => rd_nwr,
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probe_out3 => rd_nwr,
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probe_out4 => cs,
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probe_out4 => cs,
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probe_out5 => vrst_n);
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probe_out5 => vrst_n);
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i2c_bus_wrap1 : entity work.i2c_bus_wrap
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i2c_bus_wrap1 : entity work.i2c_bus_wrap
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port map (
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port map (
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din => din,
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din => din,
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dout => dout,
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dout => dout,
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addr => addr,
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addr => addr,
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rd_nwr => rd_nwr(0),
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rd_nwr => rd_nwr(0),
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cs => cs(0),
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cs => cs(0),
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clk => vclk,
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clk => vclk,
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rst => vrst_n(0),
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rst => vrst_n(0),
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i2c_rst => i2c_rst_n(0),
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i2c_rst => i2c_rst_n(0),
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scl_i => scl_i,
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scl_i => scl_i,
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scl_o => scl_o,
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scl_o => scl_o,
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sda_i => sda_i,
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sda_i => sda_i,
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sda_o => sda_o);
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sda_o => sda_o);
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vclk <= clk;
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vclk <= clk;
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scl_i <= scl;
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scl_i <= scl;
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sda_i <= sda;
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sda_i <= sda;
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scl <= '0' when scl_o = '0' else 'Z';
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scl <= '0' when scl_o = '0' else 'Z';
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sda <= '0' when sda_o = '0' else 'Z';
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sda <= '0' when sda_o = '0' else 'Z';
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end architecture beh;
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end architecture beh;
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