/* FIR Filter.
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/* FIR Filter.
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Copyright© 2012 Tauhop Solutions. All rights reserved.
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Copyright© 2012 Tauhop Solutions. All rights reserved.
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This core is free hardware design; you can redistribute it and/or
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This core is free hardware design; you can redistribute it and/or
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modify it under the terms of the GNU Library General Public
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modify it under the terms of the GNU Library General Public
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License as published by the Free Software Foundation; either
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License as published by the Free Software Foundation; either
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version 2 of the License, or (at your option) any later version.
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version 2 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Library General Public License for more details.
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Library General Public License for more details.
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You should have received a copy of the GNU Library General Public
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You should have received a copy of the GNU Library General Public
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License along with this library; if not, write to the
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License along with this library; if not, write to the
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Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA.
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Boston, MA 02111-1307, USA.
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License: LGPL.
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License: LGPL.
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@dependencies:
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@dependencies:
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@designer(s):
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@designer(s):
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Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com];
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Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com];
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Tan Hooi Jing [hooijingtan@gmail.com]
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Tan Hooi Jing [hooijingtan@gmail.com]
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@info:
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@info:
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Revision History: @see Mercurial log for full list of changes.
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Revision History: @see Mercurial log for full list of changes.
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This notice and disclaimer must be retained as part of this text at all times.
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This notice and disclaimer must be retained as part of this text at all times.
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*/
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*/
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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/* Filter order = number of unit delays. */
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/* Filter order = number of unit delays. */
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entity fir is generic(order:positive:=30; width:positive:=16);
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entity fir is generic(order:positive:=30; width:positive:=16);
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port(
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port(
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reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again.
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reset:in std_ulogic; -- asserting reset will start protocol sequence transmission. To restart the re-transmission of the sequence, re-assert this reset signal, and the whole SPI sequence will be re-transmitted again.
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clk:in std_ulogic:='0';
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clk:in std_ulogic:='0';
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/* Filter ports. */
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/* Filter ports. */
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u:in signed(width-1 downto 0):=(others=>'0');
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u:in signed(width-1 downto 0):=(others=>'0');
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y:buffer signed(width-1 downto 0)
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y:buffer signed(width-1 downto 0)
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);
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);
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end entity fir;
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end entity fir;
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architecture rtl of fir is
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architecture rtl of fir is
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/* Memory I/Os: */
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/* Memory I/Os: */
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signal q:signed(width-1 downto 0):=(others=>'0');
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signal q:signed(width-1 downto 0):=(others=>'0');
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--signal rst: std_ulogic;
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--signal rst: std_ulogic;
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--signal pwrUpCnt: unsigned(8 downto 0):=(others=>'0');
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--signal pwrUpCnt: unsigned(8 downto 0):=(others=>'0');
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--signal trig:std_logic;
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--signal trig:std_logic;
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--signal c:unsigned(positive(ceil(log2(real(order))))-1 downto 0); --counter:5bits
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--signal c:unsigned(positive(ceil(log2(real(order))))-1 downto 0); --counter:5bits
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-- debugger
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-- debugger
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--signal dbgSignals:std_ulogic_vector(127 downto 0);
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--signal dbgSignals:std_ulogic_vector(127 downto 0);
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/* Memories: */
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/* Memories: */
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/* TODO: Change these arrays to internal process variables instead. */
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/* TODO: Change these arrays to internal process variables instead. */
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/* Read-only Memory (ROM). */
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/* Read-only Memory (ROM). */
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type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned.
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type signed_vector is array(natural range <>) of signed(width-1 downto 0); -- 32-by-N matrix array structure (as in RAM). Similar to integer_vector, difference being base vector is 32-bit unsigned.
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type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0);
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type signedx2_vector is array(natural range<>) of signed(width*2-1 downto 0);
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/* Filter length = number of taps = number of coefficients = order + 1 */
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/* Filter length = number of taps = number of coefficients = order + 1 */
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constant b:signed_vector(0 to order):=(
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constant b:signed_vector(0 to order):=(
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x"FFEF",
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x"FFEF",
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x"FFED",
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x"FFED",
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x"FFE8",
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x"FFE8",
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x"FFE6",
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x"FFE6",
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x"FFEB",
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x"FFEB",
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x"0000",
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x"0000",
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x"002C",
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x"002C",
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x"0075",
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x"0075",
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x"00DC",
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x"00DC",
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x"015F",
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x"015F",
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x"01F4",
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x"01F4",
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x"028E",
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x"028E",
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x"031F",
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x"031F",
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x"0394",
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x"0394",
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x"03E1",
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x"03E1",
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x"03FC",
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x"03FC",
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x"03E1",
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x"03E1",
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x"0394",
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x"0394",
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x"031F",
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x"031F",
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x"028E",
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x"028E",
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x"01F4",
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x"01F4",
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x"015F",
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x"015F",
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x"00DC",
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x"00DC",
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x"0075",
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x"0075",
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x"002C",
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x"002C",
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x"0000",
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x"0000",
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x"FFEB",
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x"FFEB",
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x"FFE6",
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x"FFE6",
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x"FFE8",
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x"FFE8",
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x"FFED",
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x"FFED",
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x"FFEF"
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x"FFEF"
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);
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);
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/*Memory Addressing*/
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/*Memory Addressing*/
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-- signal c:natural range b'range;
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-- signal c:natural range b'range;
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/* Pipes and delay chains. */
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/* Pipes and delay chains. */
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signal y0:signed(width*2-1 downto 0);
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signal y0:signed(width*2-1 downto 0);
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signal u_pipe:signed_vector(b'range):=(others=>(others=>'0'));
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signal u_pipe:signed_vector(b'range):=(others=>(others=>'0'));
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signal y_pipe:signedx2_vector(b'range):=(others=>(others=>'0'));
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signal y_pipe:signedx2_vector(b'range):=(others=>(others=>'0'));
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/* Counters. */
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/* Counters. */
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-- signal cnt:integer range 31 downto -1; -- symbol / bit counter. Counts the bits transmitted on the serial line.
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-- signal cnt:integer range 31 downto -1; -- symbol / bit counter. Counts the bits transmitted on the serial line.
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-- /* memory pointers (acts as the read/write address for the synchronous RAM). */
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-- /* memory pointers (acts as the read/write address for the synchronous RAM). */
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-- signal instrPtr:natural range rfbSequencesCache'range; --RFB sequence memory addressing. Acts as instruction pointer. Points to the current SPI instruction to be transmitted on MOSI. Size is one more than the instruction cache size, so it points past the last valid address (used for counting).
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-- signal instrPtr:natural range rfbSequencesCache'range; --RFB sequence memory addressing. Acts as instruction pointer. Points to the current SPI instruction to be transmitted on MOSI. Size is one more than the instruction cache size, so it points past the last valid address (used for counting).
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/* [end]: Memories. */
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/* [end]: Memories. */
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/* Signal preservations. */
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/* Signal preservations. */
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-- attribute keep:boolean;
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-- attribute keep:boolean;
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/* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */
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/* Explicitly define all multiplications with the "*" operator to use dedicated DSP hardware multipliers. */
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attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera
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attribute multstyle:string; attribute multstyle of rtl:architecture is "dsp"; --altera
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-- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx
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-- attribute mult_style:string; attribute mult_style of fir:entity is "block"; --xilinx
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begin
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begin
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-- /* 1-Dimensional Synchronous ROM. */
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-- /* 1-Dimensional Synchronous ROM. */
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-- readCoeffs: process(clk) is begin
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-- readCoeffs: process(clk) is begin
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-- if rising_edge(clk) then
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-- if rising_edge(clk) then
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-- if reset='1' then q<=(others=>'0');
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-- if reset='1' then q<=(others=>'0');
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-- else q<=b(c);
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-- else q<=b(c);
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-- end if;
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-- end if;
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-- end if;
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-- end if;
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-- end process readCoeffs;
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-- end process readCoeffs;
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u_pipe(0)<=u;
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u_pipe(0)<=u;
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u_dlyChain: for i in 1 to u_pipe'high generate
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u_dlyChain: for i in 1 to u_pipe'high generate
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delayChain: process(clk) is begin
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delayChain: process(clk) is begin
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if rising_edge(clk) then u_pipe(i)<=u_pipe(i-1); end if;
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if rising_edge(clk) then u_pipe(i)<=u_pipe(i-1); end if;
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end process delayChain;
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end process delayChain;
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end generate u_dlyChain;
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end generate u_dlyChain;
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y_pipe(0)<=b(0)*u;
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y_pipe(0)<=b(0)*u;
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y_dlyChain: for i in 1 to y_pipe'high generate
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y_dlyChain: for i in 1 to y_pipe'high generate
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y_pipe(i)<=b(i)*u_pipe(i) + y_pipe(i-1);
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y_pipe(i)<=b(i)*u_pipe(i) + y_pipe(i-1);
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end generate y_dlyChain;
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end generate y_dlyChain;
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y0<=y_pipe(y_pipe'high) when reset='0' else (others=>'0');
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y0<=y_pipe(y_pipe'high) when reset='0' else (others=>'0');
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y<=y0(width-1 downto 0);
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y<=y0(width-1 downto 0);
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end architecture rtl;
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end architecture rtl;
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