# -------------------------------------------------------------------------- #
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# -------------------------------------------------------------------------- #
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#
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#
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# Copyright (C) 1991-2012 Altera Corporation
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# Copyright (C) 1991-2012 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# applicable agreement for further details.
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#
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#
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# -------------------------------------------------------------------------- #
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# -------------------------------------------------------------------------- #
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#
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#
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# Quartus II 32-bit
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# Quartus II 32-bit
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# Version 12.1 Build 177 11/07/2012 SJ Full Version
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# Version 12.1 Build 177 11/07/2012 SJ Full Version
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# Date created = 22:57:28 March 05, 2014
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# Date created = 22:57:28 March 05, 2014
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#
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#
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# -------------------------------------------------------------------------- #
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# -------------------------------------------------------------------------- #
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#
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#
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# Notes:
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# Notes:
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#
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#
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# 1) The default values for assignments are stored in the file:
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# 1) The default values for assignments are stored in the file:
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# fir_assignment_defaults.qdf
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# fir_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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# assignment_defaults.qdf
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#
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#
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# 2) Altera recommends that you do not modify this file. This
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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# and any changes you make may be lost or overwritten.
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#
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#
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# -------------------------------------------------------------------------- #
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE AUTO
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set_global_assignment -name DEVICE AUTO
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set_global_assignment -name TOP_LEVEL_ENTITY tb_fir
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set_global_assignment -name TOP_LEVEL_ENTITY tb_fir
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:57:28 MARCH 05, 2014"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:57:28 MARCH 05, 2014"
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set_global_assignment -name LAST_QUARTUS_VERSION 12.1
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set_global_assignment -name LAST_QUARTUS_VERSION 12.1
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/fir.vhdl"
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set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/tb_fir.vhdl"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/fir.vhdl"
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set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/tb_fir.vhdl"
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set_global_assignment -name VHDL_FILE ../../../tester/stp.vhd
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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No newline at end of file
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No newline at end of file
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