`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company:
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// Engineer:
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// Engineer:
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//
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//
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// Create Date: 19:39:14 08/24/2011
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// Create Date: 19:39:14 08/24/2011
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// Design Name:
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// Design Name:
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// Module Name: divider
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// Module Name: divider
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies:
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module qdiv(
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module qdiv(
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input [N-1:0] dividend,
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input [N-1:0] dividend,
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input [N-1:0] divisor,
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input [N-1:0] divisor,
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input start,
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input start,
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input clk,
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input clk,
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output [N-1:0] quotient_out,
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output [N-1:0] quotient_out,
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output complete
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output complete
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);
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);
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//Parameterized values
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//Parameterized values
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parameter Q = 15;
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parameter Q = 15;
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parameter N = 32;
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parameter N = 32;
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reg [N-1:0] quotient;
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reg [N-1:0] quotient;
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reg [N-1:0] dividend_copy;
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reg [N-1:0] dividend_copy;
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reg [2*(N-1)-1:0] divider_copy;
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reg [2*(N-1)-1:0] divider_copy;
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reg [5:0] bit;
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reg [5:0] bit;
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reg done;
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reg done;
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initial done = 1;
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initial done = 1;
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assign quotient_out = quotient;
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assign quotient_out = quotient;
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assign complete = done;
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assign complete = done;
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always @( posedge clk )
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always @( posedge clk )
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begin
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begin
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if( done && start ) begin
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if( done && start ) begin
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done <= 1'b0;
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done <= 1'b0;
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bit <= N+Q-2;
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bit <= N+Q-2;
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quotient <= 0;
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quotient <= 0;
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dividend_copy <= {1'b0,dividend[N-2:0]};
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dividend_copy <= {1'b0,dividend[N-2:0]};
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divider_copy[2*(N-1)-1] <= 0;
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divider_copy[2*(N-1)-1] <= 0;
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divider_copy[2*(N-1)-2:N-2] <= divisor[N-2:0];
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divider_copy[2*(N-1)-2:N-2] <= divisor[N-2:0];
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divider_copy[N-3:0] <= 0;
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divider_copy[N-3:0] <= 0;
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//set sign bit
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//set sign bit
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if((dividend[N-1] == 1 && divisor[N-1] == 0) || (dividend[N-1] == 0 && divisor[N-1] == 1))
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if((dividend[N-1] == 1 && divisor[N-1] == 0) || (dividend[N-1] == 0 && divisor[N-1] == 1))
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quotient[N-1] <= 1;
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quotient[N-1] <= 1;
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else
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else
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quotient[N-1] <= 0;
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quotient[N-1] <= 0;
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end
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end
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else if(!done) begin
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else if(!done) begin
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//compare divisor/dividend
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//compare divisor/dividend
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if(dividend_copy >= divider_copy) begin
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if(dividend_copy >= divider_copy) begin
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//subtract
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//subtract
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dividend_copy <= dividend_copy - divider_copy;
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dividend_copy <= dividend_copy - divider_copy;
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//set quotient
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//set quotient
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quotient[bit] <= 1'b1;
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quotient[bit] <= 1'b1;
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end
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end
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//reduce divisor
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//reduce divisor
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divider_copy <= divider_copy >> 1;
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divider_copy <= divider_copy >> 1;
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//reduce bit counter
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bit <= bit - 1;
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//stop condition
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//stop condition
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if(dividend_copy == 0)
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if(bit == 0)
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done <= 1'b1;
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done <= 1'b1;
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//reduce bit counter
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bit <= bit - 1;
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end
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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