======================================================================================================
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======================================================================================================
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DP-ICSI log (C implementation of a fast logarithmic approximation unit based on ICSI log V2 0.6 Beta)
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DP-ICSI log (C implementation of a fast logarithmic approximation unit based on ICSI log V2 0.6 Beta)
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DP/SP LAU (FPGA unit that implements the ICSI log algorithm in VHDL)
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DP/SP LAU (FPGA unit that implements the ICSI log algorithm in VHDL)
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======================================================================================================
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======================================================================================================
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Version 0.2 beta
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Version 0.2 beta
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Build date: August 2nd, 2009
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Build date: August 2nd, 2009
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Introduction
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Introduction
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------------
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------------
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Software :
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Software :
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This package contains a C implementation of the ICSI logarithm approximation algorithm originally introduced in
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This package contains a C implementation of the ICSI logarithm approximation algorithm originally introduced in
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O.Vinyals, G.Friedland, A Hardware-Independent Fast Logarithm Approximation with Adjustable Accuracy.
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O.Vinyals, G.Friedland, A Hardware-Independent Fast Logarithm Approximation with Adjustable Accuracy.
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Tenth IEEE International Symposium on Multimedia, 2008. ISM 2008. pp. 61-65, December 2008.
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Tenth IEEE International Symposium on Multimedia, 2008. ISM 2008. pp. 61-65, December 2008.
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The new C function has been adjusted to support double precision inputs in contrast to the official implementation of the algorithm
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The new C function has been adjusted to support double precision inputs in contrast to the official implementation of the algorithm
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which supports only single precision. Furthermore, there is invalid input detection which makes the function fully compatible with
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which supports only single precision. Furthermore, there is invalid input detection which makes the function fully compatible with
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the IEEE 754 standard and the GNU library log() function.
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the IEEE 754 standard and the GNU library log() function.
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Hardware:
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Hardware:
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This package also contains a VHDL implementation of the ICSI logarithm approximation algorithm described in
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This package also contains a VHDL implementation of the ICSI logarithm approximation algorithm described in
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N. Alachiotis, A. Stamatakis: "Efficient Floating-Point Logarithm Unit for FPGAs". Accepted for publication at RAW workshop,
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N. Alachiotis, A. Stamatakis: "Efficient Floating-Point Logarithm Unit for FPGAs". Accepted for publication at RAW workshop,
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held in conjunction with IPDPS 2010, Atlanta, Georgia, April, 2010.
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held in conjunction with IPDPS 2010, Atlanta, Georgia, April, 2010.
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The SP-LAU (Single Precision Logarithm Approximation Unit) implements the algorithm and supports single precision inputs.
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The SP-LAU (Single Precision Logarithm Approximation Unit) implements the algorithm and supports single precision inputs.
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The DP-LAU (Double Precision Logarithm Approximation Unit) implements the algorithm and supports double precision inputs.
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The DP-LAU (Double Precision Logarithm Approximation Unit) implements the algorithm and supports double precision inputs.
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Both units support invalid input detection.
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Both units support invalid input detection.
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All implementations in this package calculate an approximation of the natural logarithm.
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All implementations in this package calculate an approximation of the natural logarithm.
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For more details about the software implementation see the respective readme file and paper for the ICSI log.
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For more details about the software implementation see the respective readme file and paper for the ICSI log.
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Package Structure
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Package Structure
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-----------------
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-----------------
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This package contains the following files and folder:
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This package contains the following files and folder:
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-README : This file
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-README : This file
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-DP-ICSILog/DP-ICSILog.c : C file that contains the adjusted for double precision implementation and an example of how to use the function.
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-DP-ICSILog/DP-ICSILog.c : C file that contains the adjusted for double precision implementation and an example of how to use the function.
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-Virtex 5/SP-LAU : This folder contains the VHDL source files as well as .xco and .ngc files of the IPs that have been used to implement the single precision unit on Virtex 5.
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-Virtex 5/SP-LAU : This folder contains the VHDL source files as well as .xco and .ngc files of the IPs that have been used to implement the single precision unit on Virtex 5.
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-Virtex 5/DP-LAU : This folder contains the VHDL source files as well as .xco and .ngc files of the IPs that have been used to implement the double precision unit on Virtex 5.
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-Virtex 5/DP-LAU : This folder contains the VHDL source files as well as .xco and .ngc files of the IPs that have been used to implement the double precision unit on Virtex 5.
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-Virtex 4/SP-LAU : This folder contains the VHDL source files as well as .xco and .ngc files of the IPs that have been used to implement the single precision unit on Virtex 4.
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-Virtex 4/SP-LAU : This folder contains the VHDL source files as well as .xco and .ngc files of the IPs that have been used to implement the single precision unit on Virtex 4.
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-Virtex 4/DP-LAU : This folder contains the VHDL source files as well as .xco and .ngc files of the IPs that have been used to implement the double precision unit on Virtex 4.
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-Virtex 4/DP-LAU : This folder contains the VHDL source files as well as .xco and .ngc files of the IPs that have been used to implement the double precision unit on Virtex 4.
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-COE Files : This folder contains COE files to be used if one needs to adjust the accuracy of the unit.
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-COE Files : This folder contains COE files to be used if one needs to adjust the accuracy of the unit.
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-PAO Files : This folder contains PAO files that contain the Peripheral Analysis Order for the SP and DP LAUs.
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-PAO Files : This folder contains PAO files that contain the Peripheral Analysis Order for the SP and DP LAUs.
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Usage of the DP-ICSILog
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Usage of the DP-ICSILog
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-----------------------
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-----------------------
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The DP-ICSILog.c file contains the necessay global variables and functions that need to be
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The DP-ICSILog.c file contains the necessay global variables and functions that need to be
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called in order to use the DP-ICSILog function as well as an example.
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called in order to use the DP-ICSILog function as well as an example.
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Interface of the LAU
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Interface of the LAU
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--------------------
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--------------------
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The toplevel module of the LAU is sp_fp_log_v2 for the single precision logarithm approximation unit
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The toplevel module of the LAU is sp_fp_log_v2 for the single precision logarithm approximation unit
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and the dp_fp_log_v2 for double precison.
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and the dp_fp_log_v2 for double precison.
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sp/dp : Single Precision / Double Precision
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sp/dp : Single Precision / Double Precision
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fp : Floating Point
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fp : Floating Point
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log : Logarithm
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log : Logarithm
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V2 : Because the mantissa lookup table has been initialized using the respective function of the ICSILog V2 0.6 Beta software.
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V2 : Because the mantissa lookup table has been initialized using the respective function of the ICSILog V2 0.6 Beta software.
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(The Version 2 of this function doubled the precision of the unit comparing to Version 1)
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(The Version 2 of this function doubled the precision of the unit comparing to Version 1)
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The interface of the unit is defined as follows:
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The interface of the unit is defined as follows:
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entity sp_fp_log_v2/dp_fp_log_v2 is
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entity sp_fp_log_v2/dp_fp_log_v2 is
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Port ( rst : in STD_LOGIC; -- The reset signal
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Port ( rst : in STD_LOGIC; -- The reset signal
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clk : in STD_LOGIC; -- The clock signal
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clk : in STD_LOGIC; -- The clock signal
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valid_in: in STD_LOGIC; -- Signal that indicates valid number at the input port of the unit.
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valid_in: in STD_LOGIC; -- Signal that indicates valid number at the input port of the unit.
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input_val: STD_LOGIC_VECTOR(31/63 downto 0); -- The input number.
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input_val: STD_LOGIC_VECTOR(31/63 downto 0); -- The input number.
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valid_out : STD_LOGIC; -- Signal that indicates valid number at the output port of the unit.
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valid_out : STD_LOGIC; -- Signal that indicates valid number at the output port of the unit.
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output_val : STD_LOGIC_VECTOR(31/63 downto 0) -- The output number, the approximation of the logarithm of the input number.
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output_val : STD_LOGIC_VECTOR(31/63 downto 0) -- The output number, the approximation of the logarithm of the input number.
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);
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);
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end sp_fp_log_v2/dp_fp_log_v2;
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end sp_fp_log_v2/dp_fp_log_v2;
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Implementation Details
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Implementation Details
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----------------------
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----------------------
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The VHDL units have been designed using the Xilinx 10.1 Design Suite.
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The VHDL units have been designed using the Xilinx 10.1 Design Suite.
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ISE 10.1 was used to create the unit.
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ISE 10.1 was used to create the unit.
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Coregen was used to create all the IPs used in this unit.
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Coregen was used to create all the IPs used in this unit.
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The released LAUs use a mantissa lookup table with 4,096 entries.
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The released LAUs use a mantissa lookup table with 4,096 entries.
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Target devices are Virtex 4 and Virtex 5 FPGAs.
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Target devices are Virtex 4 and Virtex 5 FPGAs.
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One needs to change the IPs used in order to use the unit on any FPGA that meets the demands of number of block rams (This number
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One needs to change the IPs used in order to use the unit on any FPGA that meets the demands of number of block rams (This number
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depends on the desired accuracy and thus on the size of the mantissa lookup table) and number of DSP slices (3 DSP slices are occupied).
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depends on the desired accuracy and thus on the size of the mantissa lookup table) and number of DSP slices (3 DSP slices are occupied).
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One can use the coe files in the COE file folder to regenerate the mantissa lookup table for different accuracy and resources occupation.
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One can use the coe files in the COE file folder to regenerate the mantissa lookup table for different accuracy and resources occupation.
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Both units have a latency of 22 cycles (Virtex 5) and 28 cycles (Virtex 4) which is the same irrespective of the size of the mantissa lookup table used and thus the accuracy.
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Both units have a latency of 22 cycles (Virtex 5) and 28 cycles (Virtex 4) which is the same irrespective of the size of the mantissa lookup table used and thus the accuracy.
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The released units occupy 2% of the hardware resources on the Virtex 5 SX95T FPGA and can operate with the following clock frequencies
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The released units occupy 2% of the hardware resources on the Virtex 5 SX95T FPGA and can operate with the following clock frequencies
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as they were reported by the static timing report:
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as they were reported by the static timing report:
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353.4 MHz for the SP-LAU on the V5SX95T-2 and
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353.4 MHz for the SP-LAU on the V5SX95T-2 and
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320.6 MHz for the DP-LAU on the V5SX95T-2 .
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320.6 MHz for the DP-LAU on the V5SX95T-2 .
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Verification Details
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Verification Details
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--------------------
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--------------------
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Modelsim 6.3f was used for extensive post place and route simulations.
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Modelsim 6.3f was used for extensive post place and route simulations.
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The development board HTG-V5-PCIE by HiTech Global populated with a V5SX95T-1 FPGA was used to verify the LAUs.
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The development board HTG-V5-PCIE by HiTech Global populated with a V5SX95T-1 FPGA was used to verify the LAUs.
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ChiScope Pro Analyzer was used for advanced on-chip debugging and verification of the units.
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ChiScope Pro Analyzer was used for advanced on-chip debugging and verification of the units.
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IP Configuration Details for the Virtex 5 LAUs
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IP Configuration Details for the Virtex 5 LAUs
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----------------------------------------------
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----------------------------------------------
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The IPs used for the implementations are the following:
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The IPs used for the implementations are the following:
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(The configuration options that are not mentioned were not selected.)
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(The configuration options that are not mentioned were not selected.)
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comp_eq_000000000000 :
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comp_eq_000000000000 :
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Comparator ,
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Comparator ,
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Operation :A=B,
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Operation :A=B,
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Data Type: Unsigned,
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Data Type: Unsigned,
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Input Width: 12,
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Input Width: 12,
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Port B Constant: 000000000000,
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Port B Constant: 000000000000,
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Pipeline Stages: 0,
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Pipeline Stages: 0,
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Output Options:Registered Output,
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Output Options:Registered Output,
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Synchronous Settings: Clear
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Synchronous Settings: Clear
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comp_eq_000000000000000 :
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comp_eq_000000000000000 :
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Comparator ,
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Comparator ,
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Operation :A=B,
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Operation :A=B,
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Data Type: Unsigned,
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Data Type: Unsigned,
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Input Width: 15,
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Input Width: 15,
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Port B Constant: 000000000000000,
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Port B Constant: 000000000000000,
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Pipeline Stages: 0,
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Pipeline Stages: 0,
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Output Options:Registered Output,
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Output Options:Registered Output,
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Synchronous Settings: Clear
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Synchronous Settings: Clear
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comp_eq_8ones :
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comp_eq_8ones :
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Comparator ,
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Comparator ,
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Operation :A=B,
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Operation :A=B,
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Data Type: Unsigned,
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Data Type: Unsigned,
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Input Width: 8,
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Input Width: 8,
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Port B Constant: 11111111,
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Port B Constant: 11111111,
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Pipeline Stages: 0,
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Pipeline Stages: 0,
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Output Options:Registered Output,
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Output Options:Registered Output,
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Synchronous Settings: Clear
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Synchronous Settings: Clear
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comp_eq_11ones :
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comp_eq_11ones :
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Comparator ,
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Comparator ,
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Operation :A=B,
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Operation :A=B,
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Data Type: Unsigned,
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Data Type: Unsigned,
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Input Width: 11,
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Input Width: 11,
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Port B Constant: 11111111111,
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Port B Constant: 11111111111,
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Pipeline Stages: 0,
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Pipeline Stages: 0,
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Output Options:Registered Output,
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Output Options:Registered Output,
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Synchronous Settings: Clear
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Synchronous Settings: Clear
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comp_eq_22zeros :
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comp_eq_22zeros :
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Comparator ,
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Comparator ,
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Operation :A=B,
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Operation :A=B,
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Data Type: Unsigned,
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Data Type: Unsigned,
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Input Width: 22,
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Input Width: 22,
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Port B Constant: 00000...0000,
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Port B Constant: 00000...0000,
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Pipeline Stages: 0,
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Pipeline Stages: 0,
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Output Options:Registered Output,
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Output Options:Registered Output,
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Synchronous Settings: Clear
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Synchronous Settings: Clear
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comp_eq_51zeros :
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comp_eq_51zeros :
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Comparator ,
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Comparator ,
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Operation :A=B,
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Operation :A=B,
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Data Type: Unsigned,
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Data Type: Unsigned,
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Input Width: 51,
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Input Width: 51,
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Port B Constant: 00000...0000,
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Port B Constant: 00000...0000,
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Pipeline Stages: 0,
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Pipeline Stages: 0,
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Output Options:Registered Output,
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Output Options:Registered Output,
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Synchronous Settings: Clear
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Synchronous Settings: Clear
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comp_eq_111111 :
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comp_eq_111111 :
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Comparator ,
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Comparator ,
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Operation :A=B,
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Operation :A=B,
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Data Type: Unsigned,
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Data Type: Unsigned,
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Input Width: 6,
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Input Width: 6,
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Port B Constant: 111111,
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Port B Constant: 111111,
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Pipeline Stages: 0,
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Pipeline Stages: 0,
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Output Options:Registered Output,
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Output Options:Registered Output,
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Synchronous Settings: Clear
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Synchronous Settings: Clear
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comp_eq_111111111 :
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comp_eq_111111111 :
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Comparator ,
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Comparator ,
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Operation :A=B,
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Operation :A=B,
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Data Type: Unsigned,
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Data Type: Unsigned,
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Input Width: 9,
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Input Width: 9,
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Port B Constant: 111111111,
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Port B Constant: 111111111,
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Pipeline Stages: 0,
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Pipeline Stages: 0,
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Output Options:Registered Output,
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Output Options:Registered Output,
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Synchronous Settings: Clear
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Synchronous Settings: Clear
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exp_lut_MEM :
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exp_lut_MEM :
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Block Memory Generator,
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Block Memory Generator,
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Memory Type: Single Port ROM,
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Memory Type: Single Port ROM,
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Read Width: 9
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Read Width: 9
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Read Depth: 128
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Read Depth: 128
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mant_lut_MEM :
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mant_lut_MEM :
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Block Memory Generator,
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Block Memory Generator,
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Memory Type: Single Port ROM,
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Memory Type: Single Port ROM,
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Read Width: 27
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Read Width: 27
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Read Depth: 4096 (depends on the desired accuracy)
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Read Depth: 4096 (depends on the desired accuracy)
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All the registers used are RAM-based Shift Registers. The width and depth of each register is indicated by the name.
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All the registers used are RAM-based Shift Registers. The width and depth of each register is indicated by the name.
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For example: reg_1b_1c is a register of 1 bit and 1 clock latency.
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For example: reg_1b_1c is a register of 1 bit and 1 clock latency.
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sp_fp_add:
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sp_fp_add:
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Floating Point,
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Floating Point,
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Operation Selection: Add,
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Operation Selection: Add,
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Precision: Single,
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Precision: Single,
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Architecture Optimization: High Speed,
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Architecture Optimization: High Speed,
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Family Optimizations: Full Usage,
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Family Optimizations: Full Usage,
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Latency and Rate Configuration: Use Maximum Latency
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Latency and Rate Configuration: Use Maximum Latency
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sp_fp_mult:
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sp_fp_mult:
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Floating Point,
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Floating Point,
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Operation Selection: Multiply,
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Operation Selection: Multiply,
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Precision: Single,
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Precision: Single,
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Architecture Optimization: High Speed,
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Architecture Optimization: High Speed,
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Family Optimizations: Medium Usage,
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Family Optimizations: Medium Usage,
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Latency and Rate Configuration: Use Maximum Latency
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Latency and Rate Configuration: Use Maximum Latency
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Note:
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Note:
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The Coregen Project Settings were changed from Virtex 5 to Virtex 4 and all the above IPs were regenerated under the current project settings,
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The Coregen Project Settings were changed from Virtex 5 to Virtex 4 and all the above IPs were regenerated under the current project settings,
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except only for the RAM-based Shift Registers that operate in parallel with the sp_fp_add and sp_fp_mult IPs. In this case the depth (clock delay)
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except only for the RAM-based Shift Registers that operate in parallel with the sp_fp_add and sp_fp_mult IPs. In this case the depth (clock delay)
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was changed according to the latency of the sp_fp_add and sp_fp_mult IPs.
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was changed according to the latency of the sp_fp_add and sp_fp_mult IPs.
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Authors and Contact Details
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Authors and Contact Details
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---------------------------
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---------------------------
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Nikos Alachiotis alachiot@in.tum.de
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Nikos Alachiotis alachiot@in.tum.de
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Alexandros Stamatakis stamatak@in.tum.de
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Alexandros Stamatakis stamatak@in.tum.de
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Copyright
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Copyright
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---------
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---------
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These programs are free software; you can redistribute it and/or modify
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These programs are free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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The programs are distributed in the hope that they will be useful,
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The programs are distributed in the hope that they will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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Further Information
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Further Information
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-------------------
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-------------------
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The FPGA units SP-LAU and DP-LAU are exact implementations of the SP-ICSILog and the DP-ICSILog algorithms respectively.
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The FPGA units SP-LAU and DP-LAU are exact implementations of the SP-ICSILog and the DP-ICSILog algorithms respectively.
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Furthermore there is support for invalid input detection like nan, inf, -inf or zero.
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Furthermore there is support for invalid input detection like nan, inf, -inf or zero.
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For more information on the LAU see the paper:
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For more information on the LAU see the paper:
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N. Alachiotis, A. Stamatakis: "Efficient Floating-Point Logarithm Unit for FPGAs". Accepted for publication at RAW workshop,
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N. Alachiotis, A. Stamatakis: "Efficient Floating-Point Logarithm Unit for FPGAs". Accepted for publication at RAW workshop,
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held in conjunction with IPDPS 2010, Atlanta, Georgia, April, 2010.
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held in conjunction with IPDPS 2010, Atlanta, Georgia, April, 2010.
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For more information on the ICSI log algorithm see the paper:
|
For more information on the ICSI log algorithm see the paper:
|
|
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O.Vinyals, G.Friedland, A Hardware-Independent Fast Logarithm Approximation with Adjustable Accuracy.
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O.Vinyals, G.Friedland, A Hardware-Independent Fast Logarithm Approximation with Adjustable Accuracy.
|
Tenth IEEE International Symposium on Multimedia, 2008. ISM 2008. pp. 61-65, December 2008.
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Tenth IEEE International Symposium on Multimedia, 2008. ISM 2008. pp. 61-65, December 2008.
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or/and download the official single precision C implementation from:
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or/and download the official single precision C implementation from:
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http://linux.softpedia.com/get/Programming/Libraries/ICSILog-41333.shtml
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http://linux.softpedia.com/get/Programming/Libraries/ICSILog-41333.shtml
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Citation
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Citation
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--------
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--------
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By using this component you agree to cite it as: "Efficient Floating-Point Logarithm Unit for FPGAs", by Nikos Alachiotis and Alexandros Stamatakis, accapted for publication at RAW workhsop, held in conjunction with IPDPS 2010.
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By using this component you agree to cite it as: "Efficient Floating-Point Logarithm Unit for FPGAs", by Nikos Alachiotis and Alexandros Stamatakis, accapted for publication at RAW workhsop, held in conjunction with IPDPS 2010.
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Release Notes
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Release Notes
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------------
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------------
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Version : 0.2 beta
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Version : 0.2 beta
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Build date : September 20th, 2009
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Build date : September 20th, 2009
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* support for Virtex 4 FPGAs as well
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* support for Virtex 4 FPGAs as well
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* FPGA verification
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* FPGA verification
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Version : 0.1 beta
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Version : 0.1 beta
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Build date : August 2nd, 2009
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Build date : August 2nd, 2009
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* support for Virtex 5 FPGAs only
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* support for Virtex 5 FPGAs only
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* Tested by using extensive post place and route simulations.
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* Tested by using extensive post place and route simulations.
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