# Channel Interface Generator
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# Channel Interface Generator
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import sys
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import sys
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if (len(sys.argv) < 2):
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if (len(sys.argv) < 2):
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print 'Usage: chifgen <#channels>'
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print 'Usage: chifgen <#channels>'
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exit()
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exit()
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numChannels = int(sys.argv[1])
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numChannels = int(sys.argv[1])
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if (numChannels < 1):
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if (numChannels < 1):
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print 'Must have one or more channels'
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print 'Must have one or more channels'
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exit()
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exit()
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f = open('channelif.v', 'w')
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f = open('channelif.v', 'w')
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f.write('''// FCP Channel Interface
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f.write('''// FCP Channel Interface
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module channelif
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module channelif
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(
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(
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// To ethernet platform
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// To ethernet platform
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input in_sof,
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input in_sof,
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input in_eof,
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input in_eof,
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input in_src_rdy,
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input in_src_rdy,
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output in_dst_rdy,
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output in_dst_rdy,
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input [7:0] in_data,
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input [7:0] in_data,
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input [3:0] inport_addr,
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input [3:0] inport_addr,
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output out_sof,
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output out_sof,
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output out_eof,
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output out_eof,
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output out_src_rdy,
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output out_src_rdy,
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input out_dst_rdy,
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input out_dst_rdy,
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output [7:0] out_data,
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output [7:0] out_data,
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input [3:0] outport_addr,
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input [3:0] outport_addr,
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''')
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''')
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for channel in range(1,numChannels+1):
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for channel in range(1,numChannels+1):
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f.write('''// Channel {0:d}
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f.write('''// Channel {0:d}
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input ch{0:d}_in_sof,
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input ch{0:d}_in_sof,
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input ch{0:d}_in_eof,
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input ch{0:d}_in_eof,
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input ch{0:d}_in_src_rdy,
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input ch{0:d}_in_src_rdy,
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output ch{0:d}_in_dst_rdy,
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output ch{0:d}_in_dst_rdy,
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input [7:0] ch{0:d}_in_data,
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input [7:0] ch{0:d}_in_data,
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output ch{0:d}_out_sof,
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output ch{0:d}_out_sof,
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output ch{0:d}_out_eof,
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output ch{0:d}_out_eof,
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output ch{0:d}_out_src_rdy,
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output ch{0:d}_out_src_rdy,
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input ch{0:d}_out_dst_rdy,
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input ch{0:d}_out_dst_rdy,
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output [7:0] ch{0:d}_out_data,
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output [7:0] ch{0:d}_out_data,
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output ch{0:d}_wen,
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output ch{0:d}_wen,
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output ch{0:d}_ren,
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output ch{0:d}_ren,
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'''.format(channel))
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'''.format(channel))
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f.write('''
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f.write('''
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// To user logic
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// To user logic
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output [15:0] wenables,
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output [15:0] wenables,
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output [15:0] renables
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output [15:0] renables
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);
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);
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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// Channel-Enable Decoders
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// Channel-Enable Decoders
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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reg [15:0] wenables_i;
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reg [15:0] wenables_i;
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reg [15:0] renables_i;
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reg [15:0] renables_i;
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always @(inport_addr)
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always @(inport_addr)
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begin
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begin
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case (inport_addr)
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case (inport_addr)
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4'h0 : wenables_i = 16'b0000000000000001;
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4'h0 : wenables_i = 16'b0000000000000001;
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4'h1 : wenables_i = 16'b0000000000000010;
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4'h1 : wenables_i = 16'b0000000000000010;
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4'h2 : wenables_i = 16'b0000000000000100;
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4'h2 : wenables_i = 16'b0000000000000100;
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4'h3 : wenables_i = 16'b0000000000001000;
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4'h3 : wenables_i = 16'b0000000000001000;
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4'h4 : wenables_i = 16'b0000000000010000;
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4'h4 : wenables_i = 16'b0000000000010000;
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4'h5 : wenables_i = 16'b0000000000100000;
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4'h5 : wenables_i = 16'b0000000000100000;
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4'h6 : wenables_i = 16'b0000000001000000;
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4'h6 : wenables_i = 16'b0000000001000000;
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4'h7 : wenables_i = 16'b0000000010000000;
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4'h7 : wenables_i = 16'b0000000010000000;
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4'h8 : wenables_i = 16'b0000000100000000;
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4'h8 : wenables_i = 16'b0000000100000000;
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4'h9 : wenables_i = 16'b0000001000000000;
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4'h9 : wenables_i = 16'b0000001000000000;
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4'hA : wenables_i = 16'b0000010000000000;
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4'hA : wenables_i = 16'b0000010000000000;
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4'hB : wenables_i = 16'b0000100000000000;
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4'hB : wenables_i = 16'b0000100000000000;
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4'hC : wenables_i = 16'b0001000000000000;
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4'hC : wenables_i = 16'b0001000000000000;
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4'hD : wenables_i = 16'b0010000000000000;
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4'hD : wenables_i = 16'b0010000000000000;
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4'hE : wenables_i = 16'b0100000000000000;
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4'hE : wenables_i = 16'b0100000000000000;
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4'hF : wenables_i = 16'b1000000000000000;
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4'hF : wenables_i = 16'b1000000000000000;
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default: wenables_i = 16'b0000000000000000;
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default: wenables_i = 16'b0000000000000000;
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endcase
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endcase
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end
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end
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always @(outport_addr)
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always @(outport_addr)
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begin
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begin
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case (outport_addr)
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case (outport_addr)
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4'h0 : renables_i = 16'b0000000000000001;
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4'h0 : renables_i = 16'b0000000000000001;
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4'h1 : renables_i = 16'b0000000000000010;
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4'h1 : renables_i = 16'b0000000000000010;
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4'h2 : renables_i = 16'b0000000000000100;
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4'h2 : renables_i = 16'b0000000000000100;
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4'h3 : renables_i = 16'b0000000000001000;
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4'h3 : renables_i = 16'b0000000000001000;
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4'h4 : renables_i = 16'b0000000000010000;
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4'h4 : renables_i = 16'b0000000000010000;
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4'h5 : renables_i = 16'b0000000000100000;
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4'h5 : renables_i = 16'b0000000000100000;
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4'h6 : renables_i = 16'b0000000001000000;
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4'h6 : renables_i = 16'b0000000001000000;
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4'h7 : renables_i = 16'b0000000010000000;
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4'h7 : renables_i = 16'b0000000010000000;
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4'h8 : renables_i = 16'b0000000100000000;
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4'h8 : renables_i = 16'b0000000100000000;
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4'h9 : renables_i = 16'b0000001000000000;
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4'h9 : renables_i = 16'b0000001000000000;
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4'hA : renables_i = 16'b0000010000000000;
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4'hA : renables_i = 16'b0000010000000000;
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4'hB : renables_i = 16'b0000100000000000;
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4'hB : renables_i = 16'b0000100000000000;
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4'hC : renables_i = 16'b0001000000000000;
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4'hC : renables_i = 16'b0001000000000000;
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4'hD : renables_i = 16'b0010000000000000;
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4'hD : renables_i = 16'b0010000000000000;
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4'hE : renables_i = 16'b0100000000000000;
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4'hE : renables_i = 16'b0100000000000000;
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4'hF : renables_i = 16'b1000000000000000;
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4'hF : renables_i = 16'b1000000000000000;
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default: renables_i = 16'b0000000000000000;
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default: renables_i = 16'b0000000000000000;
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endcase
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endcase
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end
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end
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assign wenables = wenables_i;
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assign wenables = wenables_i;
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assign renables = renables_i;
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assign renables = renables_i;
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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// Multiplexers
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// Multiplexers
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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assign in_dst_rdy = (ch1_wen & ch1_out_dst_rdy)''')
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assign in_dst_rdy = (ch1_wen & ch1_out_dst_rdy)''')
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for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_wen & ch{0:d}_out_dst_rdy)'.format(channel))
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for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_wen & ch{0:d}_out_dst_rdy)'.format(channel))
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f.write(''';
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f.write(''';
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assign out_sof = (ch1_ren & ch1_in_sof)''')
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assign out_sof = (ch1_ren & ch1_in_sof)''')
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for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_ren & ch{0:d}_in_sof)'.format(channel))
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for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_ren & ch{0:d}_in_sof)'.format(channel))
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f.write(''';
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f.write(''';
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assign out_eof = (ch1_ren & ch1_in_eof)''')
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assign out_eof = (ch1_ren & ch1_in_eof)''')
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for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_ren & ch{0:d}_in_eof)'.format(channel))
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for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_ren & ch{0:d}_in_eof)'.format(channel))
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f.write(''';
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f.write(''';
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assign out_src_rdy = (ch1_ren & ch1_in_src_rdy)''')
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assign out_src_rdy = (ch1_ren & ch1_in_src_rdy)''')
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for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_ren & ch{0:d}_in_src_rdy)'.format(channel))
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for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_ren & ch{0:d}_in_src_rdy)'.format(channel))
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f.write(''';
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f.write(''';
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assign out_data = ({8{ch1_ren}} & ch1_in_data)''')
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assign out_data = ({8{ch1_ren}} & ch1_in_data)''')
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for channel in range(2, numChannels+1): f.write(' | ({{8{{ch{0:d}_ren}}}} & ch{0:d}_in_data)'.format(channel))
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for channel in range(2, numChannels+1): f.write(' | ({{8{{ch{0:d}_ren}}}} & ch{0:d}_in_data)'.format(channel))
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f.write(''';
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f.write(''';
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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// Passthroughs
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// Passthroughs
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------
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''')
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''')
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for channel in range(1, numChannels+1): f.write('''
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for channel in range(1, numChannels+1): f.write('''
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assign ch{0:d}_in_dst_rdy = out_dst_rdy;
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assign ch{0:d}_in_dst_rdy = out_dst_rdy & ch{0:d}_ren;
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assign ch{0:d}_out_src_rdy = in_src_rdy;
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assign ch{0:d}_out_src_rdy = in_src_rdy & ch{0:d}_wen;
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assign ch{0:d}_out_sof = in_sof;
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assign ch{0:d}_out_sof = in_sof;
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assign ch{0:d}_out_eof = in_eof;
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assign ch{0:d}_out_eof = in_eof;
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assign ch{0:d}_out_data = in_data;
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assign ch{0:d}_out_data = in_data;
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assign ch{0:d}_wen = wenables_i[{0:d}];
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assign ch{0:d}_wen = wenables_i[{0:d}];
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assign ch{0:d}_ren = renables_i[{0:d}];
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assign ch{0:d}_ren = renables_i[{0:d}];
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'''.format(channel))
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'''.format(channel))
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f.write('''
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f.write('''
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endmodule
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endmodule
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''')
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''')
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