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/* --------------------------------------------------------------------------------
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This file is part of FPGA Median Filter.
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FPGA Median Filter is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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FPGA Median Filter is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>.
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-------------------------------------------------------------------------------- */
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// +----------------------------------------------------------------------------
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// +----------------------------------------------------------------------------
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// Universidade Federal da Bahia
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// Universidade Federal da Bahia
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// PROJECT: FPGA Median Filter
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// PROJECT: FPGA Median Filter
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// FILE NAME : pixel_network.v
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// FILE NAME : pixel_network.v
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// AUTHOR : João Carlos Bittencourt
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// AUTHOR : João Carlos Bittencourt
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// AUTHOR'S E-MAIL : joaocarlos@ieee.org
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// AUTHOR'S E-MAIL : joaocarlos@ieee.org
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// RELEASE HISTORY
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// RELEASE HISTORY
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// VERSION DATE AUTHOR DESCRIPTION
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// VERSION DATE AUTHOR DESCRIPTION
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// 1.0 2013-08-13 joao.nunes initial version
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// 1.0 2013-08-13 joao.nunes initial version
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// KEYWORDS: dff, flip-flop, register bank
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// KEYWORDS: dff, flip-flop, register bank
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// PURPOSE: Group median pipeline registers.
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// PURPOSE: Group median pipeline registers.
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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module dff_3_pipe
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module dff_3_pipe
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#(
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#(
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parameter DATA_WIDTH = 8
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parameter DATA_WIDTH = 8
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)(
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)(
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input clk,
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input clk,
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input rst_n,
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input rst_n,
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input [DATA_WIDTH-1:0] d0,
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input [DATA_WIDTH-1:0] d0,
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input [DATA_WIDTH-1:0] d1,
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input [DATA_WIDTH-1:0] d1,
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input [DATA_WIDTH-1:0] d2,
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input [DATA_WIDTH-1:0] d2,
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output reg [DATA_WIDTH-1:0] q0,
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output reg [DATA_WIDTH-1:0] q0,
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output reg [DATA_WIDTH-1:0] q1,
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output reg [DATA_WIDTH-1:0] q1,
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output reg [DATA_WIDTH-1:0] q2
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output reg [DATA_WIDTH-1:0] q2
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);
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);
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always @(posedge clk or negedge rst_n)
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always @(posedge clk or negedge rst_n)
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begin : register_bank_3u
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begin : register_bank_3u
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if(~rst_n) begin
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if(~rst_n) begin
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q0 <= {DATA_WIDTH{1'b0}};
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q0 <= {DATA_WIDTH{1'b0}};
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q1 <= {DATA_WIDTH{1'b0}};
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q1 <= {DATA_WIDTH{1'b0}};
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q2 <= {DATA_WIDTH{1'b0}};
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q2 <= {DATA_WIDTH{1'b0}};
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end else begin
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end else begin
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q0 <= d0;
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q0 <= d0;
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q1 <= d1;
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q1 <= d1;
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q2 <= d2;
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q2 <= d2;
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end
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end
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end
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end
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