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/* --------------------------------------------------------------------------------
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This file is part of FPGA Median Filter.
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FPGA Median Filter is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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FPGA Median Filter is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>.
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-------------------------------------------------------------------------------- */
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//*******************************************************************//
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//*******************************************************************//
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//-------------------------------------------------------------------//
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//-------------------------------------------------------------------//
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// File name : dual_port_ram.v
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// File name : dual_port_ram.v
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// File contents : Parameterized memory for syncronous fifo
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// File contents : Parameterized memory for syncronous fifo
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//
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//
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// Design Engineer : Igor Dantas
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// Design Engineer : Igor Dantas
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// Last Changed : 10/27/2008 09:00
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// Last Changed : 10/27/2008 09:00
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//-------------------------------------------------------------------//
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//-------------------------------------------------------------------//
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//*******************************************************************//
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//*******************************************************************//
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module dual_port_ram
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module dual_port_ram
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#(
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#(
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parameter MEMFILE = "",
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parameter MEMFILE = "",
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parameter DATA_WIDTH = 'd32,
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parameter DATA_WIDTH = 'd32,
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parameter ADDR_WIDTH = 14
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parameter ADDR_WIDTH = 14
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)
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)
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(
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(
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input clk,
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input clk,
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input r_ena,
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input r_ena,
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input w_ena,
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input w_ena,
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input [DATA_WIDTH-1:0] w_data,
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input [DATA_WIDTH-1:0] w_data,
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input [ADDR_WIDTH-1:0] w_addr,
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input [ADDR_WIDTH-1:0] w_addr,
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input [ADDR_WIDTH-1:0] r_addr,
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input [ADDR_WIDTH-1:0] r_addr,
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output reg [DATA_WIDTH-1:0] r_data
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output reg [DATA_WIDTH-1:0] r_data
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);
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);
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//The Register memory
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//The Register memory
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reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
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reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
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// synchronous read and write when enabled
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// synchronous read and write when enabled
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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if (w_ena) mem[w_addr] <= w_data;
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if (w_ena) mem[w_addr] <= w_data;
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if (r_ena) r_data <= mem[r_addr];
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if (r_ena) r_data <= mem[r_addr];
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end
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end
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initial $readmemh(MEMFILE, mem);
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initial $readmemh(MEMFILE, mem);
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endmodule
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endmodule
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