// +----------------------------------------------------------------------------
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/* --------------------------------------------------------------------------------
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// Universidade Federal da Bahia
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This file is part of FPGA Median Filter.
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//------------------------------------------------------------------------------
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// PROJECT: FPGA Median Filter
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FPGA Median Filter is free software: you can redistribute it and/or modify
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//------------------------------------------------------------------------------
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it under the terms of the GNU General Public License as published by
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// FILE NAME : median.v
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the Free Software Foundation, either version 3 of the License, or
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// AUTHOR : João Carlos Bittencourt
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(at your option) any later version.
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// AUTHOR'S E-MAIL : joaocarlos@ieee.org
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// -----------------------------------------------------------------------------
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FPGA Median Filter is distributed in the hope that it will be useful,
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// RELEASE HISTORY
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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// VERSION DATE AUTHOR DESCRIPTION
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// 1.0 2013-08-13 joao.nunes initial version
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GNU General Public License for more details.
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// -----------------------------------------------------------------------------
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// KEYWORDS: median, filter, image processing
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You should have received a copy of the GNU General Public License
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// -----------------------------------------------------------------------------
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along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>.
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// PURPOSE: Top level entity of the Median Filter algorithm datapath.
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-------------------------------------------------------------------------------- */
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// -----------------------------------------------------------------------------
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/* +----------------------------------------------------------------------------
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Universidade Federal da Bahia
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------------------------------------------------------------------------------
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PROJECT: FPGA Median Filter
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------------------------------------------------------------------------------
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FILE NAME : median.v
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AUTHOR : João Carlos Bittencourt
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AUTHOR'S E-MAIL : joaocarlos@ieee.org
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-----------------------------------------------------------------------------
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RELEASE HISTORY
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VERSION DATE AUTHOR DESCRIPTION
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1.0 2013-08-13 joao.nunes initial version
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-----------------------------------------------------------------------------
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KEYWORDS: median, filter, image processing
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-----------------------------------------------------------------------------
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PURPOSE: Top level entity of the Median Filter algorithm datapath.
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----------------------------------------------------------------------------- */
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`define DEBUG
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`define DEBUG
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|
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module median
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module median
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#(
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#(
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parameter MEM_DATA_WIDTH = 32,
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parameter MEM_DATA_WIDTH = 32,
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parameter LUT_ADDR_WIDTH = 10, // Input LUTs
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parameter LUT_ADDR_WIDTH = 10, // Input LUTs
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parameter MEM_ADDR_WIDTH = 10, // Output Memory
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parameter MEM_ADDR_WIDTH = 10, // Output Memory
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parameter PIXEL_DATA_WIDTH = 8,
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parameter PIXEL_DATA_WIDTH = 8,
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parameter IMG_WIDTH = 320,
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parameter IMG_WIDTH = 320,
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parameter IMG_HEIGHT = 320
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parameter IMG_HEIGHT = 320
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)(
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)(
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input clk, // Clock
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input clk, // Clock
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input rst_n, // Asynchronous reset active low
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input rst_n, // Asynchronous reset active low
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input [31:0] word0,
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input [31:0] word0,
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input [31:0] word1,
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input [31:0] word1,
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input [31:0] word2,
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input [31:0] word2,
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|
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// Test signals
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// Test signals
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`ifdef DEBUG
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`ifdef DEBUG
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output [PIXEL_DATA_WIDTH-1:0] pixel1,
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output [PIXEL_DATA_WIDTH-1:0] pixel1,
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output [PIXEL_DATA_WIDTH-1:0] pixel2,
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output [PIXEL_DATA_WIDTH-1:0] pixel2,
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output [PIXEL_DATA_WIDTH-1:0] pixel3,
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output [PIXEL_DATA_WIDTH-1:0] pixel3,
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output [PIXEL_DATA_WIDTH-1:0] pixel4,
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output [PIXEL_DATA_WIDTH-1:0] pixel4,
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`else
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`else
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output [MEM_DATA_WIDTH-1:0] median_word,
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output [MEM_DATA_WIDTH-1:0] median_word,
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`endif
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`endif
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output [LUT_ADDR_WIDTH-1:0] raddr_a,
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output [LUT_ADDR_WIDTH-1:0] raddr_a,
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output [LUT_ADDR_WIDTH-1:0] raddr_b,
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output [LUT_ADDR_WIDTH-1:0] raddr_b,
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output [LUT_ADDR_WIDTH-1:0] raddr_c,
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output [LUT_ADDR_WIDTH-1:0] raddr_c,
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|
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output [MEM_ADDR_WIDTH-1:0] waddr
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output [MEM_ADDR_WIDTH-1:0] waddr
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);
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);
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|
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wire [PIXEL_DATA_WIDTH-1:0] x2_y1;
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wire [PIXEL_DATA_WIDTH-1:0] x2_y1;
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wire [PIXEL_DATA_WIDTH-1:0] x2_y0;
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wire [PIXEL_DATA_WIDTH-1:0] x2_y0;
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wire [PIXEL_DATA_WIDTH-1:0] x2_ym1;
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wire [PIXEL_DATA_WIDTH-1:0] x2_ym1;
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wire [PIXEL_DATA_WIDTH-1:0] x1_y1;
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wire [PIXEL_DATA_WIDTH-1:0] x1_y1;
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wire [PIXEL_DATA_WIDTH-1:0] x1_y0;
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wire [PIXEL_DATA_WIDTH-1:0] x1_y0;
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wire [PIXEL_DATA_WIDTH-1:0] x1_ym1;
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wire [PIXEL_DATA_WIDTH-1:0] x1_ym1;
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wire [PIXEL_DATA_WIDTH-1:0] x0_y1;
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wire [PIXEL_DATA_WIDTH-1:0] x0_y1;
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wire [PIXEL_DATA_WIDTH-1:0] x0_y0;
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wire [PIXEL_DATA_WIDTH-1:0] x0_y0;
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wire [PIXEL_DATA_WIDTH-1:0] x0_ym1;
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wire [PIXEL_DATA_WIDTH-1:0] x0_ym1;
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wire [PIXEL_DATA_WIDTH-1:0] xm1_y1;
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wire [PIXEL_DATA_WIDTH-1:0] xm1_y1;
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wire [PIXEL_DATA_WIDTH-1:0] xm1_y0;
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wire [PIXEL_DATA_WIDTH-1:0] xm1_y0;
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wire [PIXEL_DATA_WIDTH-1:0] xm1_ym1;
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wire [PIXEL_DATA_WIDTH-1:0] xm1_ym1;
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|
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assign x2_y1 = word0[PIXEL_DATA_WIDTH-1:0];
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assign x2_y1 = word0[PIXEL_DATA_WIDTH-1:0];
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assign x2_y0 = word1[PIXEL_DATA_WIDTH-1:0];
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assign x2_y0 = word1[PIXEL_DATA_WIDTH-1:0];
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assign x2_ym1 = word2[PIXEL_DATA_WIDTH-1:0];
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assign x2_ym1 = word2[PIXEL_DATA_WIDTH-1:0];
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|
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assign x1_y1 = word0[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
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assign x1_y1 = word0[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
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assign x1_y0 = word1[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
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assign x1_y0 = word1[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
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assign x1_ym1 = word2[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
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assign x1_ym1 = word2[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
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assign x0_y1 = word0[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
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assign x0_y1 = word0[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
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assign x0_y0 = word1[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
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assign x0_y0 = word1[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
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assign x0_ym1 = word2[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
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assign x0_ym1 = word2[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
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assign xm1_y1 = word0[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
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assign xm1_y1 = word0[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
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assign xm1_y0 = word1[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
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assign xm1_y0 = word1[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
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assign xm1_ym1 = word2[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
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assign xm1_ym1 = word2[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
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// wire [PIXEL_DATA_WIDTH-1:0] pixel1_sig;
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// wire [PIXEL_DATA_WIDTH-1:0] pixel1_sig;
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// wire [PIXEL_DATA_WIDTH-1:0] pixel2_sig;
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// wire [PIXEL_DATA_WIDTH-1:0] pixel2_sig;
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// wire [PIXEL_DATA_WIDTH-1:0] pixel3_sig;
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// wire [PIXEL_DATA_WIDTH-1:0] pixel3_sig;
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// wire [PIXEL_DATA_WIDTH-1:0] pixel4_sig;
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// wire [PIXEL_DATA_WIDTH-1:0] pixel4_sig;
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|
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`ifndef DEBUG
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`ifndef DEBUG
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assign median_word = {pixel1,pixel2,pixel3,pixel4};
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assign median_word = {pixel1,pixel2,pixel3,pixel4};
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`endif
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`endif
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// Common network output signals
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// Common network output signals
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wire [PIXEL_DATA_WIDTH-1:0] c3l;
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wire [PIXEL_DATA_WIDTH-1:0] c3l;
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wire [PIXEL_DATA_WIDTH-1:0] c3h;
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wire [PIXEL_DATA_WIDTH-1:0] c3h;
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wire [PIXEL_DATA_WIDTH-1:0] c3m;
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wire [PIXEL_DATA_WIDTH-1:0] c3m;
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wire [PIXEL_DATA_WIDTH-1:0] c3l_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c3l_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c3h_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c3h_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c3m_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c3m_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c2l;
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wire [PIXEL_DATA_WIDTH-1:0] c2l;
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wire [PIXEL_DATA_WIDTH-1:0] c2h;
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wire [PIXEL_DATA_WIDTH-1:0] c2h;
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wire [PIXEL_DATA_WIDTH-1:0] c2m;
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wire [PIXEL_DATA_WIDTH-1:0] c2m;
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wire [PIXEL_DATA_WIDTH-1:0] c2l_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c2l_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c2h_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c2h_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c2m_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c2m_reg;
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wire [PIXEL_DATA_WIDTH-1:0] c1l;
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wire [PIXEL_DATA_WIDTH-1:0] c1l;
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wire [PIXEL_DATA_WIDTH-1:0] c1h;
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wire [PIXEL_DATA_WIDTH-1:0] c1h;
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wire [PIXEL_DATA_WIDTH-1:0] c1m;
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wire [PIXEL_DATA_WIDTH-1:0] c1m;
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wire [PIXEL_DATA_WIDTH-1:0] c0h;
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wire [PIXEL_DATA_WIDTH-1:0] c0h;
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wire [PIXEL_DATA_WIDTH-1:0] c0m;
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wire [PIXEL_DATA_WIDTH-1:0] c0m;
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wire [PIXEL_DATA_WIDTH-1:0] c0l;
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wire [PIXEL_DATA_WIDTH-1:0] c0l;
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|
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// Delay signals to be placed over the output registers
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// Delay signals to be placed over the output registers
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wire [PIXEL_DATA_WIDTH-1:0] p1_sig;
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wire [PIXEL_DATA_WIDTH-1:0] p1_sig;
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wire [PIXEL_DATA_WIDTH-1:0] p2_sig;
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wire [PIXEL_DATA_WIDTH-1:0] p2_sig;
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wire [PIXEL_DATA_WIDTH-1:0] p3_sig;
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wire [PIXEL_DATA_WIDTH-1:0] p3_sig;
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|
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Windowing Memory Address Controller
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// Windowing Memory Address Controller
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//------------------------------------------------------------
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//------------------------------------------------------------
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state_machine
|
state_machine
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#(
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#(
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.LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),
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.LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),
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.IMG_WIDTH(IMG_WIDTH),
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.IMG_WIDTH(IMG_WIDTH),
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.IMG_HEIGHT(IMG_HEIGHT)
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.IMG_HEIGHT(IMG_HEIGHT)
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) window_contol (
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) window_contol (
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.clk(clk), // Clock
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.clk(clk), // Clock
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.rst_n(rst_n), // Asynchronous reset active low
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.rst_n(rst_n), // Asynchronous reset active low
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|
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.raddr_a(raddr_a),
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.raddr_a(raddr_a),
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.raddr_b(raddr_b),
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.raddr_b(raddr_b),
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.raddr_c(raddr_c),
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.raddr_c(raddr_c),
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|
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.waddr(waddr)
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.waddr(waddr)
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);
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);
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|
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Pixel registers
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// Pixel registers
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//------------------------------------------------------------
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//------------------------------------------------------------
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// always @(posedge clk or negedge rst_n)
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// always @(posedge clk or negedge rst_n)
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// begin : pixel_reg
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// begin : pixel_reg
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// if(~rst_n) begin
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// if(~rst_n) begin
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// pixel1 <= {PIXEL_DATA_WIDTH{1'b0}};
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// pixel1 <= {PIXEL_DATA_WIDTH{1'b0}};
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// pixel2 <= {PIXEL_DATA_WIDTH{1'b0}};
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// pixel2 <= {PIXEL_DATA_WIDTH{1'b0}};
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// pixel3 <= {PIXEL_DATA_WIDTH{1'b0}};
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// pixel3 <= {PIXEL_DATA_WIDTH{1'b0}};
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// pixel4 <= {PIXEL_DATA_WIDTH{1'b0}};
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// pixel4 <= {PIXEL_DATA_WIDTH{1'b0}};
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// end else begin
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// end else begin
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// pixel1 <= pixel1_sig;
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// pixel1 <= pixel1_sig;
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// pixel2 <= pixel2_sig;
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// pixel2 <= pixel2_sig;
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// pixel3 <= pixel3_sig;
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// pixel3 <= pixel3_sig;
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// //pixel4 <= pixel4_sig;
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// //pixel4 <= pixel4_sig;
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// end
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// end
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// end
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// end
|
|
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Input datapath common network
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// Input datapath common network
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//------------------------------------------------------------
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//------------------------------------------------------------
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common_network
|
common_network
|
#(
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#(
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.DATA_WIDTH(PIXEL_DATA_WIDTH)
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.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
) common_network_u0 (
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) common_network_u0 (
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.x2_y1(x2_y1),
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.x2_y1(x2_y1),
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.x2_y0(x2_y0),
|
.x2_y0(x2_y0),
|
.x2_ym1(x2_ym1),
|
.x2_ym1(x2_ym1),
|
.x1_y1(x1_y1),
|
.x1_y1(x1_y1),
|
.x1_y0(x1_y0),
|
.x1_y0(x1_y0),
|
.x1_ym1(x1_ym1),
|
.x1_ym1(x1_ym1),
|
.x0_y1(x0_y1),
|
.x0_y1(x0_y1),
|
.x0_y0(x0_y0),
|
.x0_y0(x0_y0),
|
.x0_ym1(x0_ym1),
|
.x0_ym1(x0_ym1),
|
.xm1_y1(xm1_y1),
|
.xm1_y1(xm1_y1),
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.xm1_y0(xm1_y0),
|
.xm1_y0(xm1_y0),
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.xm1_ym1(xm1_ym1),
|
.xm1_ym1(xm1_ym1),
|
|
|
.c3l(c3l),
|
.c3l(c3l),
|
.c3h(c3h),
|
.c3h(c3h),
|
.c3m(c3m),
|
.c3m(c3m),
|
.c2l(c2l),
|
.c2l(c2l),
|
.c2h(c2h),
|
.c2h(c2h),
|
.c2m(c2m),
|
.c2m(c2m),
|
.c1l(c1l),
|
.c1l(c1l),
|
.c1h(c1h),
|
.c1h(c1h),
|
.c1m(c1m),
|
.c1m(c1m),
|
.c0h(c0h),
|
.c0h(c0h),
|
.c0m(c0m),
|
.c0m(c0m),
|
.c0l(c0l)
|
.c0l(c0l)
|
);
|
);
|
|
|
//------------------------------------------------------------
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//------------------------------------------------------------
|
// Pipeline Registers
|
// Pipeline Registers
|
//------------------------------------------------------------
|
//------------------------------------------------------------
|
dff_3_pipe
|
dff_3_pipe
|
#(
|
#(
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
) dff_c3_pipe (
|
) dff_c3_pipe (
|
.clk(clk),
|
.clk(clk),
|
.rst_n(rst_n),
|
.rst_n(rst_n),
|
.d0(c3h),
|
.d0(c3h),
|
.d1(c3m),
|
.d1(c3m),
|
.d2(c3l),
|
.d2(c3l),
|
|
|
.q0(c3h_reg),
|
.q0(c3h_reg),
|
.q1(c3m_reg),
|
.q1(c3m_reg),
|
.q2(c3l_reg)
|
.q2(c3l_reg)
|
);
|
);
|
|
|
dff_3_pipe
|
dff_3_pipe
|
#(
|
#(
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
) dff_c2_pipe (
|
) dff_c2_pipe (
|
.clk(clk),
|
.clk(clk),
|
.rst_n(rst_n),
|
.rst_n(rst_n),
|
.d0(c2h),
|
.d0(c2h),
|
.d1(c2m),
|
.d1(c2m),
|
.d2(c2l),
|
.d2(c2l),
|
|
|
.q0(c2h_reg),
|
.q0(c2h_reg),
|
.q1(c2m_reg),
|
.q1(c2m_reg),
|
.q2(c2l_reg)
|
.q2(c2l_reg)
|
);
|
);
|
|
|
// Output pieline registers (P1, P2, P3)
|
// Output pieline registers (P1, P2, P3)
|
dff_3_pipe
|
dff_3_pipe
|
#(
|
#(
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
) dff_out_pipe (
|
) dff_out_pipe (
|
.clk(clk),
|
.clk(clk),
|
.rst_n(rst_n),
|
.rst_n(rst_n),
|
.d0(p1_sig),
|
.d0(p1_sig),
|
.d1(p2_sig),
|
.d1(p2_sig),
|
.d2(p3_sig),
|
.d2(p3_sig),
|
|
|
.q0(pixel1),
|
.q0(pixel1),
|
.q1(pixel2),
|
.q1(pixel2),
|
.q2(pixel3)
|
.q2(pixel3)
|
);
|
);
|
|
|
//------------------------------------------------------------
|
//------------------------------------------------------------
|
// Median Filter Pixel Network
|
// Median Filter Pixel Network
|
//------------------------------------------------------------
|
//------------------------------------------------------------
|
|
|
// Pixel 1
|
// Pixel 1
|
pixel_network
|
pixel_network
|
#(
|
#(
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
) pixel_network_u0 (
|
) pixel_network_u0 (
|
.c3h(c1h),
|
.c3h(c1h),
|
.c3m(c1m),
|
.c3m(c1m),
|
.c3l(c1l),
|
.c3l(c1l),
|
.c2h(c0h),
|
.c2h(c0h),
|
.c2m(c0m),
|
.c2m(c0m),
|
.c2l(c0l),
|
.c2l(c0l),
|
.c1h(c3h_reg),
|
.c1h(c3h_reg),
|
.c1m(c3m_reg),
|
.c1m(c3m_reg),
|
.c1l(c3l_reg),
|
.c1l(c3l_reg),
|
|
|
.median(p1_sig)
|
.median(p1_sig)
|
);
|
);
|
|
|
pixel_network
|
pixel_network
|
#(
|
#(
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
) pixel_network_u1 (
|
) pixel_network_u1 (
|
.c3h(c2h),
|
.c3h(c2h),
|
.c3m(c2m),
|
.c3m(c2m),
|
.c3l(c2l),
|
.c3l(c2l),
|
.c2h(c1h),
|
.c2h(c1h),
|
.c2m(c1m),
|
.c2m(c1m),
|
.c2l(c1l),
|
.c2l(c1l),
|
.c1h(c0h),
|
.c1h(c0h),
|
.c1m(c0m),
|
.c1m(c0m),
|
.c1l(c0l),
|
.c1l(c0l),
|
|
|
.median(p2_sig)
|
.median(p2_sig)
|
);
|
);
|
|
|
pixel_network
|
pixel_network
|
#(
|
#(
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
) pixel_network_u2 (
|
) pixel_network_u2 (
|
.c3h(c3h),
|
.c3h(c3h),
|
.c3m(c3m),
|
.c3m(c3m),
|
.c3l(c3l),
|
.c3l(c3l),
|
.c2h(c2h),
|
.c2h(c2h),
|
.c2m(c2m),
|
.c2m(c2m),
|
.c2l(c2l),
|
.c2l(c2l),
|
.c1h(c1h),
|
.c1h(c1h),
|
.c1m(c1m),
|
.c1m(c1m),
|
.c1l(c1l),
|
.c1l(c1l),
|
|
|
.median(p3_sig)
|
.median(p3_sig)
|
);
|
);
|
|
|
pixel_network
|
pixel_network
|
#(
|
#(
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
.DATA_WIDTH(PIXEL_DATA_WIDTH)
|
) pixel_network_u3 (
|
) pixel_network_u3 (
|
.c3h(c0h),
|
.c3h(c0h),
|
.c3m(c0m),
|
.c3m(c0m),
|
.c3l(c0l),
|
.c3l(c0l),
|
.c2h(c3h_reg),
|
.c2h(c3h_reg),
|
.c2m(c3m_reg),
|
.c2m(c3m_reg),
|
.c2l(c3l_reg),
|
.c2l(c3l_reg),
|
.c1h(c2h_reg),
|
.c1h(c2h_reg),
|
.c1m(c2m_reg),
|
.c1m(c2m_reg),
|
.c1l(c2l_reg),
|
.c1l(c2l_reg),
|
|
|
.median(pixel4)
|
.median(pixel4)
|
);
|
);
|
|
|
|
|