OpenCores
URL https://opencores.org/ocsvn/fpga-median/fpga-median/trunk

Subversion Repositories fpga-median

[/] [fpga-median/] [trunk/] [rtl/] [node.v] - Diff between revs 2 and 9

Only display areas with differences | Details | Blame | View Log

Rev 2 Rev 9
// +----------------------------------------------------------------------------
/* --------------------------------------------------------------------------------
// Universidade Federal da Bahia
 This file is part of FPGA Median Filter.
//------------------------------------------------------------------------------
 
// PROJECT: FPGA Median Filter
    FPGA Median Filter is free software: you can redistribute it and/or modify
//------------------------------------------------------------------------------
    it under the terms of the GNU General Public License as published by
// FILE NAME            : node.v
    the Free Software Foundation, either version 3 of the License, or
// AUTHOR               : João Carlos Bittencourt
    (at your option) any later version.
// AUTHOR'S E-MAIL      : joaocarlos@ieee.org
 
// -----------------------------------------------------------------------------
    FPGA Median Filter is distributed in the hope that it will be useful,
// RELEASE HISTORY
    but WITHOUT ANY WARRANTY; without even the implied warranty of
// VERSION  DATE        AUTHOR        DESCRIPTION
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// 1.0      2013-08-13  joao.nunes    initial version
    GNU General Public License for more details.
// -----------------------------------------------------------------------------
 
// KEYWORDS: comparator, low, hight, median
    You should have received a copy of the GNU General Public License
// -----------------------------------------------------------------------------
    along with FPGA Median Filter.  If not, see <http://www.gnu.org/licenses/>.
// PURPOSE: Compare two input values and return the low and high values.
-------------------------------------------------------------------------------- */
// -----------------------------------------------------------------------------
/* +----------------------------------------------------------------------------
 
   Universidade Federal da Bahia
 
  ------------------------------------------------------------------------------
 
   PROJECT: FPGA Median Filter
 
  ------------------------------------------------------------------------------
 
   FILE NAME            : node.v
 
   AUTHOR               : João Carlos Bittencourt
 
   AUTHOR'S E-MAIL      : joaocarlos@ieee.org
 
   -----------------------------------------------------------------------------
 
   RELEASE HISTORY
 
   VERSION  DATE        AUTHOR        DESCRIPTION
 
   1.0      2013-08-13  joao.nunes    initial version
 
   -----------------------------------------------------------------------------
 
   KEYWORDS: comparator, low, hight, median
 
   -----------------------------------------------------------------------------
 
   PURPOSE: Compare two input values and return the low and high values.
 
   ----------------------------------------------------------------------------- */
module node
module node
#(
#(
    parameter DATA_WIDTH = 8,
    parameter DATA_WIDTH = 8,
    parameter LOW_MUX = 1, // disable low output
    parameter LOW_MUX = 1, // disable low output
    parameter HI_MUX = 1 // disable hight output
    parameter HI_MUX = 1 // disable hight output
)(
)(
    input [DATA_WIDTH-1:0] data_a,
    input [DATA_WIDTH-1:0] data_a,
    input [DATA_WIDTH-1:0] data_b,
    input [DATA_WIDTH-1:0] data_b,
 
 
    output reg [DATA_WIDTH-1:0] data_hi,
    output reg [DATA_WIDTH-1:0] data_hi,
    output reg [DATA_WIDTH-1:0] data_lo
    output reg [DATA_WIDTH-1:0] data_lo
);
);
 
 
 
 
    reg sel0;
    reg sel0;
 
 
    always @(*)
    always @(*)
    begin : comparator
    begin : comparator
        if(data_a < data_b) begin
        if(data_a < data_b) begin
            sel0 = 1'b0; // data_a : lo / data_b : hi
            sel0 = 1'b0; // data_a : lo / data_b : hi
        end else begin
        end else begin
            sel0 = 1'b1; // data_b : lo / data_a : hi
            sel0 = 1'b1; // data_b : lo / data_a : hi
        end
        end
    end
    end
 
 
 
 
    always @(*)
    always @(*)
    begin : mux_lo_hi
    begin : mux_lo_hi
        case (sel0)
        case (sel0)
            1'b0 :
            1'b0 :
            begin
            begin
                if(LOW_MUX == 1)
                if(LOW_MUX == 1)
                    data_lo = data_a;
                    data_lo = data_a;
                if(HI_MUX == 1)
                if(HI_MUX == 1)
                    data_hi = data_b;
                    data_hi = data_b;
            end
            end
            1'b1 :
            1'b1 :
            begin
            begin
                if(LOW_MUX == 1)
                if(LOW_MUX == 1)
                    data_lo = data_b;
                    data_lo = data_b;
                if(HI_MUX == 1)
                if(HI_MUX == 1)
                    data_hi = data_a;
                    data_hi = data_a;
            end
            end
            default :
            default :
            begin
            begin
                data_lo = {DATA_WIDTH{1'b0}};
                data_lo = {DATA_WIDTH{1'b0}};
                data_hi = {DATA_WIDTH{1'b0}};
                data_hi = {DATA_WIDTH{1'b0}};
            end
            end
        endcase
        endcase
    end
    end
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.