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/* --------------------------------------------------------------------------------
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This file is part of FPGA Median Filter.
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FPGA Median Filter is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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FPGA Median Filter is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FPGA Median Filter. If not, see .
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-------------------------------------------------------------------------------- */
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// +----------------------------------------------------------------------------
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// +----------------------------------------------------------------------------
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// Universidade Federal da Bahia
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// Universidade Federal da Bahia
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// PROJECT: FPGA Median Filter
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// PROJECT: FPGA Median Filter
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// FILE NAME : median_tb.v
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// FILE NAME : median_tb.v
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// AUTHOR : João Carlos Bittencourt
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// AUTHOR : João Carlos Bittencourt
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// AUTHOR'S E-MAIL : joaocarlos@ieee.org
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// AUTHOR'S E-MAIL : joaocarlos@ieee.org
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// RELEASE HISTORY
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// RELEASE HISTORY
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// VERSION DATE AUTHOR DESCRIPTION
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// VERSION DATE AUTHOR DESCRIPTION
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// 1.0 2013-08-27 joao.nunes initial version
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// 1.0 2013-08-27 joao.nunes initial version
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// 1.1 2013-09-04 laue.rami modified version
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// 1.1 2013-09-04 laue.rami modified version
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// KEYWORDS: median, filter, image processing
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// KEYWORDS: median, filter, image processing
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// PURPOSE: Testbench for Median filter.
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// PURPOSE: Testbench for Median filter.
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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`define IMG_HEIGHT 'd320
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`define IMG_HEIGHT 'd320
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`define IMG_WIDTH 'd320
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`define IMG_WIDTH 'd320
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module median_tb;
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module median_tb;
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`include "../tb/driver.sv"
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`include "../tb/driver.sv"
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driver driver_u0;
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driver driver_u0;
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localparam PERIOD = 10;
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localparam PERIOD = 10;
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localparam PIXEL_DATA_WIDTH = 8;
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localparam PIXEL_DATA_WIDTH = 8;
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localparam LUT_ADDR_WIDTH = 14; // Input LUTs
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localparam LUT_ADDR_WIDTH = 14; // Input LUTs
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localparam MEM_ADDR_WIDTH = 14; // Output Memory
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localparam MEM_ADDR_WIDTH = 14; // Output Memory
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bit clk;
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bit clk;
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wire [MEM_ADDR_WIDTH-1:0] raddr_a;
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wire [MEM_ADDR_WIDTH-1:0] raddr_a;
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wire [MEM_ADDR_WIDTH-1:0] raddr_b;
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wire [MEM_ADDR_WIDTH-1:0] raddr_b;
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wire [MEM_ADDR_WIDTH-1:0] raddr_c;
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wire [MEM_ADDR_WIDTH-1:0] raddr_c;
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wire [MEM_ADDR_WIDTH-1:0] waddr_a;
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wire [MEM_ADDR_WIDTH-1:0] waddr_a;
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wire [MEM_ADDR_WIDTH-1:0] waddr_b;
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wire [MEM_ADDR_WIDTH-1:0] waddr_b;
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wire [MEM_ADDR_WIDTH-1:0] waddr_c;
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wire [MEM_ADDR_WIDTH-1:0] waddr_c;
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wire [MEM_ADDR_WIDTH-1:0] waddr;
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wire [MEM_ADDR_WIDTH-1:0] waddr;
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reg [(PIXEL_DATA_WIDTH*4)-1:0] word0;
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reg [(PIXEL_DATA_WIDTH*4)-1:0] word0;
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reg [(PIXEL_DATA_WIDTH*4)-1:0] word1;
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reg [(PIXEL_DATA_WIDTH*4)-1:0] word1;
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reg [(PIXEL_DATA_WIDTH*4)-1:0] word2;
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reg [(PIXEL_DATA_WIDTH*4)-1:0] word2;
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wire [31:0] w_data_bram0;
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wire [31:0] w_data_bram0;
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wire [31:0] w_data_bram1;
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wire [31:0] w_data_bram1;
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wire [31:0] w_data_bram2;
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wire [31:0] w_data_bram2;
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//dut_if interface
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//dut_if interface
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dut_if dut_if (clk);
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dut_if dut_if (clk);
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//driver
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//driver
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always #(PERIOD/2) clk = ~clk;
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always #(PERIOD/2) clk = ~clk;
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dual_port_ram
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dual_port_ram
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#(
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#(
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.MEMFILE("./memA.hex"),
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.MEMFILE("./memA.hex"),
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.DATA_WIDTH('d32),
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.DATA_WIDTH('d32),
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.ADDR_WIDTH('d14)
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.ADDR_WIDTH('d14)
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)
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)
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BRAM0
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BRAM0
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(
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(
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.clk(clk),
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.clk(clk),
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.r_ena(1'b1),
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.r_ena(1'b1),
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.w_ena(1'b0),
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.w_ena(1'b0),
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.w_data(w_data_bram0),
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.w_data(w_data_bram0),
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.w_addr(waddr_a),
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.w_addr(waddr_a),
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.r_addr(raddr_a),
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.r_addr(raddr_a),
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.r_data(dut_if.word0)
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.r_data(dut_if.word0)
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);
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);
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dual_port_ram
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dual_port_ram
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#(
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#(
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.MEMFILE("./memB.hex"),
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.MEMFILE("./memB.hex"),
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.DATA_WIDTH('d32),
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.DATA_WIDTH('d32),
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.ADDR_WIDTH('d14)
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.ADDR_WIDTH('d14)
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)
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)
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BRAM1
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BRAM1
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(
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(
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.clk(clk),
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.clk(clk),
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.r_ena(1'b1),
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.r_ena(1'b1),
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.w_ena(1'b0),
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.w_ena(1'b0),
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.w_data(w_data_bram1),
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.w_data(w_data_bram1),
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.w_addr(waddr_b),
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.w_addr(waddr_b),
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.r_addr(raddr_b),
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.r_addr(raddr_b),
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.r_data(dut_if.word1)
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.r_data(dut_if.word1)
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);
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);
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dual_port_ram
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dual_port_ram
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#(
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#(
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.MEMFILE("./memC.hex"),
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.MEMFILE("./memC.hex"),
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.DATA_WIDTH('d32),
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.DATA_WIDTH('d32),
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.ADDR_WIDTH('d14)
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.ADDR_WIDTH('d14)
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)
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)
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BRAM2
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BRAM2
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(
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(
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.clk(clk),
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.clk(clk),
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.r_ena(1'b1),
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.r_ena(1'b1),
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.w_ena(1'b0),
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.w_ena(1'b0),
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.w_data(w_data_bram2),
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.w_data(w_data_bram2),
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.w_addr(waddr_c),
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.w_addr(waddr_c),
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.r_addr(raddr_c),
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.r_addr(raddr_c),
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.r_data(dut_if.word2)
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.r_data(dut_if.word2)
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);
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);
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median
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median
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#(
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#(
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.MEM_DATA_WIDTH(PIXEL_DATA_WIDTH*4),
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.MEM_DATA_WIDTH(PIXEL_DATA_WIDTH*4),
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.PIXEL_DATA_WIDTH(PIXEL_DATA_WIDTH),
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.PIXEL_DATA_WIDTH(PIXEL_DATA_WIDTH),
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.LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),
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.LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),
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.MEM_ADDR_WIDTH(MEM_ADDR_WIDTH),
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.MEM_ADDR_WIDTH(MEM_ADDR_WIDTH),
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.IMG_WIDTH(`IMG_WIDTH),
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.IMG_WIDTH(`IMG_WIDTH),
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.IMG_HEIGHT(`IMG_HEIGHT)
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.IMG_HEIGHT(`IMG_HEIGHT)
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) dut_u0 (
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) dut_u0 (
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.clk(clk), // Clock
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.clk(clk), // Clock
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.rst_n(dut_if.rst_n), // Asynchronous reset active low
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.rst_n(dut_if.rst_n), // Asynchronous reset active low
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.word0(dut_if.ch_word0),
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.word0(dut_if.ch_word0),
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.word1(dut_if.ch_word1),
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.word1(dut_if.ch_word1),
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.word2(dut_if.ch_word2),
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.word2(dut_if.ch_word2),
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.pixel1(dut_if.pixel1),
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.pixel1(dut_if.pixel1),
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.pixel2(dut_if.pixel2),
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.pixel2(dut_if.pixel2),
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.pixel3(dut_if.pixel3),
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.pixel3(dut_if.pixel3),
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.pixel4(dut_if.pixel4),
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.pixel4(dut_if.pixel4),
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.raddr_a(raddr_a),
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.raddr_a(raddr_a),
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.raddr_b(raddr_b),
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.raddr_b(raddr_b),
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.raddr_c(raddr_c),
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.raddr_c(raddr_c),
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.waddr(dut_if.waddr)
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.waddr(dut_if.waddr)
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);
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);
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always@(*)begin
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always@(*)begin
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dut_if.window_line_counter = dut_u0.window_contol.window_line_counter;
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dut_if.window_line_counter = dut_u0.window_contol.window_line_counter;
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end
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end
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initial begin
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initial begin
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$display("INICIO -------");
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$display("INICIO -------");
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driver_u0 = new(dut_if);
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driver_u0 = new(dut_if);
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driver_u0.init();
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driver_u0.init();
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driver_u0.receive_data();
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driver_u0.receive_data();
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driver_u0.reorganize_lines();
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driver_u0.reorganize_lines();
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wait(dut_if.end_of_operation);
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wait(dut_if.end_of_operation);
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driver_u0.write_file();
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driver_u0.write_file();
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#(PERIOD*3)
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#(PERIOD*3)
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repeat(100)@(negedge clk);
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repeat(100)@(negedge clk);
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$stop;
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$stop;
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end
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end
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endmodule
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endmodule
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