/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
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//// FPU ////
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//// FPU ////
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//// Floating Point Unit (Single precision) ////
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//// Floating Point Unit (Single precision) ////
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//// ////
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//// ////
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//// TEST BENCH ////
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//// TEST BENCH ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Rudolf Usselmann ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
|
//// ////
|
//// ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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`timescale 1ns / 100ps
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module test;
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module test;
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reg clk;
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reg clk;
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reg [31:0] opa;
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reg [31:0] opa;
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reg [31:0] opb;
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reg [31:0] opb;
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wire [3:0] sum;
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wire [3:0] sum;
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wire inf, snan, qnan;
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wire inf, snan, qnan;
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wire div_by_zero;
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wire div_by_zero;
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wire altb, blta, aeqb;
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wire altb, blta, aeqb;
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wire unordered;
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wire unordered;
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reg [3:0] exp;
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reg [3:0] exp;
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reg [31:0] opa1;
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reg [31:0] opa1;
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reg [31:0] opb1;
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reg [31:0] opb1;
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reg [2:0] fpu_op;
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reg [2:0] fpu_op;
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reg [3:0] rmode;
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reg [3:0] rmode;
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reg start;
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reg start;
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reg [75:0] tmem[0:500000];
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reg [75:0] tmem[0:500000];
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reg [75:0] tmp;
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reg [75:0] tmp;
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reg [7:0] oper;
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reg [7:0] oper;
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reg [7:0] exc;
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reg [7:0] exc;
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integer i;
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integer i;
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wire ine;
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wire ine;
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reg match;
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reg match;
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wire overflow, underflow;
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wire overflow, underflow;
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wire zero;
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wire zero;
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reg exc_err;
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reg exc_err;
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reg m0, m1, m2;
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reg m0, m1, m2;
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reg [1:0] fpu_rmode;
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reg [1:0] fpu_rmode;
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reg [3:0] test_rmode;
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reg [3:0] test_rmode;
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reg [4:0] test_sel;
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reg [4:0] test_sel;
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reg fp_fasu;
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reg fp_fasu;
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reg fp_mul;
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reg fp_mul;
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reg fp_div;
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reg fp_div;
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reg fp_combo;
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reg fp_combo;
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reg fp_i2f;
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reg fp_i2f;
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reg fp_0fcmp;
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reg fp_0fcmp;
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reg test_exc;
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reg test_exc;
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reg show_prog;
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reg show_prog;
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event error_event;
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event error_event;
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integer error, vcount;
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integer error, vcount;
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always #50 clk = ~clk;
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always #50 clk = ~clk;
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initial
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initial
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begin
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begin
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$display ("\n\nFloating Point Compare Version 1.0\n\n");
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$display ("\n\nFloating Point Compare Version 1.0\n\n");
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clk = 0;
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clk = 0;
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start = 0;
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start = 0;
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error = 0;
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error = 0;
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vcount = 0;
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vcount = 0;
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show_prog = 0;
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show_prog = 0;
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test_exc = 1;
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test_exc = 1;
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test_sel = 5'b11111;
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test_sel = 5'b11111;
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@(posedge clk);
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@(posedge clk);
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$display("\n\nTesting FP CMP Unit\n");
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$display("\n\nTesting FP CMP Unit\n");
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if(test_sel[0])
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if(test_sel[0])
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begin
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begin
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$display("\nRunning Pat 0 Test ...\n");
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$display("\nRunning Pat 0 Test ...\n");
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$readmemh ("../test_vectors/fcmp/fcmp_pat0.hex", tmem);
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$readmemh ("../test_vectors/fcmp/fcmp_pat0.hex", tmem);
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run_test;
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run_test;
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end
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end
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if(test_sel[1])
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if(test_sel[1])
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begin
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begin
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$display("\nRunning Pat 1 Test ...\n");
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$display("\nRunning Pat 1 Test ...\n");
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$readmemh ("../test_vectors/fcmp/fcmp_pat1.hex", tmem);
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$readmemh ("../test_vectors/fcmp/fcmp_pat1.hex", tmem);
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run_test;
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run_test;
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end
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end
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if(test_sel[2])
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if(test_sel[2])
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begin
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begin
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$display("\nRunning Pat 2 Test ...\n");
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$display("\nRunning Pat 2 Test ...\n");
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$readmemh ("../test_vectors/fcmp/fcmp_pat2.hex", tmem);
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$readmemh ("../test_vectors/fcmp/fcmp_pat2.hex", tmem);
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run_test;
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run_test;
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end
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end
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if(test_sel[3])
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if(test_sel[3])
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begin
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begin
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$display("\nRunning Random Lg. Num Test ...\n");
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$display("\nRunning Random Lg. Num Test ...\n");
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$readmemh ("../test_vectors/fcmp/fcmp_lg.hex", tmem);
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$readmemh ("../test_vectors/fcmp/fcmp_lg.hex", tmem);
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run_test;
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run_test;
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end
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end
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if(test_sel[4])
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if(test_sel[4])
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begin
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begin
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$display("\nRunning Random Sm. Num Test ...\n");
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$display("\nRunning Random Sm. Num Test ...\n");
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$readmemh ("../test_vectors/fcmp/fcmp_sm.hex", tmem);
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$readmemh ("../test_vectors/fcmp/fcmp_sm.hex", tmem);
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run_test;
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run_test;
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end
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end
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repeat (4) @(posedge clk);
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repeat (4) @(posedge clk);
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$display("\n\n");
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$display("\n\n");
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$display("\n\nAll test Done !\n\n");
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$display("\n\nAll test Done !\n\n");
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$display("Run %0d vecors, found %0d errors.\n\n",vcount, error);
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$display("Run %0d vecors, found %0d errors.\n\n",vcount, error);
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$finish;
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$finish;
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end
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end
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task run_test;
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task run_test;
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begin
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begin
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@(posedge clk);
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@(posedge clk);
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#1;
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#1;
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opa = 32'h0;
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opa = 32'h0;
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opb = 32'hx;
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opb = 32'hx;
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@(posedge clk);
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@(posedge clk);
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#1;
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#1;
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i=0;
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i=0;
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while( |opa !== 1'bx )
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while( |opa !== 1'bx )
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begin
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begin
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@(posedge clk);
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@(posedge clk);
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#1;
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#1;
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start = 1;
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start = 1;
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tmp = tmem[i];
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tmp = tmem[i];
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exc = tmp[75:68];
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exc = tmp[75:68];
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opa = tmp[67:36];
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opa = tmp[67:36];
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opb = tmp[35:04];
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opb = tmp[35:04];
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exp = exc==0 ? tmp[03:00] : 0;
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exp = exc==0 ? tmp[03:00] : 0;
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if(show_prog) $write("Vector: %d\015",i);
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if(show_prog) $write("Vector: %d\015",i);
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i= i+1;
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i= i+1;
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end
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end
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start = 0;
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start = 0;
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@(posedge clk);
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@(posedge clk);
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#1;
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#1;
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opa = 32'hx;
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opa = 32'hx;
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opb = 32'hx;
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opb = 32'hx;
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fpu_rmode = 2'hx;
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fpu_rmode = 2'hx;
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@(posedge clk);
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@(posedge clk);
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#1;
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#1;
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for(i=0;i<500000;i=i+1) // Clear Memory
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for(i=0;i<500000;i=i+1) // Clear Memory
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tmem[i] = 76'hxxxxxxxxxxxxxxxxx;
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tmem[i] = 76'hxxxxxxxxxxxxxxxxx;
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end
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end
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endtask
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endtask
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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#3;
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#3;
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// Floating Point Exceptions ( exc4 )
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// Floating Point Exceptions ( exc4 )
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// -------------------------
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// -------------------------
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// float_flag_invalid = 1,
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// float_flag_invalid = 1,
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// float_flag_divbyzero = 4,
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// float_flag_divbyzero = 4,
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// float_flag_overflow = 8,
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// float_flag_overflow = 8,
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// float_flag_underflow = 16,
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// float_flag_underflow = 16,
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// float_flag_inexact = 32
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// float_flag_inexact = 32
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exc_err=0;
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exc_err=0;
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if(test_exc)
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if(test_exc)
|
begin
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begin
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|
|
if(exc[5])
|
if(exc[5])
|
begin
|
begin
|
exc_err=1;
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exc_err=1;
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$display("\nERROR: INE Exception: Expected: 0, Got 1\n");
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$display("\nERROR: INE Exception: Expected: 0, Got 1\n");
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end
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end
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if(exc[3])
|
if(exc[3])
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begin
|
begin
|
exc_err=1;
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exc_err=1;
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$display("\nERROR: Overflow Exception: Expected: 0, Got 1\n");
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$display("\nERROR: Overflow Exception: Expected: 0, Got 1\n");
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end
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end
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if(exc[4])
|
if(exc[4])
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begin
|
begin
|
exc_err=1;
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exc_err=1;
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$display("\nERROR: Underflow Exception: Expected: 0, Got 1\n");
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$display("\nERROR: Underflow Exception: Expected: 0, Got 1\n");
|
end
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end
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|
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if(zero !== !(|opa[30:0]))
|
if(zero !== !(|opa[30:0]))
|
begin
|
begin
|
exc_err=1;
|
exc_err=1;
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$display("\nERROR: Zero Detection Failed. ZERO: %h, Sum: %h\n", zero, opa);
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$display("\nERROR: Zero Detection Failed. ZERO: %h, Sum: %h\n", zero, opa);
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end
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end
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if(inf !== (((opa[30:23] == 8'hff) & ((|opa[22:0]) == 1'b0)) | ((opb[30:23] == 8'hff) & ((|opb[22:0]) == 1'b0))) )
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if(inf !== (((opa[30:23] == 8'hff) & ((|opa[22:0]) == 1'b0)) | ((opb[30:23] == 8'hff) & ((|opb[22:0]) == 1'b0))) )
|
begin
|
begin
|
exc_err=1;
|
exc_err=1;
|
$display("\nERROR: INF Detection Failed. INF: %h, Sum: %h\n", inf, sum);
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$display("\nERROR: INF Detection Failed. INF: %h, Sum: %h\n", inf, sum);
|
end
|
end
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|
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if(unordered !== ( ( &opa[30:23] & |opa[22:0]) | ( &opb[30:23] & |opb[22:0]) ) )
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if(unordered !== ( ( &opa[30:23] & |opa[22:0]) | ( &opb[30:23] & |opb[22:0]) ) )
|
begin
|
begin
|
exc_err=1;
|
exc_err=1;
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$display("\nERROR: UNORDERED Detection Failed. SNAN: %h, OpA: %h, OpB: %h\n", snan, opa, opb);
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$display("\nERROR: UNORDERED Detection Failed. SNAN: %h, OpA: %h, OpB: %h\n", snan, opa, opb);
|
end
|
end
|
|
|
end
|
end
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|
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m0 = ( (|sum) !== 1'b1) & ( (|sum) !== 1'b0); // result unknown (ERROR)
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m0 = ( (|sum) !== 1'b1) & ( (|sum) !== 1'b0); // result unknown (ERROR)
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m1 = (exp === sum) ; // results are equal
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m1 = (exp === sum) ; // results are equal
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|
|
match = m1;
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match = m1;
|
|
|
if( (exc_err | !match | m0) & start )
|
if( (exc_err | !match | m0) & start )
|
begin
|
begin
|
$display("\n%t: ERROR: output mismatch. Expected %h, Got %h (%h)", $time, exp, sum, {opa, opb, exp} );
|
$display("\n%t: ERROR: output mismatch. Expected %h, Got %h (%h)", $time, exp, sum, {opa, opb, exp} );
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$write("opa:\t"); disp_fp(opa);
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$write("opa:\t"); disp_fp(opa);
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$write("opb:\t"); disp_fp(opb);
|
$write("opb:\t"); disp_fp(opb);
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$display("EXP:\t%b",exp);
|
$display("EXP:\t%b",exp);
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$display("GOT:\t%b",sum);
|
$display("GOT:\t%b",sum);
|
$display("\n");
|
$display("\n");
|
|
|
error = error + 1;
|
error = error + 1;
|
end
|
end
|
|
|
if(start) vcount = vcount + 1;
|
if(start) vcount = vcount + 1;
|
|
|
if(error > 10)
|
if(error > 10)
|
begin
|
begin
|
@(posedge clk);
|
@(posedge clk);
|
$display("\n\nFound to many errors, aborting ...\n\n");
|
$display("\n\nFound to many errors, aborting ...\n\n");
|
$display("Run %0d vecors, found %0d errors.\n\n",vcount, error);
|
$display("Run %0d vecors, found %0d errors.\n\n",vcount, error);
|
$finish;
|
$finish;
|
end
|
end
|
end
|
end
|
|
|
assign sum = {1'b0, altb, blta, aeqb};
|
assign sum = {1'b0, altb, blta, aeqb};
|
|
|
fcmp u0(opa, opb, unordered, altb, blta, aeqb, inf, zero );
|
fcmp u0(opa, opb, unordered, altb, blta, aeqb, inf, zero );
|
|
|
task disp_fp;
|
task disp_fp;
|
input [31:0] fp;
|
input [31:0] fp;
|
|
|
reg [63:0] x;
|
reg [63:0] x;
|
reg [7:0] exp;
|
reg [7:0] exp;
|
|
|
begin
|
begin
|
|
|
exp = fp[30:23];
|
exp = fp[30:23];
|
if(exp==8'h7f) $write("(%h %h ( 00 ) %h) ",fp[31], exp, fp[22:0]);
|
if(exp==8'h7f) $write("(%h %h ( 00 ) %h) ",fp[31], exp, fp[22:0]);
|
else
|
else
|
if(exp>8'h7f) $write("(%h %h (+%d ) %h) ",fp[31], exp, exp-8'h7f, fp[22:0]);
|
if(exp>8'h7f) $write("(%h %h (+%d ) %h) ",fp[31], exp, exp-8'h7f, fp[22:0]);
|
else $write("(%h %h (-%d ) %h) ",fp[31], exp, 8'h7f-exp, fp[22:0]);
|
else $write("(%h %h (-%d ) %h) ",fp[31], exp, 8'h7f-exp, fp[22:0]);
|
|
|
|
|
x[51:0] = {fp[22:0], 29'h0};
|
x[51:0] = {fp[22:0], 29'h0};
|
x[63] = fp[31];
|
x[63] = fp[31];
|
x[62] = fp[30];
|
x[62] = fp[30];
|
x[61:59] = {fp[29], fp[29], fp[29]};
|
x[61:59] = {fp[29], fp[29], fp[29]};
|
x[58:52] = fp[29:23];
|
x[58:52] = fp[29:23];
|
|
|
$display("\t%f",$bitstoreal(x));
|
$display("\t%f",$bitstoreal(x));
|
end
|
end
|
|
|
endtask
|
endtask
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|
endmodule
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endmodule
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