/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Pre Normalize ////
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//// Pre Normalize ////
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//// Pre Normalization Unit for Add/Sub Operations ////
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//// Pre Normalization Unit for Add/Sub Operations ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer.////
|
//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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`timescale 1ns / 100ps
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|
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module pre_norm(clk, rmode, add, opa, opb, opa_nan, opb_nan, fracta_out,
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module pre_norm(clk, rmode, add, opa, opb, opa_nan, opb_nan, fracta_out,
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fractb_out, exp_dn_out, sign, nan_sign, result_zero_sign,
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fractb_out, exp_dn_out, sign, nan_sign, result_zero_sign,
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fasu_op);
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fasu_op);
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input clk;
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input clk;
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input [1:0] rmode;
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input [1:0] rmode;
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input add;
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input add;
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input [31:0] opa, opb;
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input [31:0] opa, opb;
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input opa_nan, opb_nan;
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input opa_nan, opb_nan;
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output [26:0] fracta_out, fractb_out;
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output [26:0] fracta_out, fractb_out;
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output [7:0] exp_dn_out;
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output [7:0] exp_dn_out;
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output sign;
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output sign;
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output nan_sign, result_zero_sign;
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output nan_sign, result_zero_sign;
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output fasu_op; // Operation Output
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output fasu_op; // Operation Output
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|
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires and registers
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// Local Wires and registers
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//
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//
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wire signa, signb; // alias to opX sign
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wire signa, signb; // alias to opX sign
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wire [7:0] expa, expb; // alias to opX exponent
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wire [7:0] expa, expb; // alias to opX exponent
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wire [22:0] fracta, fractb; // alias to opX fraction
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wire [22:0] fracta, fractb; // alias to opX fraction
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wire expa_lt_expb; // expa is larger than expb indicator
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wire expa_lt_expb; // expa is larger than expb indicator
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wire fractb_lt_fracta; // fractb is larger than fracta indicator
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wire fractb_lt_fracta; // fractb is larger than fracta indicator
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reg [7:0] exp_dn_out; // de normalized exponent output
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reg [7:0] exp_dn_out; // de normalized exponent output
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wire [7:0] exp_small, exp_large;
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wire [7:0] exp_small, exp_large;
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wire [7:0] exp_diff; // Numeric difference of the two exponents
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wire [7:0] exp_diff; // Numeric difference of the two exponents
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wire [22:0] adj_op; // Fraction adjustment: input
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wire [22:0] adj_op; // Fraction adjustment: input
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wire [26:0] adj_op_tmp;
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wire [26:0] adj_op_tmp;
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wire [26:0] adj_op_out; // Fraction adjustment: output
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wire [26:0] adj_op_out; // Fraction adjustment: output
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wire [26:0] fracta_n, fractb_n; // Fraction selection after normalizing
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wire [26:0] fracta_n, fractb_n; // Fraction selection after normalizing
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wire [26:0] fracta_s, fractb_s; // Fraction Sorting out
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wire [26:0] fracta_s, fractb_s; // Fraction Sorting out
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reg [26:0] fracta_out, fractb_out; // Fraction Output
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reg [26:0] fracta_out, fractb_out; // Fraction Output
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reg sign, sign_d; // Sign Output
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reg sign, sign_d; // Sign Output
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reg add_d; // operation (add/sub)
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reg add_d; // operation (add/sub)
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reg fasu_op; // operation (add/sub) register
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reg fasu_op; // operation (add/sub) register
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wire expa_dn, expb_dn;
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wire expa_dn, expb_dn;
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reg sticky;
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reg sticky;
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reg result_zero_sign;
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reg result_zero_sign;
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reg add_r, signa_r, signb_r;
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reg add_r, signa_r, signb_r;
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wire [4:0] exp_diff_sft;
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wire [4:0] exp_diff_sft;
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wire exp_lt_27;
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wire exp_lt_27;
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wire op_dn;
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wire op_dn;
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wire [26:0] adj_op_out_sft;
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wire [26:0] adj_op_out_sft;
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reg fracta_lt_fractb, fracta_eq_fractb;
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reg fracta_lt_fractb, fracta_eq_fractb;
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wire nan_sign1;
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wire nan_sign1;
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reg nan_sign;
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reg nan_sign;
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Aliases
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// Aliases
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//
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//
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assign signa = opa[31];
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assign signa = opa[31];
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assign signb = opb[31];
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assign signb = opb[31];
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assign expa = opa[30:23];
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assign expa = opa[30:23];
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assign expb = opb[30:23];
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assign expb = opb[30:23];
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assign fracta = opa[22:0];
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assign fracta = opa[22:0];
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assign fractb = opb[22:0];
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assign fractb = opb[22:0];
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//
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//
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// Pre-Normalize exponents (and fractions)
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// Pre-Normalize exponents (and fractions)
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//
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//
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assign expa_lt_expb = expa > expb; // expa is larger than expb
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assign expa_lt_expb = expa > expb; // expa is larger than expb
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Normalize
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// Normalize
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assign expa_dn = !(|expa); // opa denormalized
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assign expa_dn = !(|expa); // opa denormalized
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assign expb_dn = !(|expb); // opb denormalized
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assign expb_dn = !(|expb); // opb denormalized
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Calculate the difference between the smaller and larger exponent
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// Calculate the difference between the smaller and larger exponent
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wire [7:0] exp_diff1, exp_diff1a, exp_diff2;
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wire [7:0] exp_diff1, exp_diff1a, exp_diff2;
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assign exp_small = expa_lt_expb ? expb : expa;
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assign exp_small = expa_lt_expb ? expb : expa;
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assign exp_large = expa_lt_expb ? expa : expb;
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assign exp_large = expa_lt_expb ? expa : expb;
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assign exp_diff1 = exp_large - exp_small;
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assign exp_diff1 = exp_large - exp_small;
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assign exp_diff1a = exp_diff1-1;
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assign exp_diff1a = exp_diff1-1;
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assign exp_diff2 = (expa_dn | expb_dn) ? exp_diff1a : exp_diff1;
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assign exp_diff2 = (expa_dn | expb_dn) ? exp_diff1a : exp_diff1;
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assign exp_diff = (expa_dn & expb_dn) ? 8'h0 : exp_diff2;
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assign exp_diff = (expa_dn & expb_dn) ? 8'h0 : exp_diff2;
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always @(posedge clk) // If numbers are equal we should return zero
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always @(posedge clk) // If numbers are equal we should return zero
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exp_dn_out <= #1 (!add_d & expa==expb & fracta==fractb) ? 8'h0 : exp_large;
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exp_dn_out <= #1 (!add_d & expa==expb & fracta==fractb) ? 8'h0 : exp_large;
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Adjust the smaller fraction
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// Adjust the smaller fraction
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assign op_dn = expa_lt_expb ? expb_dn : expa_dn;
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assign op_dn = expa_lt_expb ? expb_dn : expa_dn;
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assign adj_op = expa_lt_expb ? fractb : fracta;
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assign adj_op = expa_lt_expb ? fractb : fracta;
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assign adj_op_tmp = { ~op_dn, adj_op, 3'b0 }; // recover hidden bit (op_dn)
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assign adj_op_tmp = { ~op_dn, adj_op, 3'b0 }; // recover hidden bit (op_dn)
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// adj_op_out is 27 bits wide, so can only be shifted 27 bits to the right
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// adj_op_out is 27 bits wide, so can only be shifted 27 bits to the right
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assign exp_lt_27 = exp_diff > 8'd27;
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assign exp_lt_27 = exp_diff > 8'd27;
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assign exp_diff_sft = exp_lt_27 ? 5'd27 : exp_diff[4:0];
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assign exp_diff_sft = exp_lt_27 ? 5'd27 : exp_diff[4:0];
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assign adj_op_out_sft = adj_op_tmp >> exp_diff_sft;
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assign adj_op_out_sft = adj_op_tmp >> exp_diff_sft;
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assign adj_op_out = {adj_op_out_sft[26:1], adj_op_out_sft[0] | sticky };
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assign adj_op_out = {adj_op_out_sft[26:1], adj_op_out_sft[0] | sticky };
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Get truncated portion (sticky bit)
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// Get truncated portion (sticky bit)
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always @(exp_diff_sft or adj_op_tmp)
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always @(exp_diff_sft or adj_op_tmp)
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case(exp_diff_sft) // synopsys full_case parallel_case
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case(exp_diff_sft) // synopsys full_case parallel_case
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00: sticky = 1'h0;
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00: sticky = 1'h0;
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01: sticky = adj_op_tmp[0];
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01: sticky = adj_op_tmp[0];
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02: sticky = |adj_op_tmp[01:0];
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02: sticky = |adj_op_tmp[01:0];
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03: sticky = |adj_op_tmp[02:0];
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03: sticky = |adj_op_tmp[02:0];
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04: sticky = |adj_op_tmp[03:0];
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04: sticky = |adj_op_tmp[03:0];
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05: sticky = |adj_op_tmp[04:0];
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05: sticky = |adj_op_tmp[04:0];
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06: sticky = |adj_op_tmp[05:0];
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06: sticky = |adj_op_tmp[05:0];
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07: sticky = |adj_op_tmp[06:0];
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07: sticky = |adj_op_tmp[06:0];
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08: sticky = |adj_op_tmp[07:0];
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08: sticky = |adj_op_tmp[07:0];
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09: sticky = |adj_op_tmp[08:0];
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09: sticky = |adj_op_tmp[08:0];
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10: sticky = |adj_op_tmp[09:0];
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10: sticky = |adj_op_tmp[09:0];
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11: sticky = |adj_op_tmp[10:0];
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11: sticky = |adj_op_tmp[10:0];
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12: sticky = |adj_op_tmp[11:0];
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12: sticky = |adj_op_tmp[11:0];
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13: sticky = |adj_op_tmp[12:0];
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13: sticky = |adj_op_tmp[12:0];
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14: sticky = |adj_op_tmp[13:0];
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14: sticky = |adj_op_tmp[13:0];
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15: sticky = |adj_op_tmp[14:0];
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15: sticky = |adj_op_tmp[14:0];
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16: sticky = |adj_op_tmp[15:0];
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16: sticky = |adj_op_tmp[15:0];
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17: sticky = |adj_op_tmp[16:0];
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17: sticky = |adj_op_tmp[16:0];
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18: sticky = |adj_op_tmp[17:0];
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18: sticky = |adj_op_tmp[17:0];
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19: sticky = |adj_op_tmp[18:0];
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19: sticky = |adj_op_tmp[18:0];
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20: sticky = |adj_op_tmp[19:0];
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20: sticky = |adj_op_tmp[19:0];
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21: sticky = |adj_op_tmp[20:0];
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21: sticky = |adj_op_tmp[20:0];
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22: sticky = |adj_op_tmp[21:0];
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22: sticky = |adj_op_tmp[21:0];
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23: sticky = |adj_op_tmp[22:0];
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23: sticky = |adj_op_tmp[22:0];
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24: sticky = |adj_op_tmp[23:0];
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24: sticky = |adj_op_tmp[23:0];
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25: sticky = |adj_op_tmp[24:0];
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25: sticky = |adj_op_tmp[24:0];
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26: sticky = |adj_op_tmp[25:0];
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26: sticky = |adj_op_tmp[25:0];
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27: sticky = |adj_op_tmp[26:0];
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27: sticky = |adj_op_tmp[26:0];
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endcase
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endcase
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Select operands for add/sub (recover hidden bit)
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// Select operands for add/sub (recover hidden bit)
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assign fracta_n = expa_lt_expb ? {~expa_dn, fracta, 3'b0} : adj_op_out;
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assign fracta_n = expa_lt_expb ? {~expa_dn, fracta, 3'b0} : adj_op_out;
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assign fractb_n = expa_lt_expb ? adj_op_out : {~expb_dn, fractb, 3'b0};
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assign fractb_n = expa_lt_expb ? adj_op_out : {~expb_dn, fractb, 3'b0};
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Sort operands (for sub only)
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// Sort operands (for sub only)
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assign fractb_lt_fracta = fractb_n > fracta_n; // fractb is larger than fracta
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assign fractb_lt_fracta = fractb_n > fracta_n; // fractb is larger than fracta
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assign fracta_s = fractb_lt_fracta ? fractb_n : fracta_n;
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assign fracta_s = fractb_lt_fracta ? fractb_n : fracta_n;
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assign fractb_s = fractb_lt_fracta ? fracta_n : fractb_n;
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assign fractb_s = fractb_lt_fracta ? fracta_n : fractb_n;
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always @(posedge clk)
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always @(posedge clk)
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fracta_out <= #1 fracta_s;
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fracta_out <= #1 fracta_s;
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always @(posedge clk)
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always @(posedge clk)
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fractb_out <= #1 fractb_s;
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fractb_out <= #1 fractb_s;
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|
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// ---------------------------------------------------------------------
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// ---------------------------------------------------------------------
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// Determine sign for the output
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// Determine sign for the output
|
|
|
// sign: 0=Positive Number; 1=Negative Number
|
// sign: 0=Positive Number; 1=Negative Number
|
always @(signa or signb or add or fractb_lt_fracta)
|
always @(signa or signb or add or fractb_lt_fracta)
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case({signa, signb, add}) // synopsys full_case parallel_case
|
case({signa, signb, add}) // synopsys full_case parallel_case
|
|
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// Add
|
// Add
|
3'b0_0_1: sign_d = 0;
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3'b0_0_1: sign_d = 0;
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3'b0_1_1: sign_d = fractb_lt_fracta;
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3'b0_1_1: sign_d = fractb_lt_fracta;
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3'b1_0_1: sign_d = !fractb_lt_fracta;
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3'b1_0_1: sign_d = !fractb_lt_fracta;
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3'b1_1_1: sign_d = 1;
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3'b1_1_1: sign_d = 1;
|
|
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// Sub
|
// Sub
|
3'b0_0_0: sign_d = fractb_lt_fracta;
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3'b0_0_0: sign_d = fractb_lt_fracta;
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3'b0_1_0: sign_d = 0;
|
3'b0_1_0: sign_d = 0;
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3'b1_0_0: sign_d = 1;
|
3'b1_0_0: sign_d = 1;
|
3'b1_1_0: sign_d = !fractb_lt_fracta;
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3'b1_1_0: sign_d = !fractb_lt_fracta;
|
endcase
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endcase
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|
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always @(posedge clk)
|
always @(posedge clk)
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sign <= #1 sign_d;
|
sign <= #1 sign_d;
|
|
|
// Fix sign for ZERO result
|
// Fix sign for ZERO result
|
always @(posedge clk)
|
always @(posedge clk)
|
signa_r <= #1 signa;
|
signa_r <= #1 signa;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
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signb_r <= #1 signb;
|
signb_r <= #1 signb;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
add_r <= #1 add;
|
add_r <= #1 add;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
result_zero_sign <= #1 ( add_r & signa_r & signb_r) |
|
result_zero_sign <= #1 ( add_r & signa_r & signb_r) |
|
(!add_r & signa_r & !signb_r) |
|
(!add_r & signa_r & !signb_r) |
|
( add_r & (signa_r | signb_r) & (rmode==3)) |
|
( add_r & (signa_r | signb_r) & (rmode==3)) |
|
(!add_r & (signa_r == signb_r) & (rmode==3));
|
(!add_r & (signa_r == signb_r) & (rmode==3));
|
|
|
// Fix sign for NAN result
|
// Fix sign for NAN result
|
always @(posedge clk)
|
always @(posedge clk)
|
fracta_lt_fractb <= #1 fracta < fractb;
|
fracta_lt_fractb <= #1 fracta < fractb;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
fracta_eq_fractb <= #1 fracta == fractb;
|
fracta_eq_fractb <= #1 fracta == fractb;
|
|
|
assign nan_sign1 = fracta_eq_fractb ? (signa_r & signb_r) : fracta_lt_fractb ? signb_r : signa_r;
|
assign nan_sign1 = fracta_eq_fractb ? (signa_r & signb_r) : fracta_lt_fractb ? signb_r : signa_r;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
nan_sign <= #1 (opa_nan & opb_nan) ? nan_sign1 : opb_nan ? signb_r : signa_r;
|
nan_sign <= #1 (opa_nan & opb_nan) ? nan_sign1 : opb_nan ? signb_r : signa_r;
|
|
|
////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Decode Add/Sub operation
|
// Decode Add/Sub operation
|
//
|
//
|
|
|
// add: 1=Add; 0=Subtract
|
// add: 1=Add; 0=Subtract
|
always @(signa or signb or add)
|
always @(signa or signb or add)
|
case({signa, signb, add}) // synopsys full_case parallel_case
|
case({signa, signb, add}) // synopsys full_case parallel_case
|
|
|
// Add
|
// Add
|
3'b0_0_1: add_d = 1;
|
3'b0_0_1: add_d = 1;
|
3'b0_1_1: add_d = 0;
|
3'b0_1_1: add_d = 0;
|
3'b1_0_1: add_d = 0;
|
3'b1_0_1: add_d = 0;
|
3'b1_1_1: add_d = 1;
|
3'b1_1_1: add_d = 1;
|
|
|
// Sub
|
// Sub
|
3'b0_0_0: add_d = 0;
|
3'b0_0_0: add_d = 0;
|
3'b0_1_0: add_d = 1;
|
3'b0_1_0: add_d = 1;
|
3'b1_0_0: add_d = 1;
|
3'b1_0_0: add_d = 1;
|
3'b1_1_0: add_d = 0;
|
3'b1_1_0: add_d = 0;
|
endcase
|
endcase
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
fasu_op <= #1 add_d;
|
fasu_op <= #1 add_d;
|
|
|
endmodule
|
endmodule
|
|
|
