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[/] [fpu/] [trunk/] [verilog/] [primitives.v] - Diff between revs 3 and 11

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/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
////  Primitives                                                 ////
////  Primitives                                                 ////
////  FPU Primitives                                             ////
////  FPU Primitives                                             ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                    rudi@asics.ws                            ////
////                                                             ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
 
 
 
 
`timescale 1ns / 100ps
`timescale 1ns / 100ps
 
 
 
 
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
//
//
// Add/Sub
// Add/Sub
//
//
 
 
module add_sub27(add, opa, opb, sum, co);
module add_sub27(add, opa, opb, sum, co);
input           add;
input           add;
input   [26:0]   opa, opb;
input   [26:0]   opa, opb;
output  [26:0]   sum;
output  [26:0]   sum;
output          co;
output          co;
 
 
 
 
 
 
assign {co, sum} = add ? (opa + opb) : (opa - opb);
assign {co, sum} = add ? (opa + opb) : (opa - opb);
 
 
endmodule
endmodule
 
 
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
//
//
// Multiply
// Multiply
//
//
 
 
module mul_r2(clk, opa, opb, prod);
module mul_r2(clk, opa, opb, prod);
input           clk;
input           clk;
input   [23:0]   opa, opb;
input   [23:0]   opa, opb;
output  [47:0]   prod;
output  [47:0]   prod;
 
 
reg     [47:0]   prod1, prod;
reg     [47:0]   prod1, prod;
 
 
always @(posedge clk)
always @(posedge clk)
        prod1 <= #1 opa * opb;
        prod1 <= #1 opa * opb;
 
 
always @(posedge clk)
always @(posedge clk)
        prod <= #1 prod1;
        prod <= #1 prod1;
 
 
endmodule
endmodule
 
 
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
//
//
// Divide
// Divide
//
//
 
 
module div_r2(clk, opa, opb, quo, rem);
module div_r2(clk, opa, opb, quo, rem);
input           clk;
input           clk;
input   [49:0]   opa;
input   [49:0]   opa;
input   [23:0]   opb;
input   [23:0]   opb;
output  [49:0]   quo, rem;
output  [49:0]   quo, rem;
 
 
reg     [49:0]   quo, rem, quo1, remainder;
reg     [49:0]   quo, rem, quo1, remainder;
 
 
always @(posedge clk)
always @(posedge clk)
        quo1 <= #1 opa / opb;
        quo1 <= #1 opa / opb;
 
 
always @(posedge clk)
always @(posedge clk)
        quo <= #1 quo1;
        quo <= #1 quo1;
 
 
always @(posedge clk)
always @(posedge clk)
        remainder <= #1 opa % opb;
        remainder <= #1 opa % opb;
 
 
always @(posedge clk)
always @(posedge clk)
        rem <= #1 remainder;
        rem <= #1 remainder;
 
 
endmodule
endmodule
 
 
 
 
 
 

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