-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Project: <Floating Point Unit Core>
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-- Project: <Floating Point Unit Core>
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--
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--
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-- Description: Serial multiplication entity for the multiplication unit
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-- Description: Serial multiplication entity for the multiplication unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- 100101011010011100100
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-- 100101011010011100100
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-- 110000111011100100000
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-- 110000111011100100000
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-- 100000111011000101101
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-- 100000111011000101101
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-- 100010111100101111001
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-- 100010111100101111001
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-- 110000111011101101001
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-- 110000111011101101001
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-- 010000001011101001010
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-- 010000001011101001010
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-- 110100111001001100001
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-- 110100111001001100001
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-- 110111010000001100111
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-- 110111010000001100111
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-- 110110111110001011101
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-- 110110111110001011101
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-- 101110110010111101000
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-- 101110110010111101000
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-- 100000010111000000000
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-- 100000010111000000000
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--
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--
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-- Author: Jidan Al-eryani
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-- Author: Jidan Al-eryani
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-- E-mail: jidan@gmx.net
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-- E-mail: jidan@gmx.net
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--
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--
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-- Copyright (C) 2006
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-- Copyright (C) 2006
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--
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--
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-- This source file may be used and distributed without
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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-- the original copyright notice and the associated disclaimer.
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--
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--
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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library ieee ;
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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library work;
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library work;
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use work.fpupack.all;
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use work.fpupack.all;
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entity serial_mul is
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entity serial_mul is
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port(
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port(
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clk_i : in std_logic;
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clk_i : in std_logic;
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fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
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fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
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fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
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fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
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signa_i : in std_logic;
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signa_i : in std_logic;
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signb_i : in std_logic;
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signb_i : in std_logic;
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start_i : in std_logic;
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start_i : in std_logic;
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fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
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fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
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sign_o : out std_logic;
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sign_o : out std_logic;
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ready_o : out std_logic
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ready_o : out std_logic
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);
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);
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end serial_mul;
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end serial_mul;
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architecture rtl of serial_mul is
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architecture rtl of serial_mul is
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type t_state is (waiting,busy);
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type t_state is (waiting,busy);
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signal s_fract_o: std_logic_vector(47 downto 0);
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signal s_fract_o: std_logic_vector(47 downto 0);
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signal s_fracta_i, s_fractb_i : std_logic_vector(23 downto 0);
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signal s_fracta_i, s_fractb_i : std_logic_vector(23 downto 0);
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signal s_signa_i, s_signb_i, s_sign_o : std_logic;
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signal s_signa_i, s_signb_i, s_sign_o : std_logic;
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signal s_start_i, s_ready_o : std_logic;
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signal s_start_i, s_ready_o : std_logic;
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signal s_state : t_state;
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signal s_state : t_state;
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signal s_count : integer range 0 to 23;
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signal s_count : integer range 0 to 23;
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signal s_tem_prod : std_logic_vector(23 downto 0);
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signal s_tem_prod : std_logic_vector(23 downto 0);
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begin
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begin
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-- Input Register
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-- Input Register
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process(clk_i)
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process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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s_fracta_i <= fracta_i;
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s_fracta_i <= fracta_i;
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s_fractb_i <= fractb_i;
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s_fractb_i <= fractb_i;
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s_signa_i<= signa_i;
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s_signa_i<= signa_i;
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s_signb_i<= signb_i;
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s_signb_i<= signb_i;
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s_start_i <= start_i;
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s_start_i <= start_i;
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end if;
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end if;
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end process;
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end process;
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-- Output Register
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-- Output Register
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process(clk_i)
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process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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fract_o <= s_fract_o;
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fract_o <= s_fract_o;
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sign_o <= s_sign_o;
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sign_o <= s_sign_o;
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ready_o <= s_ready_o;
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ready_o <= s_ready_o;
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end if;
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end if;
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end process;
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end process;
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s_sign_o <= signa_i xor signb_i;
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s_sign_o <= signa_i xor signb_i;
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-- FSM
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-- FSM
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process(clk_i)
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process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if s_start_i ='1' then
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if s_start_i ='1' then
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s_state <= busy;
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s_state <= busy;
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s_count <= 0;
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s_count <= 0;
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elsif s_count=23 then
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elsif s_count=23 then
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s_state <= waiting;
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s_state <= waiting;
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s_ready_o <= '1';
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s_ready_o <= '1';
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s_count <=0;
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s_count <=0;
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elsif s_state=busy then
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elsif s_state=busy then
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s_count <= s_count + 1;
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s_count <= s_count + 1;
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else
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else
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s_state <= waiting;
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s_state <= waiting;
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s_ready_o <= '0';
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s_ready_o <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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g1: for i in 0 to 23 generate
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g1: for i in 0 to 23 generate
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s_tem_prod(i) <= s_fracta_i(i) and s_fractb_i(s_count);
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s_tem_prod(i) <= s_fracta_i(i) and s_fractb_i(s_count);
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end generate;
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end generate;
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process(clk_i)
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process(clk_i)
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variable v_prod_shl : std_logic_vector(47 downto 0);
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variable v_prod_shl : std_logic_vector(47 downto 0);
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if s_state=busy then
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if s_state=busy then
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v_prod_shl := shl(conv_std_logic_vector(0,24)&s_tem_prod, conv_std_logic_vector(s_count,5));
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v_prod_shl := shl(conv_std_logic_vector(0,24)&s_tem_prod, conv_std_logic_vector(s_count,5));
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if s_count /= 0 then
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if s_count /= 0 then
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s_fract_o <= v_prod_shl + s_fract_o;
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s_fract_o <= v_prod_shl + s_fract_o;
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else
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else
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s_fract_o <= v_prod_shl;
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s_fract_o <= v_prod_shl;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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