---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- ----
|
---- ----
|
---- Floating Point Unit (Double precision) ----
|
---- Floating Point Unit (Double precision) ----
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---- ----
|
---- ----
|
---- Author: David Lundgren ----
|
---- Author: David Lundgren ----
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---- davidklun@gmail.com ----
|
---- davidklun@gmail.com ----
|
---- ----
|
---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
|
---- ----
|
---- ----
|
---- Copyright (C) 2009 David Lundgren ----
|
---- Copyright (C) 2009 David Lundgren ----
|
---- davidklun@gmail.com ----
|
---- davidklun@gmail.com ----
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---- ----
|
---- ----
|
---- This source file may be used and distributed without ----
|
---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
|
---- removed from the file and that any derivative work contains ----
|
---- removed from the file and that any derivative work contains ----
|
---- the original copyright notice and the associated disclaimer.----
|
---- the original copyright notice and the associated disclaimer.----
|
---- ----
|
---- ----
|
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
---- THIS SOFTWARE IS PROVIDED `AS IS' AND WITHOUT ANY ----
|
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
|
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
|
---- POSSIBILITY OF SUCH DAMAGE. ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---- ----
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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|
|
LIBRARY ieee;
|
LIBRARY ieee;
|
USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
|
USE ieee.std_logic_arith.all;
|
USE ieee.std_logic_arith.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
|
|
|
ENTITY fpu_exceptions IS
|
ENTITY fpu_exceptions IS
|
|
|
PORT(
|
PORT(
|
clk, rst, enable : IN std_logic;
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clk, rst, enable : IN std_logic;
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rmode : IN std_logic_vector (1 DOWNTO 0);
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rmode : IN std_logic_vector (1 DOWNTO 0);
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opa, opb, in_except : IN std_logic_vector (63 DOWNTO 0);
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opa, opb, in_except : IN std_logic_vector (63 DOWNTO 0);
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exponent_in : IN std_logic_vector (11 DOWNTO 0);
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exponent_in : IN std_logic_vector (11 DOWNTO 0);
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mantissa_in : IN std_logic_vector (1 DOWNTO 0);
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mantissa_in : IN std_logic_vector (1 DOWNTO 0);
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fpu_op : IN std_logic_vector (2 DOWNTO 0);
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fpu_op : IN std_logic_vector (2 DOWNTO 0);
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out_fp : OUT std_logic_vector (63 DOWNTO 0);
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out_fp : OUT std_logic_vector (63 DOWNTO 0);
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ex_enable, underflow, overflow, inexact : OUT std_logic;
|
ex_enable, underflow, overflow, inexact : OUT std_logic;
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exception, invalid : OUT std_logic
|
exception, invalid : OUT std_logic
|
);
|
);
|
|
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END fpu_exceptions;
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END fpu_exceptions;
|
|
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architecture rtl of fpu_exceptions is
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architecture rtl of fpu_exceptions is
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|
|
signal in_et_zero : std_logic;
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signal in_et_zero : std_logic;
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signal opa_et_zero : std_logic;
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signal opa_et_zero : std_logic;
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signal opb_et_zero : std_logic;
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signal opb_et_zero : std_logic;
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signal add : std_logic;
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signal add : std_logic;
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signal subtract : std_logic;
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signal subtract : std_logic;
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signal multiply : std_logic;
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signal multiply : std_logic;
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signal divide : std_logic;
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signal divide : std_logic;
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signal opa_QNaN : std_logic;
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signal opa_QNaN : std_logic;
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signal opb_QNaN : std_logic;
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signal opb_QNaN : std_logic;
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signal opa_SNaN : std_logic;
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signal opa_SNaN : std_logic;
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signal opb_SNaN : std_logic;
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signal opb_SNaN : std_logic;
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signal opa_pos_inf : std_logic;
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signal opa_pos_inf : std_logic;
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signal opb_pos_inf : std_logic;
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signal opb_pos_inf : std_logic;
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signal opa_neg_inf : std_logic;
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signal opa_neg_inf : std_logic;
|
signal opb_neg_inf : std_logic;
|
signal opb_neg_inf : std_logic;
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signal opa_inf : std_logic;
|
signal opa_inf : std_logic;
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signal opb_inf : std_logic;
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signal opb_inf : std_logic;
|
signal NaN_input : std_logic;
|
signal NaN_input : std_logic;
|
signal SNaN_input : std_logic;
|
signal SNaN_input : std_logic;
|
signal a_NaN : std_logic;
|
signal a_NaN : std_logic;
|
signal div_by_0 : std_logic;
|
signal div_by_0 : std_logic;
|
signal div_0_by_0 : std_logic;
|
signal div_0_by_0 : std_logic;
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signal div_inf_by_inf : std_logic;
|
signal div_inf_by_inf : std_logic;
|
signal div_by_inf : std_logic;
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signal div_by_inf : std_logic;
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signal mul_0_by_inf : std_logic;
|
signal mul_0_by_inf : std_logic;
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signal mul_inf : std_logic;
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signal mul_inf : std_logic;
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signal div_inf : std_logic;
|
signal div_inf : std_logic;
|
signal add_inf : std_logic;
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signal add_inf : std_logic;
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signal sub_inf : std_logic;
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signal sub_inf : std_logic;
|
signal addsub_inf_invalid : std_logic;
|
signal addsub_inf_invalid : std_logic;
|
signal addsub_inf : std_logic;
|
signal addsub_inf : std_logic;
|
signal out_inf_trigger : std_logic;
|
signal out_inf_trigger : std_logic;
|
signal out_pos_inf : std_logic;
|
signal out_pos_inf : std_logic;
|
signal out_neg_inf : std_logic;
|
signal out_neg_inf : std_logic;
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signal round_nearest : std_logic;
|
signal round_nearest : std_logic;
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signal round_to_zero : std_logic;
|
signal round_to_zero : std_logic;
|
signal round_to_pos_inf : std_logic;
|
signal round_to_pos_inf : std_logic;
|
signal round_to_neg_inf : std_logic;
|
signal round_to_neg_inf : std_logic;
|
signal inf_round_down_trigger : std_logic;
|
signal inf_round_down_trigger : std_logic;
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signal mul_uf : std_logic;
|
signal mul_uf : std_logic;
|
signal div_uf : std_logic;
|
signal div_uf : std_logic;
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signal underflow_trigger : std_logic;
|
signal underflow_trigger : std_logic;
|
signal invalid_trigger : std_logic;
|
signal invalid_trigger : std_logic;
|
signal overflow_trigger : std_logic;
|
signal overflow_trigger : std_logic;
|
signal inexact_trigger : std_logic;
|
signal inexact_trigger : std_logic;
|
signal except_trigger : std_logic;
|
signal except_trigger : std_logic;
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signal enable_trigger : std_logic;
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signal enable_trigger : std_logic;
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signal NaN_out_trigger : std_logic;
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signal NaN_out_trigger : std_logic;
|
signal SNaN_trigger : std_logic;
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signal SNaN_trigger : std_logic;
|
|
|
|
|
signal exp_2047 : std_logic_vector(10 downto 0);
|
signal exp_2047 : std_logic_vector(10 downto 0);
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signal exp_2046 : std_logic_vector(10 downto 0);
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signal exp_2046 : std_logic_vector(10 downto 0);
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signal NaN_output_0 : std_logic_vector(62 downto 0);
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signal NaN_output_0 : std_logic_vector(62 downto 0);
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signal NaN_output : std_logic_vector(62 downto 0);
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signal NaN_output : std_logic_vector(62 downto 0);
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signal mantissa_max : std_logic_vector(51 downto 0);
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signal mantissa_max : std_logic_vector(51 downto 0);
|
signal inf_round_down : std_logic_vector(62 downto 0);
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signal inf_round_down : std_logic_vector(62 downto 0);
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signal out_inf : std_logic_vector(62 downto 0);
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signal out_inf : std_logic_vector(62 downto 0);
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signal out_0 : std_logic_vector(63 downto 0);
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signal out_0 : std_logic_vector(63 downto 0);
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signal out_1 : std_logic_vector(63 downto 0);
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signal out_1 : std_logic_vector(63 downto 0);
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signal out_2 : std_logic_vector(63 downto 0);
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signal out_2 : std_logic_vector(63 downto 0);
|
|
|
begin
|
begin
|
|
|
exp_2047 <= "11111111111";
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exp_2047 <= "11111111111";
|
exp_2046 <= "11111111110";
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exp_2046 <= "11111111110";
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mantissa_max <= "1111111111111111111111111111111111111111111111111111";
|
mantissa_max <= "1111111111111111111111111111111111111111111111111111";
|
|
|
process
|
process
|
begin
|
begin
|
wait until clk'event and clk = '1';
|
wait until clk'event and clk = '1';
|
if (rst = '1') then
|
if (rst = '1') then
|
in_et_zero <= '0';
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in_et_zero <= '0';
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opa_et_zero <= '0';
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opa_et_zero <= '0';
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opb_et_zero <= '0';
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opb_et_zero <= '0';
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add <= '0';
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add <= '0';
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subtract <= '0';
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subtract <= '0';
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multiply <= '0';
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multiply <= '0';
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divide <= '0';
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divide <= '0';
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opa_QNaN <= '0';
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opa_QNaN <= '0';
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opb_QNaN <= '0';
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opb_QNaN <= '0';
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opa_SNaN <= '0';
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opa_SNaN <= '0';
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opb_SNaN <= '0';
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opb_SNaN <= '0';
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opa_pos_inf <= '0';
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opa_pos_inf <= '0';
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opb_pos_inf <= '0';
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opb_pos_inf <= '0';
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opa_neg_inf <= '0';
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opa_neg_inf <= '0';
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opb_neg_inf <= '0';
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opb_neg_inf <= '0';
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opa_inf <= '0';
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opa_inf <= '0';
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opb_inf <= '0';
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opb_inf <= '0';
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NaN_input <= '0';
|
NaN_input <= '0';
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SNaN_input <= '0';
|
SNaN_input <= '0';
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a_NaN <= '0';
|
a_NaN <= '0';
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div_by_0 <= '0';
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div_by_0 <= '0';
|
div_0_by_0 <= '0';
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div_0_by_0 <= '0';
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div_inf_by_inf <= '0';
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div_inf_by_inf <= '0';
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div_by_inf <= '0';
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div_by_inf <= '0';
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mul_0_by_inf <= '0';
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mul_0_by_inf <= '0';
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mul_inf <= '0';
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mul_inf <= '0';
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div_inf <= '0';
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div_inf <= '0';
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add_inf <= '0';
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add_inf <= '0';
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sub_inf <= '0';
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sub_inf <= '0';
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addsub_inf_invalid <= '0';
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addsub_inf_invalid <= '0';
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addsub_inf <= '0';
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addsub_inf <= '0';
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out_inf_trigger <= '0';
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out_inf_trigger <= '0';
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out_pos_inf <= '0';
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out_pos_inf <= '0';
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out_neg_inf <= '0';
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out_neg_inf <= '0';
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round_nearest <= '0';
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round_nearest <= '0';
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round_to_zero <= '0';
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round_to_zero <= '0';
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round_to_pos_inf <= '0';
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round_to_pos_inf <= '0';
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round_to_neg_inf <= '0';
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round_to_neg_inf <= '0';
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inf_round_down_trigger <= '0';
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inf_round_down_trigger <= '0';
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mul_uf <= '0';
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mul_uf <= '0';
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div_uf <= '0';
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div_uf <= '0';
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underflow_trigger <= '0';
|
underflow_trigger <= '0';
|
invalid_trigger <= '0';
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invalid_trigger <= '0';
|
overflow_trigger <= '0';
|
overflow_trigger <= '0';
|
inexact_trigger <= '0';
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inexact_trigger <= '0';
|
except_trigger <= '0';
|
except_trigger <= '0';
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enable_trigger <= '0';
|
enable_trigger <= '0';
|
NaN_out_trigger <= '0';
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NaN_out_trigger <= '0';
|
SNaN_trigger <= '0';
|
SNaN_trigger <= '0';
|
NaN_output_0 <= (others =>'0');
|
NaN_output_0 <= (others =>'0');
|
NaN_output <= (others =>'0');
|
NaN_output <= (others =>'0');
|
inf_round_down <= (others =>'0');
|
inf_round_down <= (others =>'0');
|
out_inf <= (others =>'0');
|
out_inf <= (others =>'0');
|
out_0 <= (others =>'0');
|
out_0 <= (others =>'0');
|
out_1 <= (others =>'0');
|
out_1 <= (others =>'0');
|
out_2 <= (others =>'0');
|
out_2 <= (others =>'0');
|
elsif (enable = '1') then
|
elsif (enable = '1') then
|
if or_reduce(in_except(62 downto 0)) = '0' then
|
if or_reduce(in_except(62 downto 0)) = '0' then
|
in_et_zero <= '1';
|
in_et_zero <= '1';
|
else
|
else
|
in_et_zero <= '0';
|
in_et_zero <= '0';
|
end if;
|
end if;
|
if or_reduce(opa(62 downto 0)) = '0' then
|
if or_reduce(opa(62 downto 0)) = '0' then
|
opa_et_zero <= '1';
|
opa_et_zero <= '1';
|
else
|
else
|
opa_et_zero <= '0';
|
opa_et_zero <= '0';
|
end if;
|
end if;
|
if or_reduce(opb(62 downto 0)) = '0' then
|
if or_reduce(opb(62 downto 0)) = '0' then
|
opb_et_zero <= '1';
|
opb_et_zero <= '1';
|
else
|
else
|
opb_et_zero <= '0';
|
opb_et_zero <= '0';
|
end if;
|
end if;
|
if fpu_op = "000" then
|
if fpu_op = "000" then
|
add <= '1';
|
add <= '1';
|
else
|
else
|
add <= '0';
|
add <= '0';
|
end if;
|
end if;
|
if fpu_op = "001" then
|
if fpu_op = "001" then
|
subtract <= '1';
|
subtract <= '1';
|
else
|
else
|
subtract <= '0';
|
subtract <= '0';
|
end if;
|
end if;
|
if fpu_op = "010" then
|
if fpu_op = "010" then
|
multiply <= '1';
|
multiply <= '1';
|
else
|
else
|
multiply <= '0';
|
multiply <= '0';
|
end if;
|
end if;
|
if fpu_op = "011" then
|
if fpu_op = "011" then
|
divide <= '1';
|
divide <= '1';
|
else
|
else
|
divide <= '0';
|
divide <= '0';
|
end if;
|
end if;
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '1' and
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '1' and
|
opa(51) = '1' then
|
opa(51) = '1' then
|
opa_QNaN <= '1';
|
opa_QNaN <= '1';
|
else
|
else
|
opa_QNaN <= '0';
|
opa_QNaN <= '0';
|
end if;
|
end if;
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '1' and
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '1' and
|
opb(51) = '1' then
|
opb(51) = '1' then
|
opb_QNaN <= '1';
|
opb_QNaN <= '1';
|
else
|
else
|
opb_QNaN <= '0';
|
opb_QNaN <= '0';
|
end if;
|
end if;
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '1' and
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '1' and
|
opa(51) = '0' then
|
opa(51) = '0' then
|
opa_SNaN <= '1';
|
opa_SNaN <= '1';
|
else
|
else
|
opa_SNaN <= '0';
|
opa_SNaN <= '0';
|
end if;
|
end if;
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '1' and
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '1' and
|
opb(51) = '0' then
|
opb(51) = '0' then
|
opb_SNaN <= '1';
|
opb_SNaN <= '1';
|
else
|
else
|
opb_SNaN <= '0';
|
opb_SNaN <= '0';
|
end if;
|
end if;
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '0' and
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '0' and
|
opa(63) = '0' then
|
opa(63) = '0' then
|
opa_pos_inf <= '1';
|
opa_pos_inf <= '1';
|
else
|
else
|
opa_pos_inf <= '0';
|
opa_pos_inf <= '0';
|
end if;
|
end if;
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '0' and
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '0' and
|
opb(63) = '0' then
|
opb(63) = '0' then
|
opb_pos_inf <= '1';
|
opb_pos_inf <= '1';
|
else
|
else
|
opb_pos_inf <= '0';
|
opb_pos_inf <= '0';
|
end if;
|
end if;
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '0' and
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '0' and
|
opa(63) = '1' then
|
opa(63) = '1' then
|
opa_neg_inf <= '1';
|
opa_neg_inf <= '1';
|
else
|
else
|
opa_neg_inf <= '0';
|
opa_neg_inf <= '0';
|
end if;
|
end if;
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '0' and
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '0' and
|
opb(63) = '1' then
|
opb(63) = '1' then
|
opb_neg_inf <= '1';
|
opb_neg_inf <= '1';
|
else
|
else
|
opb_neg_inf <= '0';
|
opb_neg_inf <= '0';
|
end if;
|
end if;
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '0' then
|
if opa(62 downto 52) = "11111111111" and or_reduce(opa(51 downto 0)) = '0' then
|
opa_inf <= '1';
|
opa_inf <= '1';
|
else
|
else
|
opa_inf <= '0';
|
opa_inf <= '0';
|
end if;
|
end if;
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '0' then
|
if opb(62 downto 52) = "11111111111" and or_reduce(opb(51 downto 0)) = '0' then
|
opb_inf <= '1';
|
opb_inf <= '1';
|
else
|
else
|
opb_inf <= '0';
|
opb_inf <= '0';
|
end if;
|
end if;
|
if opa_QNaN = '1' or opb_QNaN = '1' or opa_SNaN = '1' or opb_SNaN = '1' then
|
if opa_QNaN = '1' or opb_QNaN = '1' or opa_SNaN = '1' or opb_SNaN = '1' then
|
NaN_input <= '1';
|
NaN_input <= '1';
|
else
|
else
|
NaN_input <= '0';
|
NaN_input <= '0';
|
end if;
|
end if;
|
if opa_SNaN = '1' or opb_SNaN = '1' then
|
if opa_SNaN = '1' or opb_SNaN = '1' then
|
SNaN_input <= '1';
|
SNaN_input <= '1';
|
else
|
else
|
SNaN_input <= '0';
|
SNaN_input <= '0';
|
end if;
|
end if;
|
if opa_SNaN = '1' or opa_QNaN = '1' then
|
if opa_SNaN = '1' or opa_QNaN = '1' then
|
a_NaN <= '1';
|
a_NaN <= '1';
|
else
|
else
|
a_NaN <= '0';
|
a_NaN <= '0';
|
end if;
|
end if;
|
if divide = '1' and opb_et_zero = '1' and opa_et_zero = '0' then
|
if divide = '1' and opb_et_zero = '1' and opa_et_zero = '0' then
|
div_by_0 <= '1';
|
div_by_0 <= '1';
|
else
|
else
|
div_by_0 <= '0';
|
div_by_0 <= '0';
|
end if;
|
end if;
|
if divide = '1' and opb_et_zero = '1' and opa_et_zero = '1' then
|
if divide = '1' and opb_et_zero = '1' and opa_et_zero = '1' then
|
div_0_by_0 <= '1';
|
div_0_by_0 <= '1';
|
else
|
else
|
div_0_by_0 <= '0';
|
div_0_by_0 <= '0';
|
end if;
|
end if;
|
if divide = '1' and opa_inf = '1' and opb_inf = '1' then
|
if divide = '1' and opa_inf = '1' and opb_inf = '1' then
|
div_inf_by_inf <= '1';
|
div_inf_by_inf <= '1';
|
else
|
else
|
div_inf_by_inf <= '0';
|
div_inf_by_inf <= '0';
|
end if;
|
end if;
|
if divide = '1' and opa_inf = '0' and opb_inf = '1' then
|
if divide = '1' and opa_inf = '0' and opb_inf = '1' then
|
div_by_inf <= '1';
|
div_by_inf <= '1';
|
else
|
else
|
div_by_inf <= '0';
|
div_by_inf <= '0';
|
end if;
|
end if;
|
if multiply = '1' and ((opa_inf = '1' and opb_et_zero = '1') or
|
if multiply = '1' and ((opa_inf = '1' and opb_et_zero = '1') or
|
(opa_et_zero = '1' and opb_inf = '1')) then
|
(opa_et_zero = '1' and opb_inf = '1')) then
|
mul_0_by_inf <= '1';
|
mul_0_by_inf <= '1';
|
else
|
else
|
mul_0_by_inf <= '0';
|
mul_0_by_inf <= '0';
|
end if;
|
end if;
|
if multiply = '1' and (opa_inf = '1' or opb_inf = '1') and
|
if multiply = '1' and (opa_inf = '1' or opb_inf = '1') and
|
mul_0_by_inf = '0' then
|
mul_0_by_inf = '0' then
|
mul_inf <= '1';
|
mul_inf <= '1';
|
else
|
else
|
mul_inf <= '0';
|
mul_inf <= '0';
|
end if;
|
end if;
|
if divide = '1' and opa_inf = '1' and opb_inf = '0' then
|
if divide = '1' and opa_inf = '1' and opb_inf = '0' then
|
div_inf <= '1';
|
div_inf <= '1';
|
else
|
else
|
div_inf <= '0';
|
div_inf <= '0';
|
end if;
|
end if;
|
if add = '1' and (opa_inf = '1' or opb_inf = '1') then
|
if add = '1' and (opa_inf = '1' or opb_inf = '1') then
|
add_inf <= '1';
|
add_inf <= '1';
|
else
|
else
|
add_inf <= '0';
|
add_inf <= '0';
|
end if;
|
end if;
|
if subtract = '1' and (opa_inf = '1' or opb_inf = '1') then
|
if subtract = '1' and (opa_inf = '1' or opb_inf = '1') then
|
sub_inf <= '1';
|
sub_inf <= '1';
|
else
|
else
|
sub_inf <= '0';
|
sub_inf <= '0';
|
end if;
|
end if;
|
if (add = '1' and opa_pos_inf = '1' and opb_neg_inf = '1') or
|
if (add = '1' and opa_pos_inf = '1' and opb_neg_inf = '1') or
|
(add = '1' and opa_neg_inf = '1' and opb_pos_inf = '1') or
|
(add = '1' and opa_neg_inf = '1' and opb_pos_inf = '1') or
|
(subtract = '1' and opa_pos_inf = '1' and opb_pos_inf = '1') or
|
(subtract = '1' and opa_pos_inf = '1' and opb_pos_inf = '1') or
|
(subtract = '1' and opa_neg_inf = '1' and opb_neg_inf = '1') then
|
(subtract = '1' and opa_neg_inf = '1' and opb_neg_inf = '1') then
|
addsub_inf_invalid <= '1';
|
addsub_inf_invalid <= '1';
|
else
|
else
|
addsub_inf_invalid <= '0';
|
addsub_inf_invalid <= '0';
|
end if;
|
end if;
|
if (add_inf = '1' or sub_inf = '1') and addsub_inf_invalid = '0' then
|
if (add_inf = '1' or sub_inf = '1') and addsub_inf_invalid = '0' then
|
addsub_inf <= '1';
|
addsub_inf <= '1';
|
else
|
else
|
addsub_inf <= '0';
|
addsub_inf <= '0';
|
end if;
|
end if;
|
if addsub_inf = '1' or mul_inf = '1' or div_inf = '1' or div_by_0 = '1'
|
if addsub_inf = '1' or mul_inf = '1' or div_inf = '1' or div_by_0 = '1'
|
or (exponent_in > "011111111110") then -- 2046
|
or (exponent_in > "011111111110") then -- 2046
|
out_inf_trigger <= '1';
|
out_inf_trigger <= '1';
|
else
|
else
|
out_inf_trigger <= '0';
|
out_inf_trigger <= '0';
|
end if;
|
end if;
|
if out_inf_trigger = '1' and in_except(63) = '0' then
|
if out_inf_trigger = '1' and in_except(63) = '0' then
|
out_pos_inf <= '1';
|
out_pos_inf <= '1';
|
else
|
else
|
out_pos_inf <= '0';
|
out_pos_inf <= '0';
|
end if;
|
end if;
|
if out_inf_trigger = '1' and in_except(63) = '1' then
|
if out_inf_trigger = '1' and in_except(63) = '1' then
|
out_neg_inf <= '1';
|
out_neg_inf <= '1';
|
else
|
else
|
out_neg_inf <= '0';
|
out_neg_inf <= '0';
|
end if;
|
end if;
|
if rmode = "00" then
|
if rmode = "00" then
|
round_nearest <= '1';
|
round_nearest <= '1';
|
else
|
else
|
round_nearest <= '0';
|
round_nearest <= '0';
|
end if;
|
end if;
|
if rmode = "01" then
|
if rmode = "01" then
|
round_to_zero <= '1';
|
round_to_zero <= '1';
|
else
|
else
|
round_to_zero <= '0';
|
round_to_zero <= '0';
|
end if;
|
end if;
|
if rmode = "10" then
|
if rmode = "10" then
|
round_to_pos_inf <= '1';
|
round_to_pos_inf <= '1';
|
else
|
else
|
round_to_pos_inf <= '0';
|
round_to_pos_inf <= '0';
|
end if;
|
end if;
|
if rmode = "11" then
|
if rmode = "11" then
|
round_to_neg_inf <= '1';
|
round_to_neg_inf <= '1';
|
else
|
else
|
round_to_neg_inf <= '0';
|
round_to_neg_inf <= '0';
|
end if;
|
end if;
|
if (out_pos_inf = '1' and round_to_neg_inf = '1') or
|
if (out_pos_inf = '1' and round_to_neg_inf = '1') or
|
(out_neg_inf = '1' and round_to_pos_inf = '1') or
|
(out_neg_inf = '1' and round_to_pos_inf = '1') or
|
(out_inf_trigger = '1' and round_to_zero = '1') then
|
(out_inf_trigger = '1' and round_to_zero = '1') then
|
inf_round_down_trigger <= '1';
|
inf_round_down_trigger <= '1';
|
else
|
else
|
inf_round_down_trigger <= '0';
|
inf_round_down_trigger <= '0';
|
end if;
|
end if;
|
if multiply = '1' and opa_et_zero = '0' and opb_et_zero = '0' and
|
if multiply = '1' and opa_et_zero = '0' and opb_et_zero = '0' and
|
in_et_zero = '1' then
|
in_et_zero = '1' then
|
mul_uf <= '1';
|
mul_uf <= '1';
|
else
|
else
|
mul_uf <= '0';
|
mul_uf <= '0';
|
end if;
|
end if;
|
if divide = '1' and opa_et_zero = '0' and in_et_zero = '1' then
|
if divide = '1' and opa_et_zero = '0' and in_et_zero = '1' then
|
div_uf <= '1';
|
div_uf <= '1';
|
else
|
else
|
div_uf <= '0';
|
div_uf <= '0';
|
end if;
|
end if;
|
if div_by_inf = '1' or mul_uf = '1' or div_uf = '1' then
|
if div_by_inf = '1' or mul_uf = '1' or div_uf = '1' then
|
underflow_trigger <= '1';
|
underflow_trigger <= '1';
|
else
|
else
|
underflow_trigger <= '0';
|
underflow_trigger <= '0';
|
end if;
|
end if;
|
if SNaN_input = '1' or addsub_inf_invalid = '1' or mul_0_by_inf = '1' or
|
if SNaN_input = '1' or addsub_inf_invalid = '1' or mul_0_by_inf = '1' or
|
div_0_by_0 = '1' or div_inf_by_inf = '1' then
|
div_0_by_0 = '1' or div_inf_by_inf = '1' then
|
invalid_trigger <= '1';
|
invalid_trigger <= '1';
|
else
|
else
|
invalid_trigger <= '0';
|
invalid_trigger <= '0';
|
end if;
|
end if;
|
if out_inf_trigger = '1' and NaN_input = '0' then
|
if out_inf_trigger = '1' and NaN_input = '0' then
|
overflow_trigger <= '1';
|
overflow_trigger <= '1';
|
else
|
else
|
overflow_trigger <= '0';
|
overflow_trigger <= '0';
|
end if;
|
end if;
|
if (or_reduce(mantissa_in(1 downto 0)) = '1' or out_inf_trigger = '1' or
|
if (or_reduce(mantissa_in(1 downto 0)) = '1' or out_inf_trigger = '1' or
|
underflow_trigger = '1') and NaN_input = '0' then
|
underflow_trigger = '1') and NaN_input = '0' then
|
inexact_trigger <= '1';
|
inexact_trigger <= '1';
|
else
|
else
|
inexact_trigger <= '0';
|
inexact_trigger <= '0';
|
end if;
|
end if;
|
if (invalid_trigger = '1' or overflow_trigger = '1' or
|
if (invalid_trigger = '1' or overflow_trigger = '1' or
|
underflow_trigger = '1' or inexact_trigger = '1') then
|
underflow_trigger = '1' or inexact_trigger = '1') then
|
except_trigger <= '1';
|
except_trigger <= '1';
|
else
|
else
|
except_trigger <= '0';
|
except_trigger <= '0';
|
end if;
|
end if;
|
if (except_trigger = '1' or out_inf_trigger = '1' or
|
if (except_trigger = '1' or out_inf_trigger = '1' or
|
NaN_input = '1') then
|
NaN_input = '1') then
|
enable_trigger <= '1';
|
enable_trigger <= '1';
|
else
|
else
|
enable_trigger <= '0';
|
enable_trigger <= '0';
|
end if;
|
end if;
|
if (NaN_input = '1' or invalid_trigger = '1') then
|
if (NaN_input = '1' or invalid_trigger = '1') then
|
NaN_out_trigger <= '1';
|
NaN_out_trigger <= '1';
|
else
|
else
|
NaN_out_trigger <= '0';
|
NaN_out_trigger <= '0';
|
end if;
|
end if;
|
if (invalid_trigger = '1' and SNaN_input = '0') then
|
if (invalid_trigger = '1' and SNaN_input = '0') then
|
SNaN_trigger <= '1';
|
SNaN_trigger <= '1';
|
else
|
else
|
SNaN_trigger <= '0';
|
SNaN_trigger <= '0';
|
end if;
|
end if;
|
if a_NaN = '1' then
|
if a_NaN = '1' then
|
NaN_output_0 <= exp_2047 & '1' & opa(50 downto 0);
|
NaN_output_0 <= exp_2047 & '1' & opa(50 downto 0);
|
else
|
else
|
NaN_output_0 <= exp_2047 & '1' & opb(50 downto 0);
|
NaN_output_0 <= exp_2047 & '1' & opb(50 downto 0);
|
end if;
|
end if;
|
if SNaN_trigger = '1' then
|
if SNaN_trigger = '1' then
|
NaN_output <= exp_2047 & "01" & opa(49 downto 0);
|
NaN_output <= exp_2047 & "01" & opa(49 downto 0);
|
else
|
else
|
NaN_output <= NaN_output_0;
|
NaN_output <= NaN_output_0;
|
end if;
|
end if;
|
inf_round_down <= exp_2046 & mantissa_max;
|
inf_round_down <= exp_2046 & mantissa_max;
|
if inf_round_down_trigger = '1' then
|
if inf_round_down_trigger = '1' then
|
out_inf <= inf_round_down;
|
out_inf <= inf_round_down;
|
else
|
else
|
out_inf <= exp_2047 & "0000000000000000000000000000000000000000000000000000";
|
out_inf <= exp_2047 & "0000000000000000000000000000000000000000000000000000";
|
end if;
|
end if;
|
if underflow_trigger = '1' then
|
if underflow_trigger = '1' then
|
out_0 <= in_except(63) & "000000000000000000000000000000000000000000000000000000000000000";
|
out_0 <= in_except(63) & "000000000000000000000000000000000000000000000000000000000000000";
|
else
|
else
|
out_0 <= in_except;
|
out_0 <= in_except;
|
end if;
|
end if;
|
if out_inf_trigger = '1' then
|
if out_inf_trigger = '1' then
|
out_1 <= in_except(63) & out_inf;
|
out_1 <= in_except(63) & out_inf;
|
else
|
else
|
out_1 <= out_0;
|
out_1 <= out_0;
|
end if;
|
end if;
|
if NaN_out_trigger = '1' then
|
if NaN_out_trigger = '1' then
|
out_2 <= in_except(63) & NaN_output;
|
out_2 <= in_except(63) & NaN_output;
|
else
|
else
|
out_2 <= out_1;
|
out_2 <= out_1;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
process
|
process
|
begin
|
begin
|
wait until clk'event and clk = '1';
|
wait until clk'event and clk = '1';
|
if (rst = '1') then
|
if (rst = '1') then
|
ex_enable <= '0';
|
ex_enable <= '0';
|
underflow <= '0';
|
underflow <= '0';
|
overflow <= '0';
|
overflow <= '0';
|
inexact <= '0';
|
inexact <= '0';
|
exception <= '0';
|
exception <= '0';
|
invalid <= '0';
|
invalid <= '0';
|
out_fp <= (others =>'0');
|
out_fp <= (others =>'0');
|
elsif (enable = '1') then
|
elsif (enable = '1') then
|
ex_enable <= enable_trigger;
|
ex_enable <= enable_trigger;
|
underflow <= underflow_trigger;
|
underflow <= underflow_trigger;
|
overflow <= overflow_trigger;
|
overflow <= overflow_trigger;
|
inexact <= inexact_trigger;
|
inexact <= inexact_trigger;
|
exception <= except_trigger;
|
exception <= except_trigger;
|
invalid <= invalid_trigger;
|
invalid <= invalid_trigger;
|
out_fp <= out_2;
|
out_fp <= out_2;
|
end if;
|
end if;
|
end process;
|
end process;
|
end rtl;
|
end rtl;
|
|
|
