-- VHDL Entity work.FPadd.symbol
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-- VHDL Entity work.FPadd.symbol
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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|
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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|
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ENTITY FPadd IS
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ENTITY FPadd IS
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PORT(
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PORT(
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ADD_SUB : IN std_logic;
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ADD_SUB : IN std_logic;
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FP_A : IN std_logic_vector (31 DOWNTO 0);
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FP_A : IN std_logic_vector (31 DOWNTO 0);
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FP_B : IN std_logic_vector (31 DOWNTO 0);
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FP_B : IN std_logic_vector (31 DOWNTO 0);
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clk : IN std_logic;
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clk : IN std_logic;
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FP_Z : OUT std_logic_vector (31 DOWNTO 0)
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FP_Z : OUT std_logic_vector (31 DOWNTO 0)
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);
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);
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-- Declarations
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-- Declarations
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END FPadd ;
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END FPadd ;
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|
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--
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--
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-- VHDL Architecture work.FPadd.single_cycle
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-- VHDL Architecture work.FPadd.single_cycle
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--
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--
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-- Created by
|
-- Created by
|
-- Guillermo Marcus, gmarcus@ieee.org
|
-- Guillermo Marcus, gmarcus@ieee.org
|
-- using Mentor Graphics FPGA Advantage tools.
|
-- using Mentor Graphics FPGA Advantage tools.
|
--
|
--
|
-- Visit "http://fpga.mty.itesm.mx" for more info.
|
-- Visit "http://fpga.mty.itesm.mx" for more info.
|
--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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|
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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|
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ARCHITECTURE single_cycle OF FPadd IS
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ARCHITECTURE single_cycle OF FPadd IS
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|
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-- Architecture declarations
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-- Architecture declarations
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-- Non hierarchical truthtable declarations
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-- Non hierarchical truthtable declarations
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|
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-- Non hierarchical truthtable declarations
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-- Non hierarchical truthtable declarations
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|
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-- Non hierarchical truthtable declarations
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-- Non hierarchical truthtable declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL A_CS : std_logic_vector(28 DOWNTO 0);
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SIGNAL A_CS : std_logic_vector(28 DOWNTO 0);
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SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL A_SIGN : std_logic;
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SIGNAL A_SIGN : std_logic;
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SIGNAL A_in : std_logic_vector(28 DOWNTO 0);
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SIGNAL A_in : std_logic_vector(28 DOWNTO 0);
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SIGNAL A_isDN : std_logic;
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SIGNAL A_isDN : std_logic;
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SIGNAL A_isINF : std_logic;
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SIGNAL A_isINF : std_logic;
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SIGNAL A_isNaN : std_logic;
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SIGNAL A_isNaN : std_logic;
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SIGNAL A_isZ : std_logic;
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SIGNAL A_isZ : std_logic;
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SIGNAL B_CS : std_logic_vector(28 DOWNTO 0);
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SIGNAL B_CS : std_logic_vector(28 DOWNTO 0);
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SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL B_SIGN : std_logic;
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SIGNAL B_SIGN : std_logic;
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SIGNAL B_XSIGN : std_logic;
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SIGNAL B_XSIGN : std_logic;
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SIGNAL B_in : std_logic_vector(28 DOWNTO 0);
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SIGNAL B_in : std_logic_vector(28 DOWNTO 0);
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SIGNAL B_isDN : std_logic;
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SIGNAL B_isDN : std_logic;
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SIGNAL B_isINF : std_logic;
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SIGNAL B_isINF : std_logic;
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SIGNAL B_isNaN : std_logic;
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SIGNAL B_isNaN : std_logic;
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SIGNAL B_isZ : std_logic;
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SIGNAL B_isZ : std_logic;
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SIGNAL EXP_base : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_base : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_diff : std_logic_vector(8 DOWNTO 0);
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SIGNAL EXP_diff : std_logic_vector(8 DOWNTO 0);
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SIGNAL EXP_isINF : std_logic;
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SIGNAL EXP_isINF : std_logic;
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SIGNAL EXP_norm : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_norm : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_round : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_round : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_selC : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_selC : std_logic_vector(7 DOWNTO 0);
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SIGNAL OV : std_logic;
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SIGNAL OV : std_logic;
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SIGNAL SIG_norm : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_norm : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_norm2 : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_norm2 : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_round : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_round : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_selC : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_selC : std_logic_vector(27 DOWNTO 0);
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SIGNAL Z_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL Z_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL Z_SIG : std_logic_vector(22 DOWNTO 0);
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SIGNAL Z_SIG : std_logic_vector(22 DOWNTO 0);
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SIGNAL Z_SIGN : std_logic;
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SIGNAL Z_SIGN : std_logic;
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SIGNAL a_align : std_logic_vector(28 DOWNTO 0);
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SIGNAL a_align : std_logic_vector(28 DOWNTO 0);
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SIGNAL a_exp_in : std_logic_vector(8 DOWNTO 0);
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SIGNAL a_exp_in : std_logic_vector(8 DOWNTO 0);
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SIGNAL a_inv : std_logic_vector(28 DOWNTO 0);
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SIGNAL a_inv : std_logic_vector(28 DOWNTO 0);
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SIGNAL add_out : std_logic_vector(28 DOWNTO 0);
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SIGNAL add_out : std_logic_vector(28 DOWNTO 0);
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SIGNAL b_align : std_logic_vector(28 DOWNTO 0);
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SIGNAL b_align : std_logic_vector(28 DOWNTO 0);
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SIGNAL b_exp_in : std_logic_vector(8 DOWNTO 0);
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SIGNAL b_exp_in : std_logic_vector(8 DOWNTO 0);
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SIGNAL b_inv : std_logic_vector(28 DOWNTO 0);
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SIGNAL b_inv : std_logic_vector(28 DOWNTO 0);
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SIGNAL cin : std_logic;
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SIGNAL cin : std_logic;
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SIGNAL cin_sub : std_logic;
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SIGNAL cin_sub : std_logic;
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SIGNAL invert_A : std_logic;
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SIGNAL invert_A : std_logic;
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SIGNAL invert_B : std_logic;
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SIGNAL invert_B : std_logic;
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SIGNAL isINF : std_logic;
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SIGNAL isINF : std_logic;
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SIGNAL isINF_tab : std_logic;
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SIGNAL isINF_tab : std_logic;
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SIGNAL isNaN : std_logic;
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SIGNAL isNaN : std_logic;
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SIGNAL isZ : std_logic;
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SIGNAL isZ : std_logic;
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SIGNAL isZ_tab : std_logic;
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SIGNAL isZ_tab : std_logic;
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SIGNAL mux_sel : std_logic;
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SIGNAL mux_sel : std_logic;
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SIGNAL zero : std_logic;
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SIGNAL zero : std_logic;
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-- ModuleWare signal declarations(v1.1) for instance 'I13' of 'mux'
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-- ModuleWare signal declarations(v1.1) for instance 'I13' of 'mux'
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SIGNAL mw_I13din0 : std_logic_vector(7 DOWNTO 0);
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SIGNAL mw_I13din0 : std_logic_vector(7 DOWNTO 0);
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SIGNAL mw_I13din1 : std_logic_vector(7 DOWNTO 0);
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SIGNAL mw_I13din1 : std_logic_vector(7 DOWNTO 0);
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|
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-- Component Declarations
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-- Component Declarations
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COMPONENT FPadd_normalize
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COMPONENT FPadd_normalize
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PORT (
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PORT (
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_in : IN std_logic_vector (27 DOWNTO 0);
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SIG_in : IN std_logic_vector (27 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (27 DOWNTO 0);
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SIG_out : OUT std_logic_vector (27 DOWNTO 0);
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zero : OUT std_logic
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zero : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT FPalign
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COMPONENT FPalign
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PORT (
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PORT (
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A_in : IN std_logic_vector (28 DOWNTO 0);
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A_in : IN std_logic_vector (28 DOWNTO 0);
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B_in : IN std_logic_vector (28 DOWNTO 0);
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B_in : IN std_logic_vector (28 DOWNTO 0);
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cin : IN std_logic ;
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cin : IN std_logic ;
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diff : IN std_logic_vector (8 DOWNTO 0);
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diff : IN std_logic_vector (8 DOWNTO 0);
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A_out : OUT std_logic_vector (28 DOWNTO 0);
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A_out : OUT std_logic_vector (28 DOWNTO 0);
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B_out : OUT std_logic_vector (28 DOWNTO 0)
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B_out : OUT std_logic_vector (28 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT FPinvert
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COMPONENT FPinvert
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GENERIC (
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GENERIC (
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width : integer := 29
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width : integer := 29
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);
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);
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PORT (
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PORT (
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A_in : IN std_logic_vector (width-1 DOWNTO 0);
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A_in : IN std_logic_vector (width-1 DOWNTO 0);
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B_in : IN std_logic_vector (width-1 DOWNTO 0);
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B_in : IN std_logic_vector (width-1 DOWNTO 0);
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invert_A : IN std_logic ;
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invert_A : IN std_logic ;
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invert_B : IN std_logic ;
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invert_B : IN std_logic ;
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A_out : OUT std_logic_vector (width-1 DOWNTO 0);
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A_out : OUT std_logic_vector (width-1 DOWNTO 0);
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B_out : OUT std_logic_vector (width-1 DOWNTO 0)
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B_out : OUT std_logic_vector (width-1 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT FPnormalize
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COMPONENT FPnormalize
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GENERIC (
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GENERIC (
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SIG_width : integer := 28
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SIG_width : integer := 28
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);
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);
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PORT (
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PORT (
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT FPround
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COMPONENT FPround
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GENERIC (
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GENERIC (
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SIG_width : integer := 28
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SIG_width : integer := 28
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);
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);
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PORT (
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PORT (
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT FPselComplement
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COMPONENT FPselComplement
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GENERIC (
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GENERIC (
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SIG_width : integer := 28
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SIG_width : integer := 28
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);
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);
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PORT (
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PORT (
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SIG_in : IN std_logic_vector (SIG_width DOWNTO 0);
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SIG_in : IN std_logic_vector (SIG_width DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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);
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);
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END COMPONENT;
|
END COMPONENT;
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COMPONENT FPswap
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COMPONENT FPswap
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GENERIC (
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GENERIC (
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width : integer := 29
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width : integer := 29
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);
|
);
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PORT (
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PORT (
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A_in : IN std_logic_vector (width-1 DOWNTO 0);
|
A_in : IN std_logic_vector (width-1 DOWNTO 0);
|
B_in : IN std_logic_vector (width-1 DOWNTO 0);
|
B_in : IN std_logic_vector (width-1 DOWNTO 0);
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swap_AB : IN std_logic ;
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swap_AB : IN std_logic ;
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A_out : OUT std_logic_vector (width-1 DOWNTO 0);
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A_out : OUT std_logic_vector (width-1 DOWNTO 0);
|
B_out : OUT std_logic_vector (width-1 DOWNTO 0)
|
B_out : OUT std_logic_vector (width-1 DOWNTO 0)
|
);
|
);
|
END COMPONENT;
|
END COMPONENT;
|
COMPONENT PackFP
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COMPONENT PackFP
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PORT (
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PORT (
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SIGN : IN std_logic ;
|
SIGN : IN std_logic ;
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EXP : IN std_logic_vector (7 DOWNTO 0);
|
EXP : IN std_logic_vector (7 DOWNTO 0);
|
SIG : IN std_logic_vector (22 DOWNTO 0);
|
SIG : IN std_logic_vector (22 DOWNTO 0);
|
isNaN : IN std_logic ;
|
isNaN : IN std_logic ;
|
isINF : IN std_logic ;
|
isINF : IN std_logic ;
|
isZ : IN std_logic ;
|
isZ : IN std_logic ;
|
FP : OUT std_logic_vector (31 DOWNTO 0)
|
FP : OUT std_logic_vector (31 DOWNTO 0)
|
);
|
);
|
END COMPONENT;
|
END COMPONENT;
|
COMPONENT UnpackFP
|
COMPONENT UnpackFP
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PORT (
|
PORT (
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FP : IN std_logic_vector (31 DOWNTO 0);
|
FP : IN std_logic_vector (31 DOWNTO 0);
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SIG : OUT std_logic_vector (31 DOWNTO 0);
|
SIG : OUT std_logic_vector (31 DOWNTO 0);
|
EXP : OUT std_logic_vector (7 DOWNTO 0);
|
EXP : OUT std_logic_vector (7 DOWNTO 0);
|
SIGN : OUT std_logic ;
|
SIGN : OUT std_logic ;
|
isNaN : OUT std_logic ;
|
isNaN : OUT std_logic ;
|
isINF : OUT std_logic ;
|
isINF : OUT std_logic ;
|
isZ : OUT std_logic ;
|
isZ : OUT std_logic ;
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isDN : OUT std_logic
|
isDN : OUT std_logic
|
);
|
);
|
END COMPONENT;
|
END COMPONENT;
|
|
|
-- Optional embedded configurations
|
-- Optional embedded configurations
|
-- pragma synthesis_off
|
-- pragma synthesis_off
|
FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize;
|
FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize;
|
FOR ALL : FPalign USE ENTITY work.FPalign;
|
FOR ALL : FPalign USE ENTITY work.FPalign;
|
FOR ALL : FPinvert USE ENTITY work.FPinvert;
|
FOR ALL : FPinvert USE ENTITY work.FPinvert;
|
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
|
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
|
FOR ALL : FPround USE ENTITY work.FPround;
|
FOR ALL : FPround USE ENTITY work.FPround;
|
FOR ALL : FPselComplement USE ENTITY work.FPselComplement;
|
FOR ALL : FPselComplement USE ENTITY work.FPselComplement;
|
FOR ALL : FPswap USE ENTITY work.FPswap;
|
FOR ALL : FPswap USE ENTITY work.FPswap;
|
FOR ALL : PackFP USE ENTITY work.PackFP;
|
FOR ALL : PackFP USE ENTITY work.PackFP;
|
FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
|
FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
|
-- pragma synthesis_on
|
-- pragma synthesis_on
|
|
|
|
|
BEGIN
|
BEGIN
|
-- Architecture concurrent statements
|
-- Architecture concurrent statements
|
-- HDL Embedded Text Block 1 eb1
|
-- HDL Embedded Text Block 1 eb1
|
-- eb1 1
|
-- eb1 1
|
cin_sub <= (A_isDN OR A_isZ) XOR
|
cin_sub <= (A_isDN OR A_isZ) XOR
|
(B_isDN OR B_isZ);
|
(B_isDN OR B_isZ);
|
|
|
-- HDL Embedded Text Block 2 eb2
|
-- HDL Embedded Text Block 2 eb2
|
-- eb2 2
|
-- eb2 2
|
Z_SIG <= SIG_norm2(25 DOWNTO 3);
|
Z_SIG <= SIG_norm2(25 DOWNTO 3);
|
|
|
-- HDL Embedded Block 3 eb3
|
-- HDL Embedded Block 3 eb3
|
-- Non hierarchical truthtable
|
-- Non hierarchical truthtable
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
eb3_truth_process: PROCESS(ADD_SUB, A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
|
eb3_truth_process: PROCESS(ADD_SUB, A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
BEGIN
|
BEGIN
|
-- Block 1
|
-- Block 1
|
IF (A_isNaN = '1') THEN
|
IF (A_isNaN = '1') THEN
|
isINF_tab <= '0';
|
isINF_tab <= '0';
|
isNaN <= '1';
|
isNaN <= '1';
|
isZ_tab <= '0';
|
isZ_tab <= '0';
|
ELSIF (B_isNaN = '1') THEN
|
ELSIF (B_isNaN = '1') THEN
|
isINF_tab <= '0';
|
isINF_tab <= '0';
|
isNaN <= '1';
|
isNaN <= '1';
|
isZ_tab <= '0';
|
isZ_tab <= '0';
|
ELSIF (ADD_SUB = '1') AND (A_isINF = '1') AND (B_isINF = '1') THEN
|
ELSIF (ADD_SUB = '1') AND (A_isINF = '1') AND (B_isINF = '1') THEN
|
isINF_tab <= '1';
|
isINF_tab <= '1';
|
isNaN <= '0';
|
isNaN <= '0';
|
isZ_tab <= '0';
|
isZ_tab <= '0';
|
ELSIF (ADD_SUB = '0') AND (A_isINF = '1') AND (B_isINF = '1') THEN
|
ELSIF (ADD_SUB = '0') AND (A_isINF = '1') AND (B_isINF = '1') THEN
|
isINF_tab <= '0';
|
isINF_tab <= '0';
|
isNaN <= '1';
|
isNaN <= '1';
|
isZ_tab <= '0';
|
isZ_tab <= '0';
|
ELSIF (A_isINF = '1') THEN
|
ELSIF (A_isINF = '1') THEN
|
isINF_tab <= '1';
|
isINF_tab <= '1';
|
isNaN <= '0';
|
isNaN <= '0';
|
isZ_tab <= '0';
|
isZ_tab <= '0';
|
ELSIF (B_isINF = '1') THEN
|
ELSIF (B_isINF = '1') THEN
|
isINF_tab <= '1';
|
isINF_tab <= '1';
|
isNaN <= '0';
|
isNaN <= '0';
|
isZ_tab <= '0';
|
isZ_tab <= '0';
|
ELSIF (A_isZ = '1') AND (B_isZ = '1') THEN
|
ELSIF (A_isZ = '1') AND (B_isZ = '1') THEN
|
isINF_tab <= '0';
|
isINF_tab <= '0';
|
isNaN <= '0';
|
isNaN <= '0';
|
isZ_tab <= '1';
|
isZ_tab <= '1';
|
ELSE
|
ELSE
|
isINF_tab <= '0';
|
isINF_tab <= '0';
|
isNaN <= '0';
|
isNaN <= '0';
|
isZ_tab <= '0';
|
isZ_tab <= '0';
|
END IF;
|
END IF;
|
|
|
END PROCESS eb3_truth_process;
|
END PROCESS eb3_truth_process;
|
|
|
-- Architecture concurrent statements
|
-- Architecture concurrent statements
|
|
|
|
|
|
|
-- HDL Embedded Text Block 4 eb4
|
-- HDL Embedded Text Block 4 eb4
|
-- eb4 4
|
-- eb4 4
|
mux_sel <= EXP_diff(8);
|
mux_sel <= EXP_diff(8);
|
|
|
-- HDL Embedded Block 5 InvertLogic
|
-- HDL Embedded Block 5 InvertLogic
|
-- Non hierarchical truthtable
|
-- Non hierarchical truthtable
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
InvertLogic_truth_process: PROCESS(A_SIGN, B_XSIGN, EXP_diff)
|
InvertLogic_truth_process: PROCESS(A_SIGN, B_XSIGN, EXP_diff)
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
BEGIN
|
BEGIN
|
-- Block 1
|
-- Block 1
|
IF (A_SIGN = '0') AND (B_XSIGN = '0') THEN
|
IF (A_SIGN = '0') AND (B_XSIGN = '0') THEN
|
invert_A <= '0';
|
invert_A <= '0';
|
invert_B <= '0';
|
invert_B <= '0';
|
ELSIF (A_SIGN = '1') AND (B_XSIGN = '1') THEN
|
ELSIF (A_SIGN = '1') AND (B_XSIGN = '1') THEN
|
invert_A <= '0';
|
invert_A <= '0';
|
invert_B <= '0';
|
invert_B <= '0';
|
ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (EXP_diff(8) = '0') THEN
|
ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (EXP_diff(8) = '0') THEN
|
invert_A <= '0';
|
invert_A <= '0';
|
invert_B <= '1';
|
invert_B <= '1';
|
ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (EXP_diff(8) = '1') THEN
|
ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (EXP_diff(8) = '1') THEN
|
invert_A <= '1';
|
invert_A <= '1';
|
invert_B <= '0';
|
invert_B <= '0';
|
ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (EXP_diff(8) = '0') THEN
|
ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (EXP_diff(8) = '0') THEN
|
invert_A <= '1';
|
invert_A <= '1';
|
invert_B <= '0';
|
invert_B <= '0';
|
ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (EXP_diff(8) = '1') THEN
|
ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (EXP_diff(8) = '1') THEN
|
invert_A <= '0';
|
invert_A <= '0';
|
invert_B <= '1';
|
invert_B <= '1';
|
ELSE
|
ELSE
|
invert_A <= '0';
|
invert_A <= '0';
|
invert_B <= '0';
|
invert_B <= '0';
|
END IF;
|
END IF;
|
|
|
END PROCESS InvertLogic_truth_process;
|
END PROCESS InvertLogic_truth_process;
|
|
|
-- Architecture concurrent statements
|
-- Architecture concurrent statements
|
|
|
|
|
|
|
-- HDL Embedded Block 6 SignLogic
|
-- HDL Embedded Block 6 SignLogic
|
-- Non hierarchical truthtable
|
-- Non hierarchical truthtable
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
SignLogic_truth_process: PROCESS(A_SIGN, B_XSIGN, add_out)
|
SignLogic_truth_process: PROCESS(A_SIGN, B_XSIGN, add_out)
|
---------------------------------------------------------------------------
|
---------------------------------------------------------------------------
|
VARIABLE b1_A_SIGNB_XSIGNadd_out_28 : std_logic_vector(2 DOWNTO 0);
|
VARIABLE b1_A_SIGNB_XSIGNadd_out_28 : std_logic_vector(2 DOWNTO 0);
|
BEGIN
|
BEGIN
|
-- Block 1
|
-- Block 1
|
b1_A_SIGNB_XSIGNadd_out_28 := A_SIGN & B_XSIGN & add_out(28);
|
b1_A_SIGNB_XSIGNadd_out_28 := A_SIGN & B_XSIGN & add_out(28);
|
|
|
CASE b1_A_SIGNB_XSIGNadd_out_28 IS
|
CASE b1_A_SIGNB_XSIGNadd_out_28 IS
|
WHEN "000" =>
|
WHEN "000" =>
|
OV <= '0';
|
OV <= '0';
|
Z_SIGN <= '0';
|
Z_SIGN <= '0';
|
WHEN "001" =>
|
WHEN "001" =>
|
OV <= '1';
|
OV <= '1';
|
Z_SIGN <= '0';
|
Z_SIGN <= '0';
|
WHEN "010" =>
|
WHEN "010" =>
|
OV <= '0';
|
OV <= '0';
|
Z_SIGN <= '0';
|
Z_SIGN <= '0';
|
WHEN "011" =>
|
WHEN "011" =>
|
OV <= '0';
|
OV <= '0';
|
Z_SIGN <= '1';
|
Z_SIGN <= '1';
|
WHEN "100" =>
|
WHEN "100" =>
|
OV <= '0';
|
OV <= '0';
|
Z_SIGN <= '0';
|
Z_SIGN <= '0';
|
WHEN "101" =>
|
WHEN "101" =>
|
OV <= '0';
|
OV <= '0';
|
Z_SIGN <= '1';
|
Z_SIGN <= '1';
|
WHEN "110" =>
|
WHEN "110" =>
|
OV <= '0';
|
OV <= '0';
|
Z_SIGN <= '1';
|
Z_SIGN <= '1';
|
WHEN "111" =>
|
WHEN "111" =>
|
OV <= '1';
|
OV <= '1';
|
Z_SIGN <= '1';
|
Z_SIGN <= '1';
|
WHEN OTHERS =>
|
WHEN OTHERS =>
|
OV <= '0';
|
OV <= '0';
|
Z_SIGN <= '0';
|
Z_SIGN <= '0';
|
END CASE;
|
END CASE;
|
|
|
END PROCESS SignLogic_truth_process;
|
END PROCESS SignLogic_truth_process;
|
|
|
-- Architecture concurrent statements
|
-- Architecture concurrent statements
|
|
|
|
|
|
|
-- HDL Embedded Text Block 7 eb5
|
-- HDL Embedded Text Block 7 eb5
|
-- eb5 7
|
-- eb5 7
|
A_in <= "00" & A_SIG(23 DOWNTO 0) & "000";
|
A_in <= "00" & A_SIG(23 DOWNTO 0) & "000";
|
|
|
-- HDL Embedded Text Block 8 eb6
|
-- HDL Embedded Text Block 8 eb6
|
-- eb6 8
|
-- eb6 8
|
B_in <= "00" & B_SIG(23 DOWNTO 0) & "000";
|
B_in <= "00" & B_SIG(23 DOWNTO 0) & "000";
|
|
|
-- HDL Embedded Text Block 9 eb7
|
-- HDL Embedded Text Block 9 eb7
|
-- eb7 9
|
-- eb7 9
|
EXP_isINF <= '1' WHEN (OV='1' OR Z_EXP=X"FF") ELSE '0';
|
EXP_isINF <= '1' WHEN (OV='1' OR Z_EXP=X"FF") ELSE '0';
|
|
|
-- HDL Embedded Text Block 10 eb8
|
-- HDL Embedded Text Block 10 eb8
|
-- eb8 10
|
-- eb8 10
|
a_exp_in <= "0" & A_EXP;
|
a_exp_in <= "0" & A_EXP;
|
|
|
-- HDL Embedded Text Block 11 eb9
|
-- HDL Embedded Text Block 11 eb9
|
-- eb9 11
|
-- eb9 11
|
b_exp_in <= "0" & B_EXP;
|
b_exp_in <= "0" & B_EXP;
|
|
|
|
|
-- ModuleWare code(v1.1) for instance 'I4' of 'add'
|
-- ModuleWare code(v1.1) for instance 'I4' of 'add'
|
I4combo: PROCESS (a_inv, b_inv, cin)
|
I4combo: PROCESS (a_inv, b_inv, cin)
|
VARIABLE mw_I4t0 : std_logic_vector(29 DOWNTO 0);
|
VARIABLE mw_I4t0 : std_logic_vector(29 DOWNTO 0);
|
VARIABLE mw_I4t1 : std_logic_vector(29 DOWNTO 0);
|
VARIABLE mw_I4t1 : std_logic_vector(29 DOWNTO 0);
|
VARIABLE mw_I4sum : signed(29 DOWNTO 0);
|
VARIABLE mw_I4sum : signed(29 DOWNTO 0);
|
VARIABLE mw_I4carry : std_logic;
|
VARIABLE mw_I4carry : std_logic;
|
BEGIN
|
BEGIN
|
mw_I4t0 := a_inv(28) & a_inv;
|
mw_I4t0 := a_inv(28) & a_inv;
|
mw_I4t1 := b_inv(28) & b_inv;
|
mw_I4t1 := b_inv(28) & b_inv;
|
mw_I4carry := cin;
|
mw_I4carry := cin;
|
mw_I4sum := signed(mw_I4t0) + signed(mw_I4t1) + mw_I4carry;
|
mw_I4sum := signed(mw_I4t0) + signed(mw_I4t1) + mw_I4carry;
|
add_out <= conv_std_logic_vector(mw_I4sum(28 DOWNTO 0),29);
|
add_out <= conv_std_logic_vector(mw_I4sum(28 DOWNTO 0),29);
|
END PROCESS I4combo;
|
END PROCESS I4combo;
|
|
|
-- ModuleWare code(v1.1) for instance 'I13' of 'mux'
|
-- ModuleWare code(v1.1) for instance 'I13' of 'mux'
|
I13combo: PROCESS(mw_I13din0, mw_I13din1, mux_sel)
|
I13combo: PROCESS(mw_I13din0, mw_I13din1, mux_sel)
|
VARIABLE dtemp : std_logic_vector(7 DOWNTO 0);
|
VARIABLE dtemp : std_logic_vector(7 DOWNTO 0);
|
BEGIN
|
BEGIN
|
CASE mux_sel IS
|
CASE mux_sel IS
|
WHEN '0'|'L' => dtemp := mw_I13din0;
|
WHEN '0'|'L' => dtemp := mw_I13din0;
|
WHEN '1'|'H' => dtemp := mw_I13din1;
|
WHEN '1'|'H' => dtemp := mw_I13din1;
|
WHEN OTHERS => dtemp := (OTHERS => 'X');
|
WHEN OTHERS => dtemp := (OTHERS => 'X');
|
END CASE;
|
END CASE;
|
EXP_base <= dtemp;
|
EXP_base <= dtemp;
|
END PROCESS I13combo;
|
END PROCESS I13combo;
|
mw_I13din0 <= A_EXP;
|
mw_I13din0 <= A_EXP;
|
mw_I13din1 <= B_EXP;
|
mw_I13din1 <= B_EXP;
|
|
|
-- ModuleWare code(v1.1) for instance 'I7' of 'or'
|
-- ModuleWare code(v1.1) for instance 'I7' of 'or'
|
isINF <= EXP_isINF OR isINF_tab;
|
isINF <= EXP_isINF OR isINF_tab;
|
|
|
-- ModuleWare code(v1.1) for instance 'I15' of 'or'
|
-- ModuleWare code(v1.1) for instance 'I15' of 'or'
|
cin <= invert_B OR invert_A;
|
cin <= invert_B OR invert_A;
|
|
|
-- ModuleWare code(v1.1) for instance 'I17' of 'or'
|
-- ModuleWare code(v1.1) for instance 'I17' of 'or'
|
isZ <= zero OR isZ_tab;
|
isZ <= zero OR isZ_tab;
|
|
|
-- ModuleWare code(v1.1) for instance 'I3' of 'sub'
|
-- ModuleWare code(v1.1) for instance 'I3' of 'sub'
|
I3combo: PROCESS (a_exp_in, b_exp_in, cin_sub)
|
I3combo: PROCESS (a_exp_in, b_exp_in, cin_sub)
|
VARIABLE mw_I3t0 : std_logic_vector(9 DOWNTO 0);
|
VARIABLE mw_I3t0 : std_logic_vector(9 DOWNTO 0);
|
VARIABLE mw_I3t1 : std_logic_vector(9 DOWNTO 0);
|
VARIABLE mw_I3t1 : std_logic_vector(9 DOWNTO 0);
|
VARIABLE diff : signed(9 DOWNTO 0);
|
VARIABLE diff : signed(9 DOWNTO 0);
|
VARIABLE borrow : std_logic;
|
VARIABLE borrow : std_logic;
|
BEGIN
|
BEGIN
|
mw_I3t0 := a_exp_in(8) & a_exp_in;
|
mw_I3t0 := a_exp_in(8) & a_exp_in;
|
mw_I3t1 := b_exp_in(8) & b_exp_in;
|
mw_I3t1 := b_exp_in(8) & b_exp_in;
|
borrow := cin_sub;
|
borrow := cin_sub;
|
diff := signed(mw_I3t0) - signed(mw_I3t1) - borrow;
|
diff := signed(mw_I3t0) - signed(mw_I3t1) - borrow;
|
EXP_diff <= conv_std_logic_vector(diff(8 DOWNTO 0),9);
|
EXP_diff <= conv_std_logic_vector(diff(8 DOWNTO 0),9);
|
END PROCESS I3combo;
|
END PROCESS I3combo;
|
|
|
-- ModuleWare code(v1.1) for instance 'I16' of 'xnor'
|
-- ModuleWare code(v1.1) for instance 'I16' of 'xnor'
|
B_XSIGN <= NOT(B_SIGN XOR ADD_SUB);
|
B_XSIGN <= NOT(B_SIGN XOR ADD_SUB);
|
|
|
-- Instance port mappings.
|
-- Instance port mappings.
|
I8 : FPadd_normalize
|
I8 : FPadd_normalize
|
PORT MAP (
|
PORT MAP (
|
EXP_in => EXP_selC,
|
EXP_in => EXP_selC,
|
SIG_in => SIG_selC,
|
SIG_in => SIG_selC,
|
EXP_out => EXP_norm,
|
EXP_out => EXP_norm,
|
SIG_out => SIG_norm,
|
SIG_out => SIG_norm,
|
zero => zero
|
zero => zero
|
);
|
);
|
I6 : FPalign
|
I6 : FPalign
|
PORT MAP (
|
PORT MAP (
|
A_in => A_CS,
|
A_in => A_CS,
|
B_in => B_CS,
|
B_in => B_CS,
|
cin => cin_sub,
|
cin => cin_sub,
|
diff => EXP_diff,
|
diff => EXP_diff,
|
A_out => a_align,
|
A_out => a_align,
|
B_out => b_align
|
B_out => b_align
|
);
|
);
|
I14 : FPinvert
|
I14 : FPinvert
|
GENERIC MAP (
|
GENERIC MAP (
|
width => 29
|
width => 29
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
A_in => a_align,
|
A_in => a_align,
|
B_in => b_align,
|
B_in => b_align,
|
invert_A => invert_A,
|
invert_A => invert_A,
|
invert_B => invert_B,
|
invert_B => invert_B,
|
A_out => a_inv,
|
A_out => a_inv,
|
B_out => b_inv
|
B_out => b_inv
|
);
|
);
|
I11 : FPnormalize
|
I11 : FPnormalize
|
GENERIC MAP (
|
GENERIC MAP (
|
SIG_width => 28
|
SIG_width => 28
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
SIG_in => SIG_round,
|
SIG_in => SIG_round,
|
EXP_in => EXP_round,
|
EXP_in => EXP_round,
|
SIG_out => SIG_norm2,
|
SIG_out => SIG_norm2,
|
EXP_out => Z_EXP
|
EXP_out => Z_EXP
|
);
|
);
|
I10 : FPround
|
I10 : FPround
|
GENERIC MAP (
|
GENERIC MAP (
|
SIG_width => 28
|
SIG_width => 28
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
SIG_in => SIG_norm,
|
SIG_in => SIG_norm,
|
EXP_in => EXP_norm,
|
EXP_in => EXP_norm,
|
SIG_out => SIG_round,
|
SIG_out => SIG_round,
|
EXP_out => EXP_round
|
EXP_out => EXP_round
|
);
|
);
|
I12 : FPselComplement
|
I12 : FPselComplement
|
GENERIC MAP (
|
GENERIC MAP (
|
SIG_width => 28
|
SIG_width => 28
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
SIG_in => add_out,
|
SIG_in => add_out,
|
EXP_in => EXP_base,
|
EXP_in => EXP_base,
|
SIG_out => SIG_selC,
|
SIG_out => SIG_selC,
|
EXP_out => EXP_selC
|
EXP_out => EXP_selC
|
);
|
);
|
I5 : FPswap
|
I5 : FPswap
|
GENERIC MAP (
|
GENERIC MAP (
|
width => 29
|
width => 29
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
A_in => A_in,
|
A_in => A_in,
|
B_in => B_in,
|
B_in => B_in,
|
swap_AB => EXP_diff(8),
|
swap_AB => EXP_diff(8),
|
A_out => A_CS,
|
A_out => A_CS,
|
B_out => B_CS
|
B_out => B_CS
|
);
|
);
|
I2 : PackFP
|
I2 : PackFP
|
PORT MAP (
|
PORT MAP (
|
SIGN => Z_SIGN,
|
SIGN => Z_SIGN,
|
EXP => Z_EXP,
|
EXP => Z_EXP,
|
SIG => Z_SIG,
|
SIG => Z_SIG,
|
isNaN => isNaN,
|
isNaN => isNaN,
|
isINF => isINF,
|
isINF => isINF,
|
isZ => isZ,
|
isZ => isZ,
|
FP => FP_Z
|
FP => FP_Z
|
);
|
);
|
I0 : UnpackFP
|
I0 : UnpackFP
|
PORT MAP (
|
PORT MAP (
|
FP => FP_A,
|
FP => FP_A,
|
SIG => A_SIG,
|
SIG => A_SIG,
|
EXP => A_EXP,
|
EXP => A_EXP,
|
SIGN => A_SIGN,
|
SIGN => A_SIGN,
|
isNaN => A_isNaN,
|
isNaN => A_isNaN,
|
isINF => A_isINF,
|
isINF => A_isINF,
|
isZ => A_isZ,
|
isZ => A_isZ,
|
isDN => A_isDN
|
isDN => A_isDN
|
);
|
);
|
I1 : UnpackFP
|
I1 : UnpackFP
|
PORT MAP (
|
PORT MAP (
|
FP => FP_B,
|
FP => FP_B,
|
SIG => B_SIG,
|
SIG => B_SIG,
|
EXP => B_EXP,
|
EXP => B_EXP,
|
SIGN => B_SIGN,
|
SIGN => B_SIGN,
|
isNaN => B_isNaN,
|
isNaN => B_isNaN,
|
isINF => B_isINF,
|
isINF => B_isINF,
|
isZ => B_isZ,
|
isZ => B_isZ,
|
isDN => B_isDN
|
isDN => B_isDN
|
);
|
);
|
|
|
END single_cycle;
|
END single_cycle;
|
|
|
