-- VHDL Entity work.FPadd_stage1.interface
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-- VHDL Entity work.FPadd_stage1.interface
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPadd_stage1 IS
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ENTITY FPadd_stage1 IS
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PORT(
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PORT(
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ADD_SUB : IN std_logic;
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ADD_SUB : IN std_logic;
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FP_A : IN std_logic_vector (31 DOWNTO 0);
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FP_A : IN std_logic_vector (31 DOWNTO 0);
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FP_B : IN std_logic_vector (31 DOWNTO 0);
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FP_B : IN std_logic_vector (31 DOWNTO 0);
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clk : IN std_logic;
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clk : IN std_logic;
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ADD_SUB_out : OUT std_logic;
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ADD_SUB_out : OUT std_logic;
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A_EXP : OUT std_logic_vector (7 DOWNTO 0);
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A_EXP : OUT std_logic_vector (7 DOWNTO 0);
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A_SIGN : OUT std_logic;
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A_SIGN : OUT std_logic;
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A_in : OUT std_logic_vector (28 DOWNTO 0);
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A_in : OUT std_logic_vector (28 DOWNTO 0);
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A_isINF : OUT std_logic;
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A_isINF : OUT std_logic;
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A_isNaN : OUT std_logic;
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A_isNaN : OUT std_logic;
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A_isZ : OUT std_logic;
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A_isZ : OUT std_logic;
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B_EXP : OUT std_logic_vector (7 DOWNTO 0);
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B_EXP : OUT std_logic_vector (7 DOWNTO 0);
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B_XSIGN : OUT std_logic;
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B_XSIGN : OUT std_logic;
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B_in : OUT std_logic_vector (28 DOWNTO 0);
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B_in : OUT std_logic_vector (28 DOWNTO 0);
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B_isINF : OUT std_logic;
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B_isINF : OUT std_logic;
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B_isNaN : OUT std_logic;
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B_isNaN : OUT std_logic;
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B_isZ : OUT std_logic;
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B_isZ : OUT std_logic;
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EXP_diff : OUT std_logic_vector (8 DOWNTO 0);
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EXP_diff : OUT std_logic_vector (8 DOWNTO 0);
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cin_sub : OUT std_logic
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cin_sub : OUT std_logic
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);
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);
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-- Declarations
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-- Declarations
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END FPadd_stage1 ;
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END FPadd_stage1 ;
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--
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--
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-- VHDL Architecture work.FPadd_stage1.struct
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-- VHDL Architecture work.FPadd_stage1.struct
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ARCHITECTURE struct OF FPadd_stage1 IS
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ARCHITECTURE struct OF FPadd_stage1 IS
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-- Architecture declarations
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-- Architecture declarations
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL A_EXP_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL A_EXP_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL A_SIGN_int : std_logic;
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SIGNAL A_SIGN_int : std_logic;
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SIGNAL A_in_int : std_logic_vector(28 DOWNTO 0);
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SIGNAL A_in_int : std_logic_vector(28 DOWNTO 0);
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SIGNAL A_isDN_int : std_logic;
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SIGNAL A_isDN_int : std_logic;
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SIGNAL A_isINF_int : std_logic;
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SIGNAL A_isINF_int : std_logic;
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SIGNAL A_isNaN_int : std_logic;
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SIGNAL A_isNaN_int : std_logic;
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SIGNAL A_isZ_int : std_logic;
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SIGNAL A_isZ_int : std_logic;
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SIGNAL B_EXP_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL B_EXP_int : std_logic_vector(7 DOWNTO 0);
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SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL B_SIGN_int : std_logic;
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SIGNAL B_SIGN_int : std_logic;
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SIGNAL B_XSIGN_int : std_logic;
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SIGNAL B_XSIGN_int : std_logic;
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SIGNAL B_in_int : std_logic_vector(28 DOWNTO 0);
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SIGNAL B_in_int : std_logic_vector(28 DOWNTO 0);
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SIGNAL B_isDN_int : std_logic;
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SIGNAL B_isDN_int : std_logic;
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SIGNAL B_isINF_int : std_logic;
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SIGNAL B_isINF_int : std_logic;
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SIGNAL B_isNaN_int : std_logic;
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SIGNAL B_isNaN_int : std_logic;
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SIGNAL B_isZ_int : std_logic;
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SIGNAL B_isZ_int : std_logic;
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SIGNAL EXP_diff_int : std_logic_vector(8 DOWNTO 0);
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SIGNAL EXP_diff_int : std_logic_vector(8 DOWNTO 0);
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SIGNAL a_exp_in : std_logic_vector(8 DOWNTO 0);
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SIGNAL a_exp_in : std_logic_vector(8 DOWNTO 0);
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SIGNAL b_exp_in : std_logic_vector(8 DOWNTO 0);
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SIGNAL b_exp_in : std_logic_vector(8 DOWNTO 0);
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SIGNAL cin_sub_int : std_logic;
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SIGNAL cin_sub_int : std_logic;
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-- Component Declarations
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-- Component Declarations
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COMPONENT UnpackFP
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COMPONENT UnpackFP
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PORT (
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PORT (
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FP : IN std_logic_vector (31 DOWNTO 0);
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FP : IN std_logic_vector (31 DOWNTO 0);
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SIG : OUT std_logic_vector (31 DOWNTO 0);
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SIG : OUT std_logic_vector (31 DOWNTO 0);
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EXP : OUT std_logic_vector (7 DOWNTO 0);
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EXP : OUT std_logic_vector (7 DOWNTO 0);
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SIGN : OUT std_logic ;
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SIGN : OUT std_logic ;
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isNaN : OUT std_logic ;
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isNaN : OUT std_logic ;
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isINF : OUT std_logic ;
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isINF : OUT std_logic ;
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isZ : OUT std_logic ;
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isZ : OUT std_logic ;
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isDN : OUT std_logic
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isDN : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
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FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
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-- pragma synthesis_on
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-- pragma synthesis_on
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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-- HDL Embedded Text Block 1 eb1
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-- reg1 1
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-- reg1 1
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PROCESS(clk)
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PROCESS(clk)
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BEGIN
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BEGIN
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IF RISING_EDGE(clk) THEN
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IF RISING_EDGE(clk) THEN
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A_SIGN <= A_SIGN_int;
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A_SIGN <= A_SIGN_int;
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B_XSIGN <= B_XSIGN_int;
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B_XSIGN <= B_XSIGN_int;
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A_in <= A_in_int;
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A_in <= A_in_int;
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B_in <= B_in_int;
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B_in <= B_in_int;
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A_EXP <= A_EXP_int;
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A_EXP <= A_EXP_int;
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B_EXP <= B_EXP_int;
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B_EXP <= B_EXP_int;
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EXP_diff <= EXP_diff_int;
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EXP_diff <= EXP_diff_int;
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A_isZ <= A_isZ_int;
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A_isZ <= A_isZ_int;
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B_isZ <= B_isZ_int;
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B_isZ <= B_isZ_int;
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A_isINF <= A_isINF_int;
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A_isINF <= A_isINF_int;
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B_isINF <= B_isINF_int;
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B_isINF <= B_isINF_int;
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A_isNaN <= A_isNaN_int;
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A_isNaN <= A_isNaN_int;
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B_isNaN <= B_isNaN_int;
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B_isNaN <= B_isNaN_int;
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ADD_SUB_out <= ADD_SUB;
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ADD_SUB_out <= ADD_SUB;
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cin_sub <= cin_sub_int;
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cin_sub <= cin_sub_int;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- HDL Embedded Text Block 2 eb2
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-- HDL Embedded Text Block 2 eb2
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-- eb2 2
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-- eb2 2
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a_exp_in <= "0" & A_EXP_int;
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a_exp_in <= "0" & A_EXP_int;
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-- HDL Embedded Text Block 3 eb3
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-- HDL Embedded Text Block 3 eb3
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-- eb3 3
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-- eb3 3
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b_exp_in <= "0" & B_EXP_int;
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b_exp_in <= "0" & B_EXP_int;
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-- HDL Embedded Text Block 4 eb4
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-- HDL Embedded Text Block 4 eb4
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-- eb4 4
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-- eb4 4
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cin_sub_int <= (A_isZ_int OR A_isDN_int) XOR (B_isZ_int OR B_isDN_int);
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cin_sub_int <= (A_isZ_int OR A_isDN_int) XOR (B_isZ_int OR B_isDN_int);
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-- HDL Embedded Text Block 8 eb6
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-- HDL Embedded Text Block 8 eb6
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-- eb5 7
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-- eb5 7
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A_in_int <= "00" & A_SIG(23 DOWNTO 0) & "000";
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A_in_int <= "00" & A_SIG(23 DOWNTO 0) & "000";
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-- HDL Embedded Text Block 10 eb8
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-- HDL Embedded Text Block 10 eb8
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-- eb6 8
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-- eb6 8
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B_in_int <= "00" & B_SIG(23 DOWNTO 0) & "000";
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B_in_int <= "00" & B_SIG(23 DOWNTO 0) & "000";
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-- ModuleWare code(v1.1) for instance 'I5' of 'sub'
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-- ModuleWare code(v1.1) for instance 'I5' of 'sub'
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I5combo: PROCESS (a_exp_in, b_exp_in, cin_sub_int)
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I5combo: PROCESS (a_exp_in, b_exp_in, cin_sub_int)
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VARIABLE mw_I5t0 : std_logic_vector(9 DOWNTO 0);
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VARIABLE mw_I5t0 : std_logic_vector(9 DOWNTO 0);
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VARIABLE mw_I5t1 : std_logic_vector(9 DOWNTO 0);
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VARIABLE mw_I5t1 : std_logic_vector(9 DOWNTO 0);
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VARIABLE diff : signed(9 DOWNTO 0);
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VARIABLE diff : signed(9 DOWNTO 0);
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VARIABLE borrow : std_logic;
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VARIABLE borrow : std_logic;
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BEGIN
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BEGIN
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mw_I5t0 := a_exp_in(8) & a_exp_in;
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mw_I5t0 := a_exp_in(8) & a_exp_in;
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mw_I5t1 := b_exp_in(8) & b_exp_in;
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mw_I5t1 := b_exp_in(8) & b_exp_in;
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borrow := cin_sub_int;
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borrow := cin_sub_int;
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diff := signed(mw_I5t0) - signed(mw_I5t1) - borrow;
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diff := signed(mw_I5t0) - signed(mw_I5t1) - borrow;
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EXP_diff_int <= conv_std_logic_vector(diff(8 DOWNTO 0),9);
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EXP_diff_int <= conv_std_logic_vector(diff(8 DOWNTO 0),9);
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END PROCESS I5combo;
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END PROCESS I5combo;
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-- ModuleWare code(v1.1) for instance 'I18' of 'xnor'
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-- ModuleWare code(v1.1) for instance 'I18' of 'xnor'
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B_XSIGN_int <= NOT(B_SIGN_int XOR ADD_SUB);
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B_XSIGN_int <= NOT(B_SIGN_int XOR ADD_SUB);
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-- Instance port mappings.
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-- Instance port mappings.
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I1 : UnpackFP
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I1 : UnpackFP
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PORT MAP (
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PORT MAP (
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FP => FP_A,
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FP => FP_A,
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SIG => A_SIG,
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SIG => A_SIG,
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EXP => A_EXP_int,
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EXP => A_EXP_int,
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SIGN => A_SIGN_int,
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SIGN => A_SIGN_int,
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isNaN => A_isNaN_int,
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isNaN => A_isNaN_int,
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isINF => A_isINF_int,
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isINF => A_isINF_int,
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isZ => A_isZ_int,
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isZ => A_isZ_int,
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isDN => A_isDN_int
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isDN => A_isDN_int
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);
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);
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I3 : UnpackFP
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I3 : UnpackFP
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PORT MAP (
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PORT MAP (
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FP => FP_B,
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FP => FP_B,
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SIG => B_SIG,
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SIG => B_SIG,
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EXP => B_EXP_int,
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EXP => B_EXP_int,
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SIGN => B_SIGN_int,
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SIGN => B_SIGN_int,
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isNaN => B_isNaN_int,
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isNaN => B_isNaN_int,
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isINF => B_isINF_int,
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isINF => B_isINF_int,
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isZ => B_isZ_int,
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isZ => B_isZ_int,
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isDN => B_isDN_int
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isDN => B_isDN_int
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);
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);
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END struct;
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END struct;
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