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[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [adder/] [fpswap_fpswap.vhd] - Diff between revs 3 and 5
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--
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--
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-- VHDL Architecture HAVOC.FPswap.FPswap
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-- VHDL Architecture HAVOC.FPswap.FPswap
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--
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--
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-- Created:
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-- Created:
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-- by - Guillermo
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-- by - Guillermo
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-- at - ITESM, 20:19:07 07/19/03
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-- at - ITESM, 20:19:07 07/19/03
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--
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
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-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
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--
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--
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-- hds interface_start
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-- hds interface_start
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPswap IS
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ENTITY FPswap IS
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GENERIC(
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GENERIC(
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width : integer := 29
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width : integer := 29
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);
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);
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PORT(
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PORT(
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A_in : IN std_logic_vector (width-1 DOWNTO 0);
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A_in : IN std_logic_vector (width-1 DOWNTO 0);
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B_in : IN std_logic_vector (width-1 DOWNTO 0);
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B_in : IN std_logic_vector (width-1 DOWNTO 0);
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swap_AB : IN std_logic;
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swap_AB : IN std_logic;
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A_out : OUT std_logic_vector (width-1 DOWNTO 0);
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A_out : OUT std_logic_vector (width-1 DOWNTO 0);
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B_out : OUT std_logic_vector (width-1 DOWNTO 0)
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B_out : OUT std_logic_vector (width-1 DOWNTO 0)
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);
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);
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-- Declarations
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-- Declarations
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END FPswap ;
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END FPswap ;
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-- hds interface_end
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-- hds interface_end
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ARCHITECTURE FPswap OF FPswap IS
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ARCHITECTURE FPswap OF FPswap IS
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BEGIN
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BEGIN
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PROCESS(A_in, B_in, swap_AB)
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PROCESS(A_in, B_in, swap_AB)
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BEGIN
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BEGIN
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IF (swap_AB='1') THEN
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IF (swap_AB='1') THEN
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A_out <= B_in;
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A_out <= B_in;
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B_out <= A_in;
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B_out <= A_in;
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ELSE
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ELSE
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A_out <= A_in;
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A_out <= A_in;
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B_out <= B_in;
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B_out <= B_in;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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END FPswap;
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END FPswap;
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