-- VHDL Entity HAVOC.FPmul.symbol
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-- VHDL Entity HAVOC.FPmul.symbol
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--
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--
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-- Created by
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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-- using Mentor Graphics FPGA Advantage tools.
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--
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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--
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-- 2003-2004. V1.0
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-- 2003-2004. V1.0
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--
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--
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|
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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|
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ENTITY FPmul IS
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ENTITY FPmul IS
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PORT(
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PORT(
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FP_A : IN std_logic_vector (31 DOWNTO 0);
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FP_A : IN std_logic_vector (31 DOWNTO 0);
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FP_B : IN std_logic_vector (31 DOWNTO 0);
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FP_B : IN std_logic_vector (31 DOWNTO 0);
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clk : IN std_logic;
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clk : IN std_logic;
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FP_Z : OUT std_logic_vector (31 DOWNTO 0)
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FP_Z : OUT std_logic_vector (31 DOWNTO 0)
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);
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);
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-- Declarations
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-- Declarations
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|
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END FPmul ;
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END FPmul ;
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|
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--
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--
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-- VHDL Architecture HAVOC.FPmul.single_cycle
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-- VHDL Architecture HAVOC.FPmul.single_cycle
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--
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--
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-- Created by
|
-- Created by
|
-- Guillermo Marcus, gmarcus@ieee.org
|
-- Guillermo Marcus, gmarcus@ieee.org
|
-- using Mentor Graphics FPGA Advantage tools.
|
-- using Mentor Graphics FPGA Advantage tools.
|
--
|
--
|
-- Visit "http://fpga.mty.itesm.mx" for more info.
|
-- Visit "http://fpga.mty.itesm.mx" for more info.
|
--
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--
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-- Copyright 2003-2004. V1.0
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-- Copyright 2003-2004. V1.0
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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|
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LIBRARY HAVOC;
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ARCHITECTURE single_cycle OF FPmul IS
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ARCHITECTURE single_cycle OF FPmul IS
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|
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-- Architecture declarations
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-- Architecture declarations
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-- Non hierarchical truthtable declarations
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-- Non hierarchical truthtable declarations
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|
|
|
|
|
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-- Internal signal declarations
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-- Internal signal declarations
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SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL A_SIGN : std_logic;
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SIGNAL A_SIGN : std_logic;
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SIGNAL A_isINF : std_logic;
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SIGNAL A_isINF : std_logic;
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SIGNAL A_isNaN : std_logic;
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SIGNAL A_isNaN : std_logic;
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SIGNAL A_isZ : std_logic;
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SIGNAL A_isZ : std_logic;
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SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
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SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
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SIGNAL B_SIGN : std_logic;
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SIGNAL B_SIGN : std_logic;
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SIGNAL B_isINF : std_logic;
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SIGNAL B_isINF : std_logic;
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SIGNAL B_isNaN : std_logic;
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SIGNAL B_isNaN : std_logic;
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SIGNAL B_isZ : std_logic;
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SIGNAL B_isZ : std_logic;
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SIGNAL EXP_addout : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_addout : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_in : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_in : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_out_norm : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_out_norm : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_out_round : std_logic_vector(7 DOWNTO 0);
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SIGNAL EXP_out_round : std_logic_vector(7 DOWNTO 0);
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SIGNAL SIGN_out : std_logic;
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SIGNAL SIGN_out : std_logic;
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SIGNAL SIG_in : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_in : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_isZ : std_logic;
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SIGNAL SIG_isZ : std_logic;
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SIGNAL SIG_out : std_logic_vector(22 DOWNTO 0);
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SIGNAL SIG_out : std_logic_vector(22 DOWNTO 0);
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SIGNAL SIG_out_norm : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_out_norm : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_out_norm2 : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_out_norm2 : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_out_round : std_logic_vector(27 DOWNTO 0);
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SIGNAL SIG_out_round : std_logic_vector(27 DOWNTO 0);
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SIGNAL dout : std_logic;
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SIGNAL dout : std_logic;
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SIGNAL isINF : std_logic;
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SIGNAL isINF : std_logic;
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SIGNAL isINF_tab : std_logic;
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SIGNAL isINF_tab : std_logic;
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SIGNAL isNaN : std_logic;
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SIGNAL isNaN : std_logic;
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SIGNAL isZ : std_logic;
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SIGNAL isZ : std_logic;
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SIGNAL isZ_tab : std_logic;
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SIGNAL isZ_tab : std_logic;
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SIGNAL prod : std_logic_vector(63 DOWNTO 0);
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SIGNAL prod : std_logic_vector(63 DOWNTO 0);
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|
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|
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-- Component Declarations
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-- Component Declarations
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COMPONENT FPnormalize
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COMPONENT FPnormalize
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GENERIC (
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GENERIC (
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SIG_width : integer := 28
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SIG_width : integer := 28
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);
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);
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PORT (
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PORT (
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT FPround
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COMPONENT FPround
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GENERIC (
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GENERIC (
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SIG_width : integer := 28
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SIG_width : integer := 28
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);
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);
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PORT (
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PORT (
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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EXP_in : IN std_logic_vector (7 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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EXP_out : OUT std_logic_vector (7 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT PackFP
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COMPONENT PackFP
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PORT (
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PORT (
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SIGN : IN std_logic ;
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SIGN : IN std_logic ;
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EXP : IN std_logic_vector (7 DOWNTO 0);
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EXP : IN std_logic_vector (7 DOWNTO 0);
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SIG : IN std_logic_vector (22 DOWNTO 0);
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SIG : IN std_logic_vector (22 DOWNTO 0);
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isNaN : IN std_logic ;
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isNaN : IN std_logic ;
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isINF : IN std_logic ;
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isINF : IN std_logic ;
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isZ : IN std_logic ;
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isZ : IN std_logic ;
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FP : OUT std_logic_vector (31 DOWNTO 0)
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FP : OUT std_logic_vector (31 DOWNTO 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT UnpackFP
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COMPONENT UnpackFP
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PORT (
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PORT (
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FP : IN std_logic_vector (31 DOWNTO 0);
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FP : IN std_logic_vector (31 DOWNTO 0);
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SIG : OUT std_logic_vector (31 DOWNTO 0);
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SIG : OUT std_logic_vector (31 DOWNTO 0);
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EXP : OUT std_logic_vector (7 DOWNTO 0);
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EXP : OUT std_logic_vector (7 DOWNTO 0);
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SIGN : OUT std_logic ;
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SIGN : OUT std_logic ;
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isNaN : OUT std_logic ;
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isNaN : OUT std_logic ;
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isINF : OUT std_logic ;
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isINF : OUT std_logic ;
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isZ : OUT std_logic ;
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isZ : OUT std_logic ;
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isDN : OUT std_logic
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isDN : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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|
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-- Optional embedded configurations
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-- Optional embedded configurations
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-- pragma synthesis_off
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-- pragma synthesis_off
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FOR ALL : FPnormalize USE ENTITY HAVOC.FPnormalize;
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FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
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FOR ALL : FPround USE ENTITY HAVOC.FPround;
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FOR ALL : FPround USE ENTITY work.FPround;
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FOR ALL : PackFP USE ENTITY HAVOC.PackFP;
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FOR ALL : PackFP USE ENTITY work.PackFP;
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FOR ALL : UnpackFP USE ENTITY HAVOC.UnpackFP;
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FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
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-- pragma synthesis_on
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-- pragma synthesis_on
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|
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BEGIN
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BEGIN
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-- Architecture concurrent statements
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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-- HDL Embedded Text Block 1 eb1
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-- eb1 1
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-- eb1 1
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SIG_in <= prod(47 DOWNTO 20);
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SIG_in <= prod(47 DOWNTO 20);
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|
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-- HDL Embedded Text Block 2 eb2
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-- HDL Embedded Text Block 2 eb2
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-- eb2
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-- eb2
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SIG_out <= SIG_out_norm2(25 DOWNTO 3);
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SIG_out <= SIG_out_norm2(25 DOWNTO 3);
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-- HDL Embedded Text Block 3 eb3
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-- HDL Embedded Text Block 3 eb3
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-- eb3 3
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-- eb3 3
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PROCESS(isZ,isINF_tab, A_EXP, B_EXP, EXP_out)
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PROCESS(isZ,isINF_tab, A_EXP, B_EXP, EXP_out)
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BEGIN
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BEGIN
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IF isZ='0' THEN
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IF isZ='0' THEN
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IF isINF_tab='1' THEN
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IF isINF_tab='1' THEN
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isINF <= '1';
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isINF <= '1';
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ELSIF EXP_out=X"FF" THEN
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ELSIF EXP_out=X"FF" THEN
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isINF <='1';
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isINF <='1';
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ELSIF (A_EXP(7)='1' AND B_EXP(7)='1' AND (EXP_out(7)='0')) THEN
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ELSIF (A_EXP(7)='1' AND B_EXP(7)='1' AND (EXP_out(7)='0')) THEN
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isINF <='1';
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isINF <='1';
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ELSE
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ELSE
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isINF <= '0';
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isINF <= '0';
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END IF;
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END IF;
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ELSE
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ELSE
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isINF <= '0';
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isINF <= '0';
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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|
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-- HDL Embedded Block 4 eb4
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-- HDL Embedded Block 4 eb4
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-- Non hierarchical truthtable
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-- Non hierarchical truthtable
|
---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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eb4_truth_process: PROCESS(A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
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eb4_truth_process: PROCESS(A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
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---------------------------------------------------------------------------
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---------------------------------------------------------------------------
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BEGIN
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BEGIN
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-- Block 1
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-- Block 1
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IF (A_isINF = '0') AND (A_isNaN = '0') AND (A_isZ = '0') AND (B_isINF = '0') AND (B_isNaN = '0') AND (B_isZ = '0') THEN
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IF (A_isINF = '0') AND (A_isNaN = '0') AND (A_isZ = '0') AND (B_isINF = '0') AND (B_isNaN = '0') AND (B_isZ = '0') THEN
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isZ_tab <= '0';
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isZ_tab <= '0';
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isINF_tab <= '0';
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isINF_tab <= '0';
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isNaN <= '0';
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isNaN <= '0';
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ELSIF (A_isINF = '1') AND (B_isZ = '1') THEN
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ELSIF (A_isINF = '1') AND (B_isZ = '1') THEN
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isZ_tab <= '0';
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isZ_tab <= '0';
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isINF_tab <= '0';
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isINF_tab <= '0';
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isNaN <= '1';
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isNaN <= '1';
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ELSIF (A_isZ = '1') AND (B_isINF = '1') THEN
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ELSIF (A_isZ = '1') AND (B_isINF = '1') THEN
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isZ_tab <= '0';
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isZ_tab <= '0';
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isINF_tab <= '0';
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isINF_tab <= '0';
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isNaN <= '1';
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isNaN <= '1';
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ELSIF (A_isINF = '1') THEN
|
ELSIF (A_isINF = '1') THEN
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isZ_tab <= '0';
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isZ_tab <= '0';
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isINF_tab <= '1';
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isINF_tab <= '1';
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isNaN <= '0';
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isNaN <= '0';
|
ELSIF (B_isINF = '1') THEN
|
ELSIF (B_isINF = '1') THEN
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isZ_tab <= '0';
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isZ_tab <= '0';
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isINF_tab <= '1';
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isINF_tab <= '1';
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isNaN <= '0';
|
isNaN <= '0';
|
ELSIF (A_isNaN = '1') THEN
|
ELSIF (A_isNaN = '1') THEN
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isZ_tab <= '0';
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isZ_tab <= '0';
|
isINF_tab <= '0';
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isINF_tab <= '0';
|
isNaN <= '1';
|
isNaN <= '1';
|
ELSIF (B_isNaN = '1') THEN
|
ELSIF (B_isNaN = '1') THEN
|
isZ_tab <= '0';
|
isZ_tab <= '0';
|
isINF_tab <= '0';
|
isINF_tab <= '0';
|
isNaN <= '1';
|
isNaN <= '1';
|
ELSIF (A_isZ = '1') THEN
|
ELSIF (A_isZ = '1') THEN
|
isZ_tab <= '1';
|
isZ_tab <= '1';
|
isINF_tab <= '0';
|
isINF_tab <= '0';
|
isNaN <= '0';
|
isNaN <= '0';
|
ELSIF (B_isZ = '1') THEN
|
ELSIF (B_isZ = '1') THEN
|
isZ_tab <= '1';
|
isZ_tab <= '1';
|
isINF_tab <= '0';
|
isINF_tab <= '0';
|
isNaN <= '0';
|
isNaN <= '0';
|
ELSE
|
ELSE
|
isZ_tab <= '0';
|
isZ_tab <= '0';
|
isINF_tab <= '0';
|
isINF_tab <= '0';
|
isNaN <= '0';
|
isNaN <= '0';
|
END IF;
|
END IF;
|
|
|
END PROCESS eb4_truth_process;
|
END PROCESS eb4_truth_process;
|
|
|
-- Architecture concurrent statements
|
-- Architecture concurrent statements
|
|
|
|
|
|
|
-- HDL Embedded Text Block 5 eb5
|
-- HDL Embedded Text Block 5 eb5
|
-- eb5 5
|
-- eb5 5
|
EXP_in <= (NOT EXP_addout(7)) & EXP_addout(6 DOWNTO 0);
|
EXP_in <= (NOT EXP_addout(7)) & EXP_addout(6 DOWNTO 0);
|
|
|
-- HDL Embedded Text Block 6 eb6
|
-- HDL Embedded Text Block 6 eb6
|
-- eb6 6
|
-- eb6 6
|
PROCESS(SIG_out_norm2,A_EXP,B_EXP, EXP_out)
|
PROCESS(SIG_out_norm2,A_EXP,B_EXP, EXP_out)
|
BEGIN
|
BEGIN
|
IF (EXP_out(7)='1' AND A_EXP(7)='0' AND B_EXP(7)='0') OR
|
IF ( EXP_out(7)='1' AND
|
(SIG_out_norm2(26 DOWNTO 3)="000000000000000000000000") THEN
|
( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND
|
|
(B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ) OR
|
|
(SIG_out_norm2(26 DOWNTO 3)=X"000000") THEN
|
-- Underflow or zero significand
|
-- Underflow or zero significand
|
SIG_isZ <= '1';
|
SIG_isZ <= '1';
|
ELSE
|
ELSE
|
SIG_isZ <= '0';
|
SIG_isZ <= '0';
|
END IF;
|
END IF;
|
END PROCESS;
|
END PROCESS;
|
|
|
|
|
-- ModuleWare code(v1.1) for instance 'I4' of 'add'
|
-- ModuleWare code(v1.1) for instance 'I4' of 'add'
|
I4combo: PROCESS (A_EXP, B_EXP, dout)
|
I4combo: PROCESS (A_EXP, B_EXP, dout)
|
VARIABLE mw_I4t0 : std_logic_vector(8 DOWNTO 0);
|
VARIABLE mw_I4t0 : std_logic_vector(8 DOWNTO 0);
|
VARIABLE mw_I4t1 : std_logic_vector(8 DOWNTO 0);
|
VARIABLE mw_I4t1 : std_logic_vector(8 DOWNTO 0);
|
VARIABLE mw_I4sum : unsigned(8 DOWNTO 0);
|
VARIABLE mw_I4sum : unsigned(8 DOWNTO 0);
|
VARIABLE mw_I4carry : std_logic;
|
VARIABLE mw_I4carry : std_logic;
|
BEGIN
|
BEGIN
|
mw_I4t0 := '0' & A_EXP;
|
mw_I4t0 := '0' & A_EXP;
|
mw_I4t1 := '0' & B_EXP;
|
mw_I4t1 := '0' & B_EXP;
|
mw_I4carry := dout;
|
mw_I4carry := dout;
|
mw_I4sum := unsigned(mw_I4t0) + unsigned(mw_I4t1) + mw_I4carry;
|
mw_I4sum := unsigned(mw_I4t0) + unsigned(mw_I4t1) + mw_I4carry;
|
EXP_addout <= conv_std_logic_vector(mw_I4sum(7 DOWNTO 0),8);
|
EXP_addout <= conv_std_logic_vector(mw_I4sum(7 DOWNTO 0),8);
|
END PROCESS I4combo;
|
END PROCESS I4combo;
|
|
|
-- ModuleWare code(v1.1) for instance 'I2' of 'mult'
|
-- ModuleWare code(v1.1) for instance 'I2' of 'mult'
|
I2combo : PROCESS (A_SIG, B_SIG)
|
I2combo : PROCESS (A_SIG, B_SIG)
|
VARIABLE dtemp : unsigned(63 DOWNTO 0);
|
VARIABLE dtemp : unsigned(63 DOWNTO 0);
|
BEGIN
|
BEGIN
|
dtemp := (unsigned(A_SIG) * unsigned(B_SIG));
|
dtemp := (unsigned(A_SIG) * unsigned(B_SIG));
|
prod <= std_logic_vector(dtemp);
|
prod <= std_logic_vector(dtemp);
|
END PROCESS I2combo;
|
END PROCESS I2combo;
|
|
|
-- ModuleWare code(v1.1) for instance 'I7' of 'or'
|
-- ModuleWare code(v1.1) for instance 'I7' of 'or'
|
isZ <= SIG_isZ OR isZ_tab;
|
isZ <= SIG_isZ OR isZ_tab;
|
|
|
-- ModuleWare code(v1.1) for instance 'I6' of 'vdd'
|
-- ModuleWare code(v1.1) for instance 'I6' of 'vdd'
|
dout <= '1';
|
dout <= '1';
|
|
|
-- ModuleWare code(v1.1) for instance 'I3' of 'xor'
|
-- ModuleWare code(v1.1) for instance 'I3' of 'xor'
|
SIGN_out <= A_SIGN XOR B_SIGN;
|
SIGN_out <= A_SIGN XOR B_SIGN;
|
|
|
-- Instance port mappings.
|
-- Instance port mappings.
|
I9 : FPnormalize
|
I9 : FPnormalize
|
GENERIC MAP (
|
GENERIC MAP (
|
SIG_width => 28
|
SIG_width => 28
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
SIG_in => SIG_in,
|
SIG_in => SIG_in,
|
EXP_in => EXP_in,
|
EXP_in => EXP_in,
|
SIG_out => SIG_out_norm,
|
SIG_out => SIG_out_norm,
|
EXP_out => EXP_out_norm
|
EXP_out => EXP_out_norm
|
);
|
);
|
I10 : FPnormalize
|
I10 : FPnormalize
|
GENERIC MAP (
|
GENERIC MAP (
|
SIG_width => 28
|
SIG_width => 28
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
SIG_in => SIG_out_round,
|
SIG_in => SIG_out_round,
|
EXP_in => EXP_out_round,
|
EXP_in => EXP_out_round,
|
SIG_out => SIG_out_norm2,
|
SIG_out => SIG_out_norm2,
|
EXP_out => EXP_out
|
EXP_out => EXP_out
|
);
|
);
|
I11 : FPround
|
I11 : FPround
|
GENERIC MAP (
|
GENERIC MAP (
|
SIG_width => 28
|
SIG_width => 28
|
)
|
)
|
PORT MAP (
|
PORT MAP (
|
SIG_in => SIG_out_norm,
|
SIG_in => SIG_out_norm,
|
EXP_in => EXP_out_norm,
|
EXP_in => EXP_out_norm,
|
SIG_out => SIG_out_round,
|
SIG_out => SIG_out_round,
|
EXP_out => EXP_out_round
|
EXP_out => EXP_out_round
|
);
|
);
|
I5 : PackFP
|
I5 : PackFP
|
PORT MAP (
|
PORT MAP (
|
SIGN => SIGN_out,
|
SIGN => SIGN_out,
|
EXP => EXP_out,
|
EXP => EXP_out,
|
SIG => SIG_out,
|
SIG => SIG_out,
|
isNaN => isNaN,
|
isNaN => isNaN,
|
isINF => isINF,
|
isINF => isINF,
|
isZ => isZ,
|
isZ => isZ,
|
FP => FP_Z
|
FP => FP_Z
|
);
|
);
|
I0 : UnpackFP
|
I0 : UnpackFP
|
PORT MAP (
|
PORT MAP (
|
FP => FP_A,
|
FP => FP_A,
|
SIG => A_SIG,
|
SIG => A_SIG,
|
EXP => A_EXP,
|
EXP => A_EXP,
|
SIGN => A_SIGN,
|
SIGN => A_SIGN,
|
isNaN => A_isNaN,
|
isNaN => A_isNaN,
|
isINF => A_isINF,
|
isINF => A_isINF,
|
isZ => A_isZ,
|
isZ => A_isZ,
|
isDN => OPEN
|
isDN => OPEN
|
);
|
);
|
I1 : UnpackFP
|
I1 : UnpackFP
|
PORT MAP (
|
PORT MAP (
|
FP => FP_B,
|
FP => FP_B,
|
SIG => B_SIG,
|
SIG => B_SIG,
|
EXP => B_EXP,
|
EXP => B_EXP,
|
SIGN => B_SIGN,
|
SIGN => B_SIGN,
|
isNaN => B_isNaN,
|
isNaN => B_isNaN,
|
isINF => B_isINF,
|
isINF => B_isINF,
|
isZ => B_isZ,
|
isZ => B_isZ,
|
isDN => OPEN
|
isDN => OPEN
|
);
|
);
|
|
|
END single_cycle;
|
END single_cycle;
|
|
|