--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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-- Title : FT245R interface
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-- Title : FT245R interface
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-- File : ft245rl_interface.vhd
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-- File : ft245rl_interface.vhd
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-- Author : Alexey Lyashko <pradd@opencores.org>
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-- Author : Alexey Lyashko <pradd@opencores.org>
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-- License : LGPL
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-- License : LGPL
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--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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-- Description :
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-- Description :
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-- The controller simplifies the communication with FT245R chip. While
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-- The controller simplifies the communication with FT245R chip. While
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-- provided interface is very similar to that of the chip itself,
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-- provided interface is very similar to that of the chip itself,
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-- this controller takes care of all the delays and other aspects of
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-- this controller takes care of all the delays and other aspects of
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-- FT245R's protocol as well as provifes separate ports for input and
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-- FT245R's protocol as well as provifes separate ports for input and
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-- output.
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-- output.
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--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity ft245rl_interface is
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entity ft245rl_interface is
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-- This value is for 400MHz clock. Change it to suit your configuration.
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-- This value is for 400MHz clock. Change it to suit your configuration.
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generic (min_delay : real := 2.5);
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generic (min_delay : real := 2.5);
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port
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port
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(
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(
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-- physical FT245RL interface
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-- physical FT245RL interface
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data_io : inout std_logic_vector(7 downto 0);
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data_io : inout std_logic_vector(7 downto 0);
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nrst : out std_logic := '1';
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nrst : out std_logic := '1';
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ntxe : in std_logic;
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ntxe : in std_logic;
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nrxf : in std_logic;
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nrxf : in std_logic;
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nwr : out std_logic := '0';
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nwr : out std_logic := '0';
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nrd : out std_logic := '1';
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nrd : out std_logic := '1';
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-- logical interface
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-- logical interface
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clk : in std_logic; -- System clock
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clk : in std_logic; -- System clock
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data_in : in std_logic_vector(7 downto 0); -- Input from client entity
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data_in : in std_logic_vector(7 downto 0); -- Input from client entity
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data_out : out std_logic_vector(7 downto 0); -- Output to client entity
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data_out : out std_logic_vector(7 downto 0); -- Output to client entity
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nce : in std_logic := '1'; -- "Chip" enable
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nce : in std_logic := '1'; -- "Chip" enable
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fetch_next_byte : in std_logic := '0'; -- Strobing this to '1' instructs the module to poll FT245RL for next available byte
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fetch_next_byte : in std_logic := '0'; -- Strobing this to '1' instructs the module to poll FT245RL for next available byte
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do_write : in std_logic := '0'; -- Strobing this to '1' instructs the module to write byte to FT245RL
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do_write : in std_logic := '0'; -- Strobing this to '1' instructs the module to write byte to FT245RL
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busy : out std_logic := '0'; -- Is '1' when the module is processing data
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busy : out std_logic := '0'; -- Is '1' when the module is processing data
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data_available : buffer std_logic := '0'; -- Notifies the client of data availability
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data_available : buffer std_logic := '0'; -- Notifies the client of data availability
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reset : in std_logic := '1' -- Resets the module
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reset : in std_logic := '1' -- Resets the module
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);
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);
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end ft245rl_interface;
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end ft245rl_interface;
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architecture action of ft245rl_interface is
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architecture action of ft245rl_interface is
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type state_t is (
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type state_t is (
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INIT,
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INIT,
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IDLE,
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IDLE,
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READ_BYTE,
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READ_BYTE,
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READ_BYTE1,
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READ_BYTE1,
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READ_BYTE2,
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READ_BYTE2,
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READ_BYTE3,
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READ_BYTE3,
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WRITE_BYTE,
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WRITE_BYTE,
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WRITE_BYTE1,
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WRITE_BYTE1,
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WRITE_BYTE2,
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WRITE_BYTE2,
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WRITE_BYTE3,
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WRITE_BYTE3,
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DO_DELAY
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DO_DELAY
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);
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);
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signal c_state : state_t := INIT; -- current state
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signal c_state : state_t := INIT; -- current state
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signal n_state : state_t := INIT; -- next state
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signal n_state : state_t := INIT; -- next state
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signal delay_cnt:integer := 0; -- Delay counter register
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signal delay_cnt:integer := 0; -- Delay counter register
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signal current_delay : integer := 0; -- This register holds number of clock cycles
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signal current_delay : integer := 0; -- This register holds number of clock cycles
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-- needed by the specified delay
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-- needed by the specified delay
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signal in_buff : std_logic_vector(7 downto 0); -- holds data received from FT245RL
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signal in_buff : std_logic_vector(7 downto 0); -- holds data received from FT245RL
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signal out_buff: std_logic_vector(7 downto 0); -- holds data to be sent to FT245RL
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signal out_buff: std_logic_vector(7 downto 0); -- holds data to be sent to FT245RL
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signal we : std_logic := '0'; -- enables data output to FT245RL
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signal we : std_logic := '0'; -- enables data output to FT245RL
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-- All delay specs may be found in FT245RL datasheet at
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-- All delay specs may be found in FT245RL datasheet at
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-- http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT245R.pdf
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-- http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT245R.pdf
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constant t1_delay : integer := integer(50.0 / min_delay) - 1;
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constant t1_delay : integer := integer(50.0 / min_delay) - 1;
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constant t2_delay : integer := integer((50.0 + 80.0) / min_delay) - 1;
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constant t2_delay : integer := integer((50.0 + 80.0) / min_delay) - 1;
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constant t3_delay : integer := integer(35.0 / min_delay) - 1;
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constant t3_delay : integer := integer(35.0 / min_delay) - 1;
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constant t4_delay : integer := 0;
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constant t4_delay : integer := 0;
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constant t5_delay : integer := integer(25.0 / min_delay) - 1;
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constant t5_delay : integer := integer(25.0 / min_delay) - 1;
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constant t6_delay : integer := integer(80.0 / min_delay) - 1;
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constant t6_delay : integer := integer(80.0 / min_delay) - 1;
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constant t7_delay : integer := integer(50.0 / min_delay) - 1;
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constant t7_delay : integer := integer(50.0 / min_delay) - 1;
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constant t8_delay : integer := integer(50.0 / min_delay) - 1;
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constant t8_delay : integer := integer(50.0 / min_delay) - 1;
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constant t9_delay : integer := integer(20.0 / min_delay) - 1;
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constant t9_delay : integer := integer(20.0 / min_delay) - 1;
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constant t10_delay : integer := 0;
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constant t10_delay : integer := 0;
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constant t11_delay : integer := integer(25.0 / min_delay) - 1;
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constant t11_delay : integer := integer(25.0 / min_delay) - 1;
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constant t12_delay : integer := integer(80.0 / min_delay) - 1;
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constant t12_delay : integer := integer(80.0 / min_delay) - 1;
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begin
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begin
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-- Bidirectional bus implementation.
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-- Bidirectional bus implementation.
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data_io <= out_buff when we = '1' else
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data_io <= out_buff when we = '1' else
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"ZZZZZZZZ" when we = '0' else
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"ZZZZZZZZ" when we = '0' else
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"XXXXXXXX";
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"XXXXXXXX";
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in_buff <= data_io;
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in_buff <= data_io;
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process(clk, reset, nrxf, ntxe, nce)
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process(clk, reset, nrxf, ntxe, nce)
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begin
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begin
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if(reset = '0')then
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if(reset = '0')then
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c_state <= INIT;
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c_state <= INIT;
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elsif(rising_edge(clk) and nce = '0')then
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elsif(rising_edge(clk) and nce = '0')then
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case c_state is
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case c_state is
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-- The module enters this state on powerup or when 'reset' is low.
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-- The module enters this state on powerup or when 'reset' is low.
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when INIT =>
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when INIT =>
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delay_cnt <= 0;
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delay_cnt <= 0;
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current_delay <= 0;
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current_delay <= 0;
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c_state <= IDLE;
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c_state <= IDLE;
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nrst <= '0'; -- Reset FT245RL on init
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nrst <= '0'; -- Reset FT245RL on init
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-- This is the "main loop"
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-- This is the "main loop"
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when IDLE =>
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when IDLE =>
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nrst <= '1';
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nrst <= '1';
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-- If this condition is true, we may safely read another byte from FT245RL's FIFO
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-- If this condition is true, we may safely read another byte from FT245RL's FIFO
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if(nrxf = '0' and data_available = '0')then
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if(nrxf = '0' and data_available = '0')then
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c_state <= READ_BYTE;
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c_state <= READ_BYTE;
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-- We have to clear 'data_available' when the client module is requesting a new byte
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-- We have to clear 'data_available' when the client module is requesting a new byte
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elsif(fetch_next_byte = '1')then
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elsif(fetch_next_byte = '1')then
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data_available <= '0';
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data_available <= '0';
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c_state <= IDLE;
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c_state <= IDLE;
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-- Well, here we simply write a byte to FT245RL's data bus
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-- Well, here we simply write a byte to FT245RL's data bus
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elsif(do_write = '1')then
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elsif(do_write = '1')then
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c_state <= WRITE_BYTE;
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c_state <= WRITE_BYTE;
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end if;
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end if;
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-- leds <= "1111";
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-- Read one byte from the device
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-- Read one byte from the device
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when READ_BYTE =>
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when READ_BYTE =>
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busy <= '1';
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busy <= '1';
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nrd <= '0';
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nrd <= '0';
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current_delay <= t3_delay;
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current_delay <= t3_delay;
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c_state <= DO_DELAY;
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c_state <= DO_DELAY;
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n_state <= READ_BYTE1;
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n_state <= READ_BYTE1;
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-- leds <= "1111";
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when READ_BYTE1 =>
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when READ_BYTE1 =>
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current_delay <= t1_delay - t3_delay;
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current_delay <= t1_delay - t3_delay;
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c_state <= DO_DELAY;
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c_state <= DO_DELAY;
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n_state <= READ_BYTE2;
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n_state <= READ_BYTE2;
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-- leds <= "1110";
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when READ_BYTE2 =>
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when READ_BYTE2 =>
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data_out <= in_buff;
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data_out <= in_buff;
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nrd <= '1';
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nrd <= '1';
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current_delay <= t5_delay;
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current_delay <= t5_delay;
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c_state <= DO_DELAY;
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c_state <= DO_DELAY;
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n_state <= READ_BYTE3;
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n_state <= READ_BYTE3;
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-- leds <= "1101";
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when READ_BYTE3 =>
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when READ_BYTE3 =>
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current_delay <= t2_delay;
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current_delay <= t2_delay;
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c_state <= DO_DELAY;
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c_state <= DO_DELAY;
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n_state <= IDLE;
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n_state <= IDLE;
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data_available <= '1';
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data_available <= '1';
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busy <= '0';
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busy <= '0';
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-- leds <= "1100";
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-- Write one byte to the device
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-- Write one byte to the device
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when WRITE_BYTE =>
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when WRITE_BYTE =>
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busy <= '1';
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busy <= '1';
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if(ntxe = '0')then
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if(ntxe = '0')then
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nwr <= '1';
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nwr <= '1';
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we <= '1';
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we <= '1';
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current_delay<= t7_delay;
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current_delay<= t7_delay;
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c_state <= DO_DELAY;
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c_state <= DO_DELAY;
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n_state <= WRITE_BYTE1;
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n_state <= WRITE_BYTE1;
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out_buff <= data_in;
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out_buff <= data_in;
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else
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else
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c_state <= WRITE_BYTE;
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c_state <= WRITE_BYTE;
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end if;
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end if;
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-- leds <= "1011";
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when WRITE_BYTE1 =>
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when WRITE_BYTE1 =>
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nwr <= '0';
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nwr <= '0';
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current_delay <= t11_delay;
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current_delay <= t11_delay;
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c_state <= DO_DELAY;
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c_state <= DO_DELAY;
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n_state <= WRITE_BYTE2;
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n_state <= WRITE_BYTE2;
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-- leds <= "1010";
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when WRITE_BYTE2 =>
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when WRITE_BYTE2 =>
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we <= '0';
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we <= '0';
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current_delay <= t12_delay;
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current_delay <= t12_delay;
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c_state <=DO_DELAY;
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c_state <=DO_DELAY;
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n_state <= WRITE_BYTE3;
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n_state <= WRITE_BYTE3;
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-- leds <= "1001";
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when WRITE_BYTE3 =>
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when WRITE_BYTE3 =>
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busy <= '0';
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busy <= '0';
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c_state <= IDLE;
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c_state <= IDLE;
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-- leds <= "1000";
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when DO_DELAY =>
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when DO_DELAY =>
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if(delay_cnt < current_delay)then
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if(delay_cnt < current_delay)then
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delay_cnt <= delay_cnt + 1;
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delay_cnt <= delay_cnt + 1;
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else
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else
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c_state <= n_state;
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c_state <= n_state;
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delay_cnt <= 0;
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delay_cnt <= 0;
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end if;
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end if;
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-- leds <= "0111";
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when others =>
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when others =>
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c_state <= INIT;
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c_state <= INIT;
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end case; -- c_state
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end case; -- c_state
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end if;
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end if;
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end process;
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end process;
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