// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \\__/ o\ (C) 2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// \/_// robfinch@finitron.ca
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// ||
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// ||
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//
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//
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// fpToPosit.v
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// fpToPosit.sv
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// - floating point to posit number convertor
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// - floating point to posit number convertor
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// - can issue every clock cycle
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// - can issue every clock cycle
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// - parameterized width
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// - parameterized width
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// - IEEE 754 representation
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// - IEEE 754 representation
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//
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//
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// Parts of this code originated from FP_to_Posit.v by Manish Kumar Jaiswal
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// Parts of this code originated from FP_to_Posit.v by Manish Kumar Jaiswal
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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// along with this program. If not, see .
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//
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//
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// ============================================================================
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// ============================================================================
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`include "positConfig.sv"
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import fp::*;
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`include "fpConfig.sv"
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import posit::*;
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`include "fpTypes.sv"
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module fpToPosit(i, o);
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module fpToPosit(i, o);
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parameter FPWID = 32;
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`include "fpSize.sv"
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`include "positSize.sv"
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input [FPWID-1:0] i;
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input [FPWID-1:0] i;
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output reg [FPWID-1:0] o;
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output reg [FPWID-1:0] o;
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parameter BIAS = {1'b0,{EMSB{1'b1}}};
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parameter BIAS = {1'b0,{EMSB{1'b1}}};
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localparam N = FPWID;
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localparam N = FPWID;
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localparam E = EMSB+1;
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localparam E = EMSB+1;
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localparam Bs = $clog2(FPWID-1);
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localparam Bs = $clog2(FPWID-1);
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// operands sign,exponent,significand
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// operands sign,exponent,significand
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wire sa;
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wire sa;
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wire [EMSB:0] xa;
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wire [EMSB:0] xa;
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wire [FMSB:0] ma;
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wire [FMSB:0] ma;
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wire [FMSB+1:0] fracta;
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wire [FMSB+1:0] fracta;
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wire adn;
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wire adn;
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wire az;
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wire az;
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wire xainf;
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wire xainf;
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wire aInf;
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wire aInf;
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wire aNan;
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wire aNan;
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fpDecomp #(FPWID) u1 (.i(i), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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fpDecomp #(.FPWID(FPWID)) u1 (.i(i), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
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assign sgno = sa;
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assign sgno = sa;
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wire [$clog2(FMSB+1):0] lzcnt;
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wire [$clog2(FMSB+1):0] lzcnt;
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generate begin : gCntlz
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generate begin : gCntlz
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case(FPWID)
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case(FPWID)
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16: begin cntlz16 u2 ({fracta,5'h1f},lzcnt); end //1-5-10
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16: begin cntlz16 u2 ({fracta,5'h1f},lzcnt); end //1-5-10
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20: begin cntlz16 u2 ({fracta,2'h3},lzcnt); end //1-6-13
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20: begin cntlz16 u2 ({fracta,2'h3},lzcnt); end //1-6-13
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32: begin cntlz32 u2 ({fracta,8'hFF},lzcnt); end // 1-8-23
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32: begin cntlz32 u2 ({fracta,8'hFF},lzcnt); end // 1-8-23
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40: begin cntlz32 u2 ({fracta,2'h3},lzcnt); end // 1-10-29
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40: begin cntlz32 u2 ({fracta,2'h3},lzcnt); end // 1-10-29
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52: begin cntlz48 u2 ({fracta,7'h7F},lzcnt); end // 1-11-40
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52: begin cntlz48 u2 ({fracta,7'h7F},lzcnt); end // 1-11-40
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64: begin cntlz64 u2 ({fracta,11'h7FF},lzcnt); end // 1-11-52
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64: begin cntlz64 u2 ({fracta,11'h7FF},lzcnt); end // 1-11-52
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80: begin cntlz80 u2 ({fracta,15'h7FFF},lzcnt); end // 1-15-64
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80: begin cntlz80 u2 ({fracta,15'h7FFF},lzcnt); end // 1-15-64
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default:
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default:
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always @*
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always @*
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begin
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begin
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$display("fpToPosit: Unsupported size");
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$display("fpToPosit: Unsupported size");
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$finish;
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$finish;
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end
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end
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endcase
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endcase
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end
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end
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endgenerate
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endgenerate
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wire [N-1:0] sig_tmp = {fracta,{E{1'b0}}} << lzcnt;
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wire [N-1:0] sig_tmp = {fracta,{E{1'b0}}} << lzcnt;
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// Convert exponent to twos complement from BIAS offset
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// Convert exponent to twos complement from BIAS offset
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wire [E:0] exp = xa - BIAS - lzcnt;
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wire [E:0] exp = xa - BIAS - lzcnt;
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wire sxp = exp[E]; // get exponent sign
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wire sxp = exp[E]; // get exponent sign
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wire [E:0] absexp = sxp ? -exp : exp; // get absolute value
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wire [E:0] absexp = sxp ? -exp : exp; // get absolute value
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wire [es-1:0] e_o = (sxp & |absexp[es-1:0]) ? exp[es-1:0] : absexp[es-1:0];
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wire [es-1:0] e_o = (sxp & |absexp[es-1:0]) ? exp[es-1:0] : absexp[es-1:0];
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wire [E-es-1:0] r_o = (~sxp || (sxp & |absexp[es-1:0])) ? {{Bs{1'b0}},absexp[E-1:es]} + 1'b1 : {{Bs{1'b0}},absexp[E-1:es]};
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wire [E-es-1:0] r_o = (~sxp || (sxp & |absexp[es-1:0])) ? {{Bs{1'b0}},absexp[E-1:es]} + 1'b1 : {{Bs{1'b0}},absexp[E-1:es]};
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// Exponent and Significand Packing
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// Exponent and Significand Packing
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wire [2*N-1:0] tmp = {{N{~sxp}},sxp,e_o,sig_tmp[N-2:es]};
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wire [2*N-1:0] tmp = {{N{~sxp}},sxp,e_o,sig_tmp[N-2:es]};
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// Including Regime bits in Exponent-Significand Packing
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// Including Regime bits in Exponent-Significand Packing
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wire [Bs-1:0] diff_b;
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wire [Bs-1:0] diff_b;
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generate begin : gDiffb
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generate begin : gDiffb
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if (E-es > Bs)
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if (E-es > Bs)
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assign diff_b = |r_o[E-es-1:Bs] ? {{(Bs-2){1'b1}},2'b01} : r_o[Bs-1:0];
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assign diff_b = |r_o[E-es-1:Bs] ? {{(Bs-2){1'b1}},2'b01} : r_o[Bs-1:0];
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else
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else
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assign diff_b = r_o;
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assign diff_b = r_o;
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end
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end
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endgenerate
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endgenerate
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wire [2*N-1:0] tmp1 = tmp >> diff_b;
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wire [2*N-1:0] tmp1 = tmp >> diff_b;
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wire [N-1:0] tmp1s = sa ? -tmp1[N-1:0] : tmp1[N-1:0];
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wire [N-1:0] tmp1s = sa ? -tmp1[N-1:0] : tmp1[N-1:0];
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always @*
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always @*
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casez({az,aInf,aNan,~sig_tmp[N-1]})
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casez({az,aInf,aNan,~sig_tmp[N-1]})
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4'b1???: o = {FPWID{1'b0}};
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4'b1???: o = {FPWID{1'b0}};
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4'b01??: o = {1'b1,{FPWID-1{1'b0}}};
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4'b01??: o = {1'b1,{FPWID-1{1'b0}}};
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4'b001?: o = {1'b1,{FPWID-1{1'b0}}};
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4'b001?: o = {1'b1,{FPWID-1{1'b0}}};
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4'b0001: o = {1'b1,{FPWID-1{1'b0}}};
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4'b0001: o = {1'b1,{FPWID-1{1'b0}}};
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default: o = {sa,tmp1s[N-1:1]};
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default: o = {sa,tmp1s[N-1:1]};
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endcase
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endcase
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endmodule
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endmodule
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